cost-effective a/d 8-bit otp mcu

Cost-Effective A/D 8-bit OTP MCU

HT46R003B

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HT46R003BCost-Effective A/D 8-bit OTP MCU


Table of Contents

Features ............................................................................................................ 5CPU Feat�res ......................................................................................................................... 5Peripheral Feat�res ................................................................................................................. 5

General Description ........................................................................................ 6Block Diagram .................................................................................................. 6Pin Assignment ................................................................................................ 6Pin Description ................................................................................................ 7Absolute Maximum Ratings ............................................................................ 8D.C. Characteristics ......................................................................................... 8A.C. Characteristics ......................................................................................... 9A/D Converter Characteristics ........................................................................ 9Power-on Reset Characteristics ................................................................... 10System Architecture ...................................................................................... 10

Clocking and Pipelining ......................................................................................................... 10Program Co�nter – PC ...........................................................................................................11Stack ..................................................................................................................................... 1�Arithmetic and Logic Unit – ALU ........................................................................................... 1�

Program Memory ........................................................................................... 13Str�ct�re ................................................................................................................................ 13Special Vectors ..................................................................................................................... 13Look-�p Table ........................................................................................................................ 13Table Program Example ........................................................................................................ 1�

RAM Data Memory ......................................................................................... 15Str�ct�re ................................................................................................................................ 15Special P�rpose Data Memory ............................................................................................. 15

Special Function Registers ........................................................................... 17Indirect Addressing Registers – IAR0� IAR1 ......................................................................... 17Memory Pointers – MP0� MP1 .............................................................................................. 17Acc�m�lator – ACC ............................................................................................................... 18Program Co�nter Low Register – PCL .................................................................................. 18Stat�s Register – STATUS .................................................................................................... 18System Control Registers – CTRL0� CTRL1 ......................................................................... �0

Oscillator ........................................................................................................ 21System Oscillator Overview .................................................................................................. �1System Clock Configurations ................................................................................................ �1Internal RC Oscillator – HIRC ............................................................................................... �1Internal 1�kHz Oscillator – LIRC ........................................................................................... �1

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Power Down Mode and Wake-up .................................................................. 22Power Down Mode ................................................................................................................ ��Standby C�rrent Considerations ........................................................................................... ��Wake-�p ................................................................................................................................ ��

Watchdog Timer ............................................................................................. 24Watchdog Timer Clock So�rce .............................................................................................. ��Watchdog Timer Control Registers ....................................................................................... ��Watchdog Timer Operation ................................................................................................... �5

Reset and Initialization .................................................................................. 26Reset F�nctions .................................................................................................................... �6Reset Initial Conditions ......................................................................................................... �8

Input/Output Ports ......................................................................................... 30Port A Wake-�p ..................................................................................................................... 31I/O Port Control Registers ..................................................................................................... 31Pin-shared F�nctions ............................................................................................................ 3�I/O Pin Str�ct�res .................................................................................................................. 33Programming Considerations ................................................................................................ 3�

Timer/Event Counter ..................................................................................... 35Configuring the Timer/Event Counter Input Clock Source .................................................... 35Timer Register – TMR ........................................................................................................... 36Timer Control Register – TMRC ............................................................................................ 36Timer Mode ........................................................................................................................... 37Event Co�nter Mode ............................................................................................................. 38P�lse Width Capt�re Mode ................................................................................................... 38Prescaler ............................................................................................................................... 3�PFD F�nction ........................................................................................................................ �0I/O Interfacing ........................................................................................................................ �0Programming Considerations ................................................................................................ �0Timer Program Example ....................................................................................................... �1Time Base ............................................................................................................................. ��

Pulse Width Modulator .................................................................................. 42PWM Operation ..................................................................................................................... ��6+� PWM Mode .................................................................................................................... ��7+1 PWM Mode .................................................................................................................... �3PWM O�tp�t Control ............................................................................................................. ��

Analog to Digital Converter ......................................................................... 45A/D Overview ........................................................................................................................ �5A/D Converter Data Registers – ADRL� ADRH ..................................................................... �5A/D Converter Control Registers – ADCR� ACSR� ADPCR .................................................. �6A/D Operation ....................................................................................................................... �8A/D Inp�t Pins ....................................................................................................................... ��S�mmary of A/D Conversion Steps ....................................................................................... ��

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Programming Considerations ................................................................................................ 50A/D Transfer F�nction ........................................................................................................... 50A/D Programming Example ................................................................................................... 51

Interrupts ........................................................................................................ 53Interr�pt Register .................................................................................................................. 53Interr�pt Operation ................................................................................................................ 5�Interr�pt Priority ..................................................................................................................... 55External Interr�pt ................................................................................................................... 56Timer/Event Co�nter Interr�pt ............................................................................................... 56A/D Converter Interr�pt ......................................................................................................... 56Time Base Interr�pt ............................................................................................................... 57Interr�pt Wake-�p F�nction ................................................................................................... 57Programming Considerations ................................................................................................ 57

Application Circuits ....................................................................................... 58Instruction Set ................................................................................................ 59

Introd�ction ........................................................................................................................... 5�Instr�ction Timing .................................................................................................................. 5�Moving and Transferring Data ............................................................................................... 5�Arithmetic Operations ............................................................................................................ 5�Logical and Rotate Operation ............................................................................................... 60Branches and Control Transfer ............................................................................................. 60Bit Operations ....................................................................................................................... 60Table Read Operations ......................................................................................................... 60Other Operations ................................................................................................................... 60

Instruction Set Summary .............................................................................. 61Table Conventions ................................................................................................................. 61

Instruction Definition ..................................................................................... 63Package Information ..................................................................................... 72

16-pin DIP (300mil) O�tline Dimensions ............................................................................... 7316-pin NSOP (150mil) O�tline Dimensions ........................................................................... 75

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Features

CPU Features• Operatingvoltage:fSYS=8MHz:2.3V~5.5V

• Upto0.5μsinstructioncyclewith8MHzsystemclockatVDD=5V

• Powerdownandwake-upfunctionstoreducepowerconsumption

• Twooscillators♦ InternalhighspeedRC–HIRC♦ Internal12kHzRC–LIRC

• Fullyintegratedinternal8MHzoscillatorrequiresnoexternalcomponents

• Allinstructionsexecutedinoneortwoinstructioncycles

• Tablereadinstruction

• 63powerfulinstructions

• 4-levelsubroutinenesting

• Bitmanipulationinstruction

Peripheral Features• ProgramMemory:1K×14

• RAMDataMemory:64×8

• WatchdogTimerfunction

• Upto14bidirectionalI/Olines

• 5-channel12-bitA/DConverter

• 1-channel8-bitPWM

• ExternalinterruptpinsharedwithI/Opin

• One8-bitprogrammableTimer/EventCounterwithoverflowinterruptandprescaler

• Time-Basefunction

• Lowvoltageresetfunction

• ProgrammableFrequencyDivider–PFD

• Packagetypes:16-pinNSOP/DIP

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General Description Thedeviceis8-bithighperformanceRISCarchitecturemicrocontrollerdevicespecificallydesignedforawiderangeofapplications.Theadvantagesoflowpowerconsumption,I/Oflexibility,timerfunctions,oscillatoroptions,HALTandwake-upfunctions,watchdogtimer,aswellas lowcost,enhancetheversatilityofthedevicetosuitforawiderangeoftheI/OandA/Dcontrolapplicationpossibilitiessuchasindustrialcontrol,consumerproductsandsubsystemcontrollers,etc.

Block Diagram

8-bitRISCMCUCore

TimeBase

A/DConverter

I/OPorts

InterruptController

ResetCircuit

Internal RCOscillators

8-bit Timer

Watchdog Timer

Low Voltage Reset

RAMData

Memory

PWM Driver

PFD Driver

OTPProgram Memory

Pin Assignment

161514131211109

12345678

HT46R003B16 NSOP-A/DIP-A

PA3/AN3PA2/AN2PA1/AN1PA0/AN0

VSSPB0PB1PB2

PA4/PWMPA5/AN4PA6/INTPA7/RESVDDPB5/PFDPB4/TMRPB3

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Pin DescriptionPin Name Function OPT I/T O/T Description

PA0/AN0PA0 PAPU

PAWU ST CMOS General p�rpose I/O. Register enabled p�ll-�p and wake-�p.

AN0 ADPCR AN — Analog inp�t channel 0

PA1/AN1PA1 PAPU



PA�/AN�PA� PAPU


AN� ADPCR AN — Analog inp�t channel �

PA3/AN3PA3 PAPU



PA�/PWMPA� PAPU


PWM CTRL0 — CMOS PWM o�tp�t

PA5/AN�PA5 PAPU


AN� ADPCR AN — Analog inp�t channel �

PA6/INTPA6 PAPU


INT INTC0CTRL1 ST — External interr�pt inp�t

PA7/RESPA7 PAWU

EXTRESB ST NMOS General p�rpose I/O. Register enabled wake-�p.

RES EXTRESB ST — Reset inp�tPB0~PB3 PB0~PB3 PBPU ST CMOS General p�rpose I/O. Register enabled p�ll-�p.

PB�/TMRPB� PBPU ST CMOS General p�rpose I/O. Register enabled p�ll-�p.TMR TMRC ST — Timer/Event co�nter inp�t

PB5/PFDPB5 PBPU ST CMOS General p�rpose I/O. Register enabled p�ll-�p.PFD CTRL0 — CMOS PFD o�tp�t

VDD VDD — PWR — Power s�pplyVSS VSS — PWR — Gro�nd

Note:I/T:Inputtype; O/T:Outputtype;OPT:Optionalbyregisteroption;PWR:Power; AN:Analogsignal;ST:SchmittTriggerinput;CMOS:CMOSoutput;NMOS:NMOSoutput

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Absolute Maximum RatingsSupplyVoltage................................................................................................VSS-0.3VtoVSS+6.0VInputVoltage.................................................................................................. VSS-0.3VtoVDD+0.3VStorageTemperature.................................................................................................... -50°Cto125°COperatingTemperature.................................................................................................. -40°Cto85°C

Note:These are stress ratingsonly.Stresses exceeding the range specifiedunder “AbsoluteMaximumRatings”maycausesubstantialdamagetothedevice.Functionaloperationofthisdeviceatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicereliability.

D.C. CharacteristicsTa=�5°C

Symbol ParameterTest Conditions

Min. Typ. Max. UnitVDD Conditions

VDD Operating voltage — fSYS=8MHz �.3 — 5.5 V

IDDOperating c�rrent(HIRC on)

3V No load� fSYS=8MHz A/D Converter disable

— 1.� 1.8 mA5V — �.� 3.6 mA

ISTB

Standby c�rrent(LIRC on)

3VNo load� System halt

— — 5 μA5V — — 10 μA

Standby c�rrent(LIRC off)

3VNo load� System halt

— — 1 μA5V — — � μA

VILInp�t Low Voltage for I/O ports� TMR� INT

5V—

0 — 1.5 V— 0 — 0.�VDD V

Inp�t low voltage for RES pin — — 0 — 0.�VDD V

VIHInp�t High Voltage for I/O ports� TMR� INT

5V—

3.5 — 5 V— 0.8VDD — VDD V

Inp�t high voltage for RES pin — — 0.�VDD — VDD V

VLVR Low Voltage Reset voltage — LVR enable� voltage select �.1V �.0 �.1 �.� V

IOH So�rce c�rrent for I/O ports3V

VOH=0.�VDD-�.5 -5 — mA

5V -5 -11 — mA

IOLSink c�rrent for I/O ports

3VVOL=0.1VDD

7.5 15 — mA5V 15 30 — mA

Sink c�rrent for PA7 pin 5V VOL=0.1VDD � 3 — mA

RPH P�ll-high resistance for I/O ports3V — �0 60 100 kΩ5V — 10 30 50 kΩ

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A.C. CharacteristicsTa=�5°C



fSYS System clock �.3V~5.5V — 8 MHz

fHIRC System clock (HIRC)

3V/5V Ta=�5°C -�% 8 +�% MHz3V/5V Ta=0°C~70°C -5% 8 +5% MHz

3.0V~5.5V Ta=0°C~70°C -8% 8 +8% MHz3.0V~5.5V Ta=-�0°C~85°C -1�% 8 +1�% MHz

fTIMER Timer I/P freq�ency (TMR) 3.3V~5.5V — 0 — 8 MHz

tWDTOSC Watchdog oscillator period3V — �5 �0 180 μs5V — 3� 65 130 μs

tRES External reset low p�lse width — — 1 — — μstRESF External reset low p�lse width (with filter) — — — 150 — nstSST System start-�p timer period — Wake-�p from halt — 16 — tSYS

tLVR Low Voltage Width to Reset — — 0.�5 1 � mstRSD System Reset Delay Time (All Reset) — — �5 50 100 ms

Note:1.tSYS=1/fSYS

2.TomaintaintheaccuracyoftheinternalHIRCoscillatorfrequency,a0.1μFdecouplingcapacitorshouldbeconnectedbetweenVDDandVSSandlocatedasclosetothedeviceaspossible.

A/D Converter CharacteristicsTa=�5°C



AVDD Analog operating voltage — VREF=VDD �.7 — 5.5 VVAD A/D Inp�t Voltage — — 0 — AVDD /VREF V

DNL A/D Differential Non-linearity�.7V

VREF=VDD=AVDD

tAD=0.5μs -� — +� LSB3V5V

INL A/D Integral non-linearity�.7V

VREF=VDD=AVDD

tAD=0.5μs -� — +� LSB3V5V

IADCAdditional Power Cons�mption if A/D Converter is �sed

3VNo load (tAD=0.5μs)

— 0.5 — mA5V — 0.6 — mA

tAD A/D Converter Clock Period �.7V~5.5V — 0.5 — 10 μs

tADCA/D Conversion Time (Incl�de Sample and Hold Time) �.7V~5.5V 1�-bit A/D Converter — 16 — tAD

tON�ST A/D Converter On-to-Start Time �.7V~5.5V — � — — μs

Note:A/Dconversiontime(tAD)=n(bitsADC)+4(samplingtime),theconversionforeachbitneedsoneADCclock(tAD).

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Power-on Reset CharacteristicsTa=�5°C



VPOR VDD Start Voltage to Ens�re Power-on Reset — — — — 100 mVRRVDD VDD Raising Rate to Ens�re Power-on Reset — — 0.035 — — V/ms

tPORMinim�m Time for VDD Stays at VPOR to Ens�re Power-on Reset — — 1 — — ms

VDD

tPOR RRVDD

VPORTime

System ArchitectureAkeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheinternalsystemarchitecture.TherangeofdevicetakeadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.Thepipeliningscheme is implemented insuchaway that instruction fetchingand instructionexecutionareoverlapped,hence instructionsareeffectivelyexecuted inonecycle,with theexceptionofbranchorcall instructions.An8-bitwideALUisusedinpracticallyalloperationsof the instructionset. Itcarriesoutarithmeticoperations, logicoperations, rotation, increment,decrement,branchdecisions,etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulatorandtheALU.Certain internal registersare implemented in theDataMemoryandcanbedirectlyor indirectlyaddressed.Thesimpleaddressingmethodsof theseregistersalongwithadditionalarchitecturalfeaturesensurethataminimumofexternalcomponentsisrequiredtoprovideafunctionalI/OandA/Dsystemwithmaximumreliabilityandflexibility.

Clocking and PipeliningThemainsystemclock,derivedfromHIRCoscillatorissubdividedintofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounter is incrementedat thebeginningof theT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryout thedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstructioncycles,thepipeliningstructureofthemicrocontrollerensuresthatinstructionsareeffectivelyexecutedinoneinstructioncycle.TheexceptiontothisareinstructionswherethecontentsoftheProgramCounterarechanged,suchassubroutinecallsor jumps, inwhichcasetheinstructionwill takeonemoreinstructioncycletoexecute.

For instructionsinvolvingbranches,suchas jumporcall instructions, twoinstructioncyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstlyobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.

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System Clocking and Pipelining

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Instruction Fetching

Program Counter – PCDuringprogramexecution, theProgramCounterisusedtokeeptrackof theaddressof thenextinstruction tobeexecuted. It isautomatically incrementedbyoneeach timean instruction isexecutedexceptforinstructions,suchas“JMP”or“CALL”thatdemandajumptoanon-consecutiveProgramMemoryaddress. Itmustbenoted thatonly the lower8bits,knownas theProgramCounterLowRegister,aredirectlyaddressablebyuser.

Whenexecuting instructions requiring jumping tonon-consecutiveaddressessuchasa jumpinstruction,asubroutinecall, interruptorreset,etc, themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.

Program Counter

High Byte of Program Low Byte of ProgramPC�~PC8 PCL7~PCL0

Thelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly.However,asonlythis lowbyteisavailableformanipulation, the jumpsare limited in thepresentpageofmemory,whichhave256locations.Whensuchprogramjumpsareexecuteditshouldalsobenotedthatadummycyclewillbeinserted.ThelowerbyteoftheProgramCounterisfullyaccessibleunderprogramcontrol.ManipulatingthePCLmightcauseprogrambranching,soanextracycleisneededtopre-fetch.

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StackThisisaspecialpartofthememorywhichisusedtosavethecontentsoftheProgramCounteronly.Thedevicestackisorganizedinto4levelsandneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.Theactivatedlevel is indexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.

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Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointerisdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresultinastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.

Arithmetic and Logic Unit – ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticor logicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:

• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA

• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA

• RotationRRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC

• IncrementandDecrementINCA,INC,DECA,DEC

• Branchdecision,JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI.

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Program MemoryTheProgramMemory is the locationwhere theusercodeorprogramisstored.Thedevice issuppliedwithOne-TimeProgrammable,OTP,memorywhereuserscanprogramtheirapplicationcode into thedevice.Byusing theappropriateprogramming tools,OTPdeviceoffersusers theflexibilitytofreelydeveloptheirapplicationswhichmaybeusefulduringdebugorforproductsrequiringfrequentupgradesorprogramchanges.

StructureTheProgramMemoryhasacapacityof1K×14bits.TheProgramMemoryisaddressedby theProgramCounterandalsocontainsdata,tableinformationandinterruptentriesinformation.Tabledata,whichcanbesetinanylocationwithintheProgramMemory,isaddressedbyseparatetablepointerregister.

000HInitialisation Vector

00�H

3FFH 1� bits

Interr�pt Vectors

010H

Look-�p Tablen00H

nFFH

Program Memory Structure

Special VectorsWithintheProgramMemory,certainlocationsarereservedfortheresetandinterrupts.Thelocation000His reserved foruseby thedevice reset forprograminitialisation.Afteradevice reset isinitiated,theprogramwilljumptothislocationandbeginexecution.

Look-up TableAnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetbyplacingtheaddressofthelookupdatatoberetrievedinthetablepointerregister,TBLP.Thisregisterdefinesthetotaladdressofthelook-uptable.

After settingup the tablepointer, the tabledatacanbe retrieved from theProgramMemoryusing the“TABRDC[m]”or“TABRDL[m]” instructions, respectively.Whenthe instruction isexecuted, the lowerorder tablebyte fromtheProgramMemorywillbe transferred to theuserdefinedDataMemoryregister[m]asspecifiedintheinstruction.ThehigherordertabledatabytefromtheProgramMemorywillbetransferredtotheTBLHspecialregister.Anyunusedbitsinthistransferredhigherorderbytewillbereadas“0”.

Theaccompanyingdiagramillustratestheaddressingdataflowofthelook-uptable.

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Table Program ExampleTheaccompanyingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthedevice.ThisexampleusesrawtabledatalocatedinthelastpagewhichisstoredthereusingtheORGstatement.ThevalueatthisORGstatementis“0300H”whichreferstothestartaddressofthelastpagewithinthe1KProgramMemoryofthemicrocontroller.

Thetablepointerissetheretohaveaninitialvalueof“06H”.ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress“0306H”or6locationsafterthestartofthelastpage.Notethatthevalueforthetablepointerisreferencedtothefirstaddressofthepresentpageifthe“TABRDC[m]”instructionisbeingused.Thehighbyteofthetabledatawhichinthiscaseisequal tozerowillbetransferredtotheTBLHregisterautomaticallywhenthe“TABRDL[m]”instructionisexecuted.

Because theTBLHregister isaread-onlyregisterandcannotberestored,careshouldbe takentoensure itsprotectionifboththemainroutineandInterruptServiceRoutineusethetablereadinstructions. Ifusing the tableread instructions, theInterruptServiceRoutinesmaychange thevalueofTBLHandsubsequentlycauseerrors ifusedagainby themainroutine.Asarule it isrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.

Table Read Program Exampletempreg1 db ? ; temporary register #1tempreg2 db ? ; temporary register #2 :mov a,06h ; initialize table pointer - note that this address ; is referencedmov tblp, a ; to the last page or present page :tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempreg1 ; data at prog. memory address “0306H” transferred to tempreg1 ; and TBLHdec tblp ; reduce value of table pointer by onetabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at prog. memory address “0305H” transferred to ; tempreg2 and TBLH ; in this example the data “1AH” is transferred to tempreg1 and ; data “0FH” to register tempreg2 ; the value “00H” will be transferred to the high byte ; register TBLH :org 0300h ; sets initial address of last pagedc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh :

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RAM Data MemoryTheDataMemoryisavolatileareaof8-bitwideRAMinternalmemoryandisthelocationwheretemporaryinformationisstored.

StructureDividedintotwosections,thefirstoftheseisanareaofRAMwherespecialfunctionregistersarelocated.Theseregistershavefixedlocationsandarenecessaryforcorrectoperationofthedevice.Manyoftheseregisterscanbereadfromandwrittentodirectlyunderprogramcontrol,however,someremainprotectedfromusermanipulation.ThesecondareaofDataMemoryisreservedforgeneralpurposeuse.All locationswithin thisareaarereadandwriteaccessibleunderprogramcontrol.

The twosectionsofDataMemory, theSpecialPurposeandGeneralPurposeDataMemoryarelocatedatconsecutivelocations.AllareimplementedinRAMandare8bitswidebutthelengthofeachmemorysectionisdictatedbythetypeofmicrocontrollerchosen.ThestartaddressoftheDataMemoryforthedeviceistheaddress“00H”.

Allmicrocontrollerprogramsrequireanareaofread/writememorywheretemporarydatacanbestoredandretrievedforuselater.ItisthisareaofRAMmemorythatisknownasGeneralPurposeDataMemory.ThisareaofDataMemoryisfullyaccessiblebytheuserprogramforbothreadingandwritingoperations.Byusingthe“SET[m].i”and“CLR[m].i”instructionsindividualbitscanbesetorresetunderprogramcontrolgivingtheuseralargerangeofflexibilityforbitmanipulationintheDataMemory.

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Data Memory StructureNote:MostoftheDataMemorybitscanbedirectlymanipulatedusingthe“SET[m].i”and“CLR

[m].i”withtheexceptionofafewdedicatedbits.TheDataMemorycanalsobeaccessedviathememorypointerregisters.

Special Purpose Data MemoryThis area ofDataMemory iswhere registers, necessary for the correct operation of themicrocontroller,arestored.Mostof theregistersarebothreadableandwriteablebutsomeareprotectedandarereadableonly,thedetailsofwhicharelocatedundertherelevantSpecialFunctionRegistersection.Notethatforlocationsthatareunused,anyreadinstructiontotheseaddresseswillreturnthevalue“00H”.

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00H01H02H03H

IAR0MP0IAR1MP1

04HACC05HPCL06H

TBLP07HTBLH08HWDTS09H

STATUS0AHINTC00BHTMR0CH

TMRC0DHINTC10EH

0FHPA10H

PAC11HPAPU12HPAWU13H

PB14HPBC15H

PBPU16H17H18H19H

CTRL01AHCTRL11BHWDTC1CH

1DHADPCR1EHPWM01FHADRL20HADRH21HADCR22HACSR23H

24H EXTRESB25H

3FH: unused, read as 00H

Special Purpose Data Memory

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Special Function RegistersToensuresuccessfuloperationofthemicrocontroller,certaininternalregistersareimplementedintheDataMemoryarea.Theseregistersensurecorrectoperationofinternalfunctionssuchastimer,interrupts,etc.,aswellasexternalfunctionssuchasI/Odatacontrol.Thelocationsoftheseregisterswithin theDataMemorybeginat theaddressof“00H”.AnyunusedDataMemory locationsbetweenthesespecialfunctionregistersandthepointwheretheGeneralPurposeMemorybeginsisreservedandattemptingtoreaddatafromtheselocationswillreturnavalueof“00H”.

Indirect Addressing Registers – IAR0, IAR1TheIndirectAddressingRegisters,IAR0andIAR1,althoughhavingtheirlocationsinnormalRAMregister,donotactuallyphysicallyexistasnormalregisters.Themethodof indirectaddressingforRAMdatamanipulationisusingtheseIndirectAddressingRegistersandMemoryPointers,incontrast todirectmemoryaddressing,wheretheactualmemoryaddress isspecified.ActionsontheIAR0andIAR1registerswillresult innoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0orMP1.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof“00H”andwritingtotheregistersindirectlywillresultinnooperation.

Memory Pointers – MP0, MP1TwoMemoryPointers, knownasMP0andMP1areprovided.TheseMemoryPointers arephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichto indirectlyaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddresswhichthemicrocontrollerisdirectedtoistheaddressspecifiedbytherelatedMemoryPointer.Notethatforthisdevice,theMemoryPointers,MP0andMP1,areboth8-bitregistersandusedtoaccesstheDataMemorytogetherwiththeircorrespondingindirectaddressingregistersIAR0andIAR1.

ThefollowingexampleshowshowtoclearasectionoffourDataMemorylocationsalreadydefinedaslocationsadres1toadres4.

Indirect Addressing Program Exampledata .section ‘data’adres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ?code. section at 0 codeorg 00hstart:mov a,04h ; set size of blockmov block,amov a,offsetadres1 ;AccumulatorloadedwithfirstRAMaddressmov mp0,a ;setmemorypointerwithfirstRAMaddressloop: clr IAR0 ;clearthedataataddressdefinedbyMP0inc mp0 ; increment memory pointersdz block ; check if last memory location has been clearedjmp loopcontinue:

Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificDataMemoryaddresses.

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Accumulator – ACCTheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuser-definedregisterandanother, it isnecessary todo thisbypassing thedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.

Program Counter Low Register – PCLToprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,howeverastheregisterisonly8-bitwideonlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.

Status Register – STATUSThis8-bitregistercontainsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationofthemicrocontroller.

WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe“CLRWDT”or“HALT”instruction.ThePDFflagisaffectedonlybyexecutingthe“HALT”or“CLRWDT”instructionorduringasystempower-up.

TheZ,OV,ACandCflagsgenerallyreflectthestatusofthelatestoperations.

Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.Notethatbits0~3oftheSTATUSregisterarebothreadableandwriteablebits.

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STATUS Register

Bit 7 6 5 4 3 2 1 0Name — — TO PDF OV Z AC CR/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 x x x x

“x”: �nknownBit7~6 Unimplemented,readas“0”Bit5 TO:WatchdogTime-Outflag

0:Afterpoweruporexecutingthe“CLRWDT”or“HALT”instruction1:Awatchdogtime-outoccurred.

Bit4 PDF:Powerdownflag0:Afterpoweruporexecutingthe“CLRWDT”instruction1:byexecutingthe“HALT”instruction

Bit3 OV:Overflowflag0:Nooverflow1:Anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa.

Bit2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero

Bit1 AC:Auxiliaryflag0:Noauxiliarycarry1:Anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction

Bit0 C:Carryflag0:Nocarryout1:Anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation

Cisalsoaffectedbyarotatethroughcarryinstruction.

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System Control Registers – CTRL0, CTRL1TheseregistersareusedtoprovidecontrolinternalfunctionssuchasthePFDfunction,thePWMfunction,externalinterruptedgetriggertypeselectionandTimeBasefunctiondivisionratio.

CTRL0 Register

Bit 7 6 5 4 3 2 1 0Name — — PWMSEL — PWMC PFDC — —R/W — — R/W — R/W R/W — —POR — — 0 — 0 0 — —

Bit7~6 Unimplemented,readas"0"Bit5 PWMSEL:PWMtypeselection

0:6+21:7+1

Bit4 Unimplemented,readas"0"Bit3 PWMC:I/OorPWMselection

0:PA41:PWM

Bit2 PFDC:I/OorPFDselection0:PB51:PFD

Bit1~0 Unimplemented,readas"0"

CTRL1 Register

Bit 7 6 5 4 3 2 1 0Name INTES1 INTES0 TBSEL1 TBSEL0 — — — —R/W R/W R/W R/W R/W — — — —POR 1 0 0 0 — — — —

Bit7~6 INTES1~INTES0:Externalinterruptedgetypeselection00:Disable01:Risingedgetrigger10:Fallingedgetrigger11:Dualedgetrigger

Bit5~4 TBSEL1~TBSEL0:Timebaseperiodselection00:210×(1/fS)01:211×(1/fS)10:212×(1/fS)11:213×(1/fS)

Bit3~0 Unimplemented,readas"0"

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OscillatorVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplication requirements.The flexible featuresof theoscillator functionsensure that thebestoptimizationcanbeachievedintermsofspeedandpowersaving.

System Oscillator OverviewInadditiontobeingthesourceofthemainsystemclocktheoscillatorsalsoprovideclocksourcesfortheWatchdogTimerfunction,PWMfunction,Timer/EventcounterandTimeBase.

Type Name Freq.Internal High Speed RC HIRC 8MHzInternal Low Speed RC LIRC 1�kHz

Oscillator Types

System Clock ConfigurationsThereisonesystemoscillatorimplementedinthedevice,internal8MHzRC,HIRC.Alsothereisaninternal12kHzRCoscillatorLIRCusedastheclocksourcefortheWDTfunction,PWMfunction,Timer/EventcounterandTimeBase.Moredetailsaredescribedintheaccompanysections.

Internal RC Oscillator – HIRCTheinternalRCoscillatorisafullyintegratedsystemoscillatorrequiringnoexternalcomponents.TheinternalRCoscillatorhasthefrequencyof8MHz.Devicetrimmingduringthemanufacturingprocessand the inclusionof internal frequencycompensationcircuit isused toensure that theinfluenceof thepower supplyvoltage, temperatureandprocessvariationson theoscillationfrequencyareminimized.Notethatthisinternalsystemclockoptionrequiresnoexternalpinsforitsoperation.RefertotheA.C.Characteristicsformorefrequencyaccuracydetails.

Internal 12kHz Oscillator – LIRCTheLIRCisafullyself-containedfreerunningon-chipRCoscillatorwithatypicalfrequencyof12kHzat5V,requiringnoexternalcomponentsforitsimplementation.WhenthedeviceenterstheSleepMode,thesystemclockwillstoprunningbuttheLIRCoscillatorcontinuestofree-runandtokeepthewatchdogactive.However,topreservepowerincertainapplicationstheLIRCcanbedisabledbydisablingtheWDTfunction,PWMfunction,Timer/EventcounterandTimeBaseinthehaltmode.

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Power Down Mode and Wake-up

Power Down ModeAlloftheHoltekmicrocontrollershavetheabilitytoenteraPowerDownMode,alsoknownastheHALTModeorSleepMode.Whenthedeviceentersthismode,thenormaloperatingcurrentwillbereducedtoanextremelylowstandbycurrentlevel.ThisoccursbecausewhenthedeviceentersthePowerDownMode, thesystemoscillator isstoppedwhichreduces thepowerconsumptiontoextremelylowlevels.However,asthedevicemaintainsitspresentinternalcondition, theycanbewokenupata laterstageandcontinuerunning,withoutrequiringafullreset.Thisfeature isextremelyimportantinapplicationareaswheretheMCUsmusthavetheirpowersupplyconstantlymaintainedtokeepthedeviceinaknowncondition.

Entering the Power Down ModeThere isonlyonewayfor thedevice toenter thePowerDownModeandthat is toexecute the“HALT”instructionintheapplicationprogram.Whenthisinstructionisexecuted,thefollowingwilloccur:

• Thesystemoscillatorwillstoprunningandtheapplicationprogramwillstopat the“HALT”instruction.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheWDTwillbeclearedandresumecounting.

• TheI/Oportswillmaintaintheirpresentcondition.

Inthestatusregister, thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.

Standby Current ConsiderationsAs themain reason for entering theSleepMode is tokeep the current consumptionof theMCUtoas lowavalueaspossible,perhapsonly in theorderofseveralmicro-amps, thereareotherconsiderationswhichmustalsobe takenintoaccountby thecircuitdesigner if thepowerconsumptionistobeminimized.

SpecialattentionmustbemadetotheI/Opinsonthedevice.Allhigh-impedanceinputpinsmustbeconnected toeitherafixedhighor lowlevelasanyfloating inputpinscouldcreate internaloscillationsandresult in increasedcurrentconsumption.Caremustalsobetakenwiththeloads,whichareconnectedtoI/Opins,whicharesetasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrent isdrawnorconnectedonlytoexternalcircuits thatdonotdrawcurrent,suchasotherCMOSinputs.

Wake-upAfterthesystementerstheSleepMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:

• Anexternalreset

• AnexternalfallingedgeonPortA

• Asysteminterrupt

• AWDToverflow

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If thesystemiswokenupbyanexternal reset, thedevicewillexperiencea full systemreset,however,ifthedeviceiswokenupbyaWDToverflow,aWatchdogTimerresetwillbeinitiated.Althoughbothof thesewake-upmethodswill initiatearesetoperation, theactualsourceof thewake-upcanbedeterminedbyexaminingtheTOandPDFflags.ThePDFflag isclearedbyasystempower-uporexecutingtheclearWatchdogTimerinstructionsandissetwhenexecutingthe“HALT”instruction.TheTOflagissetifaWDTtime-outoccurs,andcausesawake-upthatonlyresetstheProgramCounterandStackPointer,theotherflagsremainintheiroriginalstatus.

PinsPA0~PA7canbesetviathePAWUregistertopermitanegativetransitiononthepintowake-upthe system.WhenaPA0~PA7pinwake-upoccurs, theprogramwill resumeexecutionat theinstructionfollowingthe“HALT”instruction.

Ifthesystemiswokenupbyaninterrupt,thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterrupt isdisabledor theinterrupt isenabledbut thestackisfull, inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.Inthissituation,theinterruptwhichwoke-upthedevicewillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelated interrupt isfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.IfaninterruptrequestflagissethighbeforeenteringtheSLEEPMode,thewake-upfunctionoftherelatedinterruptwillbeignored.

Nomatterwhatthesourceofthewake-upeventis,onceawake-upeventoccurs, therewillbeatimedelaybeforenormalprogramexecutionresumes.Consultthetablefortherelatedtime

Wake-up SourceOscillator Type

HIRC, LIRCExternal RES tRSTD + tSST

PA PorttSSTInterr�pt

WDT Overflow

Note:1.tRSTD(resetdelaytime),tSYS(systemclock)2.tRSTDispower-ondelay,typicaltime=50ms3.tSST=16tSYS

Wake-up Delay Time

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Watchdog TimerTheWatchdogTimer,alsoknownas theWDT, isprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.

Watchdog Timer Clock SourceTheWatchdogTimerclocksourceisprovidedbytheLIRCoscillator, thesystemclockfSYSanditsdivisionclockfSYS/4,whicharesourcedfromtheHIRCoscillator.TheWatchdogTimersourceclockisthensubdividedbyaratioof28to215togivelongertimeouts,theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTSregister.TheLIRCinternaloscillatorhasanapproximateperiodfrequencyof12kHzatasupplyvoltageof5V.However,itshouldbenotedthatthisspecifiedinternalclockperiodcanvarywithVDD,temperatureandprocessvariations.

Watchdog Timer Control Registers

WDTS Register

Bit 7 6 5 4 3 2 1 0Name — — — — — WS� WS1 WS0R/W — — — — — R/W R/W R/WPOR — — — — — 1 1 1

Bit7~3 Unimplemented,readas“0”Bit2~0 WS2~WS0:WDTTime-outperiodselection

000:28/fS

001:28/fS

010:210/fS

011:211/fS

100:212/fS

101:213/fS

110:214/fS

111:215/fS

These threebitsdetermine thedivisionratioof theWatchdogTimersourceclock,whichinturndeterminesthetimeoutperiod.

WDTC Register

Bit 7 6 5 4 3 2 1 0Name WDTCLS1 WDTCLS0 WDTEN5 WDTEN� WDTEN3 WDTEN� WDTEN1 WDTEN0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 WDTCLS1~WDTCLS0:WDT/Timer/PWM/Timebaseclocksource00:fLIRC01:fSYS/410:fSYS

11:fSYS

Bit5~0 WDTEN5~WDTEN0:WDTenablecontrol000000:Enable101101:DisableOthervalues:MCUreset

Whenthesebitsarechangedbytheenvironmentalnoisetoresetthemicrocontroller,theresetoperationwillbeactivatedafter2~3LIRCclockcycles.

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Watchdog Timer OperationTheWatchdogTimeroperatesbyprovidingadeviceresetwhenits timeroverflows.ThismeansthatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallycleartheWatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisisdoneusingtheclearwatchdoginstruction.NotethatiftheWatchdogTimerfunctionisnotenabled,thenanyinstructionrelatedtotheWatchdogTimerwillresultinnooperation.

SettingthevariousWatchdogTimeroptionsarecontrolledvia the internalregistersWDTCandWDTS.EnablingtheWatchdogTimercanbecontrolledbytheWDTENnbitsintheinternalWDTCregisterintheDataMemory.TheWatchdogTimerwillbedisabledifbitsWDTEN5~WDTEN0intheWDTCregisterarewrittenwiththebinaryvalue101101BwhiletheWDTTimerwillbeenabledifthesebitsarewrittenwiththebinaryvalue000000B.Ifthesebitsarewrittenwiththeothervaluesexcept000000Band101101B,theMCUwillbereset.

TheWatchdogTimer clock can emanate from three different sources, selected by theWDTCLS1~WDTCLS0bits in theWDTCregister.ThesesourcesarefSYS, fSYS/4orLIRC.It isimportanttonotethatwhenthesystementerstheSleepModethesystemclockisstopped,thereforeifithasselectedfSYSorfSYS/4astheWatchdogTimerclocksource,theWatchdogTimerwillstop.Forsystemsthatoperate innoisyenvironments, it’srecommendedtouse theLIRCas theclocksource.Thedivisionratiooftheprescalerisdeterminedbybits0,1and2oftheWDTSregister,knownasWS0,WS1andWS2.If theWatchdogTimerinternalclocksourceisselectedandwiththeWS0,WS1andWS2bitsoftheWDTSregisterallsethigh,theprescalerdivisionratiowillbe1:32768,whichwillgiveamaximumtime-outperiod.

Undernormalprogramoperation,aWatchdogTimertime-outwillinitializeadeviceresetandsetthestatusbitTO.However,if thesystemisintheSleepMode,whenaWatchdogTimertime-outoccurs,thedevicewillbewokenup,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointerwillbereset.FourmethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.ThefirstisaWDTsoftwarereset,whichmeansacertainvalueexcept000000Band101101BwrittenintotheWDTEN5~WDTEN0bitfiled, thesecondisanexternalhardwarereset,whichmeansalowlevelontheexternalresetpin,thethirdisusingtheClearWatchdogTimersoftwareinstructionsandthefourthisviaa“HALT”instruction.

ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistousethe“CLRWDT”instructiontocleartheWDT.

“CLR WDT”Instruction

8-stage Divider WDT Prescaler

WDTEN5~WDTEN0 bitsWDTC Register Reset MCU

S/W Control

fS fS/28

8-to-1 MUX

CLR

WS2~WS0(fS/28 ~ fS/215)

WDT Time-out(28/fS ~ 215/fS)

fSYS/4

fSYS

fLIRC

WDTCLS1~WDTCLS0

RES pin reset“HALT”Instruction

Watchdog Timer

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Reset and InitializationAresetfunctionisafundamentalpartofanymicrocontrollerensuringthat thedevicecanbesettosomepredeterminedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawelldefinedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.

Inadditiontothepower-onreset,situationsmayarisewhereit isnecessarytoforcefullyapplyaresetconditionwhenthemicrocontrollerisrunning.Oneexampleofthisiswhereafterpowerhasbeenappliedandthemicrocontrollerisalreadyrunning,theRESlineisforcefullypulledlow.Insuchacase,knownasanormaloperationreset,someofthemicrocontrollerregistersremainunchangedallowingthemicrocontrollertodealwithnormaloperationaftertheresetlineisallowedtoreturnhigh.AnothertypeofresetiswhentheWatchdogTimeroverflowsandresetsthemicrocontroller.Alltypesofresetoperationsresultindifferentregisterconditionsbeingset.

AnotherresetexistsintheformofaLowVoltageReset,LVR,whereafullreset,similartotheRESresetisimplementedinsituationswherethepowersupplyvoltagefallsbelowacertainthreshold.

Reset FunctionsThereare fiveways inwhichamicrocontroller resetcanoccur, througheventsoccurringbothinternallyandexternally:

Power-on ResetThemostfundamentalandunavoidablereset is theonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensures thatcertainother registersarepreset toknownconditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuringthatallpinswillbefirstsettoinputs.

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Note:tRSTDispower-ondelay,typicaltime=50msPower-On Reset Timing Chart

RES Pin ResetAlthoughthemicrocontrollerhasaninternalRCresetfunction,iftheVDDpowersupplyrisetimeisnot fastenoughordoesnotstabilizequicklyatpower-on, the internalreset functionmaybeincapableofprovidingproperresetoperation.Forthisreasonit isrecommendedthatanexternalRCnetworkisconnectedtotheRESpin,whoseadditionaltimedelaywillensurethattheRESpinremainslowforanextendedperiodtoallowthepowersupplytostabilize.Duringthistimedelay,normaloperationof themicrocontrollerwillbe inhibited.After theRES line reachesacertainvoltagevalue,theresetdelaytimetRSTDisinvokedtoprovideanextradelaytimeafterwhichthemicrocontrollerwillbeginnormaloperation.TheabbreviationSSTinthefiguresstandsforSystemStart-upTimer.

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FormostapplicationsaresistorconnectedbetweenVDDandtheRESpinandacapacitorconnectedbetweenVSSandtheRESpinwillprovideasuitableexternalresetcircuit.AnywiringconnectedtotheRESpinshouldbekeptasshortaspossibletominimizeanystraynoiseinterference.

Forapplicationsthatoperatewithinanenvironmentwheremorenoiseispresent theresetcircuitshownisrecommended.

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Note:“*’ItisrecommendedthatthiscomponentisaddedforaddedESDprotection.“**”Itisrecommendedthatthiscomponentisaddedinenvironmentswherepowerlinenoiseissignificant.

External RES Circuit

MoreinformationregardingexternalresetcircuitsislocatedinApplicationNoteHA0075EontheHoltekwebsite.

ThistypeofresetoccurswhenthemicrocontrollerisalreadyrunningandtheRESpinisforcefullypulledlowbysoftwarecontrolusingtheregisterEXTRESB.Inthiscaseofotherreset,theProgramCounterwillresettozeroandprogramexecutioninitiatedfromthispoint.

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Note:tRSTDispower-ondelay,typicaltime=50msRES Reset Timing Chart

• EXTRESB Register

Bit 7 6 5 4 3 2 1 0Name — — — RESBEN� RESBEN3 RESBEN� RESBEN1 RESBEN0R/W — — — R/W R/W R/W R/W R/WPOR — — — 0 0 0 0 0

Bit7~5 Unimplemented,readas“0”Bit4~0 RESBEN4~RESBEN0:PA7/RESselection

00000:PA710101:RESOthervalues:MCUreset

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Low Voltage Reset – LVRThemicrocontrollercontainsalowvoltageresetcircuit inordertomonitorthesupplyvoltageofthedevice.Thisvoltageisfixedat2.1V(VLVR).Ifthesupplyvoltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingabattery,theLVRwillautomaticallyresetthedeviceinternally.

TheLVRincludesthefollowingspecifications:ForavalidLVRsignal,alowvoltage,i.e.,avoltagein therangebetween0.9V~VLVRmustexist forgreater than thevalue tLVRspecified in theA.C.characteristics.If thelowvoltagestatedoesnotexceedtLVR, theLVRwill ignoreitandwillnotperformaresetfunction.NotethattheLVRfunctionwillautomaticallybedisabledwhentheMCUentersthePowerDownMode.

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Note:tRSTDispower-ondelay,typicaltime=50msLow Voltage Reset Timing Chart

Watchdog Time-out Reset during Normal OperationTheWatchdogtime-outResetduringnormaloperation is thesameasahardwareRESpinresetexceptthattheWatchdogtime-outflagTOwillbesetto“1”.

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Note:tRSTDispower-ondelay,typicaltime=50msWDT Time-out Reset during Normal Operation Timing Chart

Watchdog Time-out Reset during Sleep ModeTheWatchdogtime-outResetduringSleepModeisalittledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedto“0”andtheTOflagwillbesetto“1”.RefertotheA.C.CharacteristicsfortSSTdetails.

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Note:tSSTis16clockcyclesforthesystemclocksourceisprovidedbyHIRC.WDT Time-out Reset during Sleep Timing Chart

Reset Initial ConditionsThedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchastheSleepModefunctionorWatchdogTimer.Theresetflagsareshowninthetable:

TO PDF RESET Conditions0 0 Power-on reset� � RES or LVR reset d�ring NORMAL Mode operation1 � WDT time-o�t reset d�ring NORMAL Mode operation1 1 WDT time-o�t reset d�ring Sleep Mode operation

Note: “�” stands for �nchanged

Rev. 1.00 �8 ��ne 1�� 01� Rev. 1.00 �� ne 1�� 01�



Thefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.

Item Condition After RESETProgram Co�nter Reset to zeroInterr�pts All interr�pts will be disabledWDT Clear after reset� WDT begins co�ntingTimer/Event Co�nter Timer Co�nter will be t�rned offPrecaler The Timer Co�nter Prescaler will be clearedInp�t/O�tp�t Ports I/O ports will be set as inp�tsStack Pointer Stack Pointer will point to the top of the stack

Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontrolleris inafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectsthemicrocontrollerinternalregisters.

Register Reset(Power On)

RES Reset(Normal Operation)

RES Reset(HALT)

WDT Time-out(Normal Operation)

WDT Time-out(HALT)

Program Co�nter 0 0 0 H 0 0 0 H 0 0 0 H 0 0 0 H 0 0 0 HMP0 1 x x x x x x x 1 � � � � � � � 1 � � � � � � � 1 � � � � � � � 1 � � � � � � �MP1 1 x x x x x x x 1 � � � � � � � 1 � � � � � � � 1 � � � � � � � 1 � � � � � � �ACC x x x x x x x x � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �TBLP x x x x x x x x � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �TBLH - - x x x x x x - - � � � � � � - - � � � � � � - - � � � � � � - - � � � � � �WDTS - - - - - 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 - - - - - � � �STATUS - - 0 0 x x x x - - � � � � � � - - 0 1 � � � � - - 1 � � � � � - - 1 1 � � � �INTC0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - � � � � � � �TMR x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x � � � � � � � �TMRC 0 0 - 0 1 0 0 0 0 0 - 0 1 0 0 0 0 0 - 0 1 0 0 0 0 0 - 0 1 0 0 0 � � - � � � � �INTC1 - - - 0 - - - 0 - - - 0 - - - 0 - - - 0 - - - 0 - - - 0 - - - 0 - - - � - - - �PA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �PAC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �PAWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PAPU - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - � � � � � � �PB - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - � � � � � �PBC - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - � � � � � �PBPU - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - � � � � � �CTRL0 - - 0 - 0 0 - - - - 0 - 0 0 - - - - 0 - 0 0 - - - - 0 - 0 0 - - - - � - � � - -CTRL1 1 0 0 0 - - - - 1 0 0 0 - - - - 1 0 0 0 - - - - 1 0 0 0 - - - - � � � � - - - -WDTC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADPCR - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - � � � � �PWM0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x � � � � � � � �ADRL x x x x - - - - x x x x - - - - x x x x - - - - x x x x - - - - � � � � - - - -ADRH x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x � � � � � � � �ADCR 0 1 - - - 0 0 0 0 1 - - - 0 0 0 0 1 - - - 0 0 0 0 1 - - - 0 0 0 � � - - - � � �ACSR 1 0 - - - 0 0 0 1 0 - - - 0 0 0 1 0 - - - 0 0 0 1 0 - - - 0 0 0 1 � - - - � � �EXTRESB - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - � � � � �

Note:“-”notimplement“u”means“unchanged”“x”means“unknown”

Rev. 1.00 30 ��ne 1�� 01� Rev. 1.00 31 ��ne 1�� 01�



Input/Output PortsHoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Mostpinscanhaveeitheraninputoroutputdesignationunderuserprogramcontrol.Additionally,astherearepull-highresistorsandwake-upsoftwareconfigurations,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.

Thedeviceprovidesbidirectionalinput/outputlineslabeledwithportnamesPAandPB.TheseI/OportsaremappedtotheRAMDataMemorywithspecificaddressesasshownintheSpecialPurposeDataMemorytable.Allof theseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction“MOVA,[m]”,wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.

Register Name

Bit

7 6 5 4 3 2 1 0PA PA7 PA6 PA5 PA� PA3 PA� PA1 PA0

PAC PAC7 PAC6 PAC5 PAC� PAC3 PAC� PAC1 PAC0PAPU — PAPU6 PAPU5 PAPU� PAPU3 PAPU� PAPU1 PAPU0PAWU PAWU7 PAWU6 PAWU5 PAWU� PAWU3 PAWU� PAWU1 PAWU0

PB — — PB5 PB� PB3 PB� PB1 PB0PBC — — PBC5 PBC� PBC3 PBC� PBC1 PBC0

PBPU — — PBPU5 PBPU� PBPU3 PBPU� PBPU1 PBPU0

I/O Registers List

Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternal resistor.Toeliminate theneedfor theseexternal resistors,all I/Opins,whenconfiguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.Thesepull-highresistorsareselectedusingaregistersPAPUandPBPUlocatedintheDataMemory.Thepull-highresistorsareimplementedusingweakPMOStransistors.NotethatpinPA7doesnothaveapull-highresistorselection.

PAPU Register

Bit 7 6 5 4 3 2 1 0Name — PAPU6 PAPU5 PAPU� PAPU3 PAPU� PAPU1 PAPU0R/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas"0"Bit6~0 PAPU6~PAPU0:PortAbit6~bit0pull-highcontrol

0:Disable1:Enable

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PBPU Register

Bit 7 6 5 4 3 2 1 0Name — — PBPU5 PBPU� PBPU3 PBPU� PBPU1 PBPU0R/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

Bit7~6 Unimplemented,readas"0"Bit5~0 PBPU5~PBPU0:PortBbit5~bit0pull-highcontrol

0:Disable1:Enable

Port A Wake-upIftheHALTinstructionisexecuted,thedevicewillentertheSleepMode,wherethesystemclockwillstopresultinginpowerbeingconserved,afeaturethatisimportantforbatteryandotherlow-powerapplications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePA0~PA7pinsfromhightolow.AfteraHALTinstructionforcesthemicrocontrollerintoenteringtheSleepMode,theprocessorwillremaininalow-powerstateuntilthelogicconditionoftheselectedwake-uppinonPortAchangesfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.NotethatpinsPA0~PA7canbeselectedindividuallytohavethiswake-upfeatureusinganinternalregisterknownasPAWU,locatedintheDataMemory.

PAWU Register

Bit 7 6 5 4 3 2 1 0Name PAWU7 PAWU6 PAWU5 PAWU� PAWU3 PAWU� PAWU1 PAWU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 PAWU7~PAWU0:PortAbit7~bit0wake-upcontrol0:Disable1:Enable

I/O Port Control RegistersEachporthas itsowncontrol registerknownasPAC,PBC,whichcontrol the input/outputconfiguration.With thiscontrolregister,eachI/Opinwithorwithoutpull-highresistorscanbereconfigureddynamicallyunder softwarecontrol.For the I/Opin to functionasan input, thecorrespondingbitof thecontrolregistermustbewrittenasa“1”.Thiswill thenallowthelogicstateoftheinputpintobedirectlyreadbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa“0”,theI/OpinwillbesetasaCMOSoutput.Ifthepiniscurrentlysetasanoutput,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.

PAC Register

Bit 7 6 5 4 3 2 1 0Name PAC7 PAC6 PAC5 PAC� PAC3 PAC� PAC1 PAC0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 1 1 1 1 1 1

Bit7~0 PAC7~PAC0:PortAbit7~bit0Input/Outputcontrol0:Output1:Input

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PBC Register

Bit 7 6 5 4 3 2 1 0Name — — PBC5 PBC� PBC3 PBC� PBC1 PBC0R/W — — R/W R/W R/W R/W R/W R/WPOR — — 1 1 1 1 1 1

Bit7~6 Unimplemented,readas"0"Bit5~0 PBC5~PBC0:PortBbit5~bit0Input/Outputcontrol

0:Output1:Input

Pin-shared FunctionsTheflexibilityofthemicrocontrollerrangeisgreatlyenhancedbytheuseofpinsthathavemorethanonefunction.Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyofthesedifficultiescanbeovercome.Forsomepins,thechosenfunctionofthemulti-functionI/Opinsissetbyapplicationprogramcontrol.

• ExternalInterruptInputTheexternal interruptpin, INT, ispin-sharedwithanI/Opin.Touse thepinasanexternalinterruptinputthecorrectbitsintheINTC0registermustbeprogrammed.ThepinmustalsobesetasaninputbysettingthePAC6bitinthePortControlRegister.Apull-highresistorcanalsobeselectedviatheappropriateportpull-highresistorregister.NotethatevenifthepinissetasanexternalinterruptinputtheI/Ofunctionstillremains.

• ExternalTimer/EventCounterInputTheTimer/EventCounterpinTMRispin-sharedwithI/OpinsForthissharedpintobeusedasTimer/EventCounterinput, theTimer/EventCountermustbeconfiguredtobeintheEventCounterorPulseWidthCaptureMode.Thisisachievedbysettingtheappropriatebits intheTimer/EventCounterControlRegister.Thepinmustalsobesetasinputbysettingtheappropriatebit in thePortControlRegister.Pull-highresistoroptionscanalsobeselectedusingtheportpull-highresistor registers.Note thateven if thepin issetasanexternal timer input theI/Ofunctionstillremains.

• PFDOutputThePFDfunctionoutputispin-sharedwithanI/Opin.TheoutputfunctionofthispinischosenusingtheCTRL0register.Notethat thecorrespondingbitof theportcontrolregistermustbesetthepinasanoutputtoenablethePFDoutput.Iftheportcontrolregisterhassetthepinasaninput,thenthepinwillfunctionasanormallogicinputwiththeusualpull-highselection,evenifthePFDfunctionhasbeenselected.

• PWMOutputForthedevicethePWMfunctionisincluded.ThePWMfunctionwhoseoutputsarepin-sharedwithI/Opins.ThePWMoutputfunctionsarechosenusingtheCTRL0register.Notethat thecorrespondingbitoftheportcontrolregisters,fortheoutputpin,mustsetupthepinasanoutputtoenablethePWMoutput.Ifthepinsaresetupasinputs,thenthepinwillfunctionasanormallogicinputwiththeusualpull-highselections,evenifthePWMregistershaveenabledthePWMfunction.

Rev. 1.00 3� ��ne 1�� 01� Rev. 1.00 33 ��ne 1�� 01�



• A/DIutputThedevicehasfiveinputstotheA/Dconverter.Alloftheseanaloginputsarepin-sharedwithI/Opins.IfthesepinsaretobeusedasA/DinputsandnotasI/Opins,thenthecorrespondingPCRnbitsintheA/Dconvertercontrolregister,ADPCR,mustbeproperlysetup.IfchosenasI/Opins,thenfullpull-highresistorcontrolremains,howeverifusedasA/Dinputsthenanypull-highresistorcontrolassociatedwiththesepinswillbeautomaticallydisconnected.

I/O Pin StructuresThe accompanyingdiagrams illustrate the I/Opin internal structures.As the exact logicalconstructionof theI/Opinmaydifferfromthesedrawings, theyaresuppliedasaguideonlytoassistwiththefunctionalunderstandingoftheI/Opins.

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Generic Input/Output Ports

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PA7 NMOS Input/Output Port

Rev. 1.00 3� ��ne 1�� 01� Rev. 1.00 35 ��ne 1�� 01�



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A/D Input/Output Port

Programming ConsiderationsWithintheuserprogram,oneofthethingsfirst toconsiderisport initialization.Afterareset,allof theI/Odataandportcontrolregisterswillbeset tohigh.ThismeansthatallI/Opinswillbedefaultedtoaninputstate,thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.Iftheportcontrolregistersarethenprogrammedtosetsomepinsasoutputs, theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedportdataregistersarefirstprogrammed.Selectingwhichpinsareinputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvalues into theappropriateportcontrolregisterorbyprogrammingindividualbits in theportcontrolregisterusingthe“SET[m].i”and“CLR[m].i”instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.

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Read Modify Write Timing

PinsPA0~PA7eachhavewake-upfunctions,selectedviathePAWUregister.WhenthedeviceisintheSleepMode,variousmethodsareavailabletowakethedeviceup.Oneoftheseisahightolowtransitionofanypins.SingleormultiplepinsonPortAcanbesettohavethisfunction.

Rev. 1.00 3� ��ne 1�� 01� Rev. 1.00 35 ��ne 1�� 01�



Timer/Event CounterTheprovisionoftimerformanimportantpartofanymicrocontroller,givingthedesignerameansofcarryingouttimerelatedfunctions.Thedevicecontainsfroman8-bitcount-uptimer.Asthetimerhasthreedifferentoperatingmodes,theycanbeconfiguredtooperateasageneraltimer,anexternaleventcounterorasapulsewidthcapturedevice.Theprovisionofaninternalprescalertotheclockcircuitryongivesaddedrangetothetimer.

Thereare twotypesofregistersrelatedto theTimer/EventCounter.Thefirst is theregister thatcontainstheactualvalueofthetimerandintowhichaninitialvaluecanbepreloaded.ReadingfromthisregisterretrievesthecontentsoftheTimer/EventCounter.Thesecondtypeofassociatedregisteris theTimerControlRegisterwhichdefinesthetimeroptionsanddetermineshowthetimeris tobeused.Thedevicecanhavethetimerclockconfiguredtocomefromtheinternalclocksource.Inaddition,thetimerclocksourcecanalsobeconfiguredtocomefromanexternaltimerpin.

Configuring the Timer/Event Counter Input Clock SourceTheTimer/EventCounterclocksourcecanoriginatefromvarioussources,aninternalclockoranexternalpin.Theinternalclocksourceisusedwhenthetimerisinthetimermode.FortheTimer/EventCounter,thisinternalclocksourceisfirstdividedbyaprescaler,thedivisionratioofwhichisconditionedbytheTimerControlRegisterbitsTPSC2~TPSC0.TheinternalclocksourcecanbederivedfromthesystemclockfSYSorfromtheinstructionclockfSYS/4ortheinternallowspeedoscillatorLIRCforTimer/EventCounterselectedbytheclockselectionbitsWDTCLS1~WDTCLS0intheregisterWDTC.

AnexternalclocksourceisusedwhentheTimer/EventCounterisintheeventcountingmode,theclocksourcebeingprovidedonanexternaltimerpinTMR.DependingupontheconditionoftheTEGbit,eachhightolow,or lowtohightransitionontheexternal timerpinwill increment thecounterbyone.

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Rev. 1.00 36 ��ne 1�� 01� Rev. 1.00 37 ��ne 1�� 01�



Timer Register – TMRThetimerregisterisspecialfunctionregisterlocatedintheSpecialPurposeDataMemoryandistheplacewheretheactualtimervalueisstored.TheregisterisknownasTMR.Thevalueinthetimerregisterincreasesbyoneeachtimeaninternalclockpulseisreceivedoranexternaltransitionoccursontheexternaltimerpin.ThetimerwillcountfromtheinitialvalueloadedbythepreloadregistertothefullcountofFFHatwhichpointthetimeroverflowsandaninternalinterruptsignalisgenerated.Thetimervaluewillthenresetwiththeinitialpreloadregistervalueandcontinuecounting.

NotethattoachieveamaximumfullrangecountofFFH,thepreloadregistermustfirstbecleared.Itshouldbenotedthatafterpower-on,thepreloadregisterwillbeinanunknowncondition.Notethat if theTimer/EventCounteris inanOFFconditionanddataiswrittentoitspreloadregister,thisdatawillbeimmediatelywrittenintotheactualcounter.However,ifthecounterisenabledandcounting,anynewdatawrittenintothepreloaddataregisterduringthisperiodwillremaininthepreloadregisterandwillonlybewrittenintotheactualcounterthenexttimeanoverflowoccurs.

Timer Control Register – TMRCTheflexiblefeaturesoftheHoltekmicrocontrollerTimer/EventCounterenableittooperateinthreedifferentmodes, theoptionsofwhicharedeterminedbythecontentsof their respectivecontrolregister.

TheTimerControlRegisterisknownasTMRC.ItistheTimerControlRegistertogetherwithitscorresponding timerregister thatcontrols thefulloperationof theTimer/EventCounter.Beforethetimercanbeused,it isessentialthattheTimerControlRegisterisfullyprogrammedwiththerightdata toensure itscorrectoperation,aprocess that isnormallycarriedoutduringprograminitialization.

Toselectwhichofthethreemodesthetimeris tooperatein,eitherinthetimermode, theeventcountingmodeorthepulsewidthcapturemode,bits7and6oftheTimerControlRegister,whichareknownasthebitpairTM1/TM0,mustbesettotherequiredlogiclevels.Thetimer-onbit,whichisbit4oftheTimerControlRegisterandknownasTON,providesthebasicon/offcontroloftherespectivetimer.Settingthebittohighallowsthecountertorun.Clearingthebitstopsthecounter.Bits0~2oftheTimerControlRegisterdeterminethedivisionratiooftheinputclockprescaler.Theprescalerbitsettingshavenoeffectifanexternalclocksourceisused.Ifthetimerisintheeventcountorpulsewidthcapturemode,theactivetransitionedgeleveltypeisselectedbythelogiclevelofbit3oftheTimerControlRegisterwhichisknownasTEG.

TMRC Register

Bit 7 6 5 4 3 2 1 0Name TM1 TM0 — TON TEG TPSC� TPSC1 TPSC0R/W R/W R/W — R/W R/W R/W R/W R/WPOR 0 0 — 0 1 0 0 0

Bit7~6 TM1~TM0:Timeroperationmodeselection00:Nomodeavailable01:Eventcountermode10:Timermode11:Pulsewidthcapturemode

Bit5 Unimplemented,readas"0"Bit4 TON:Timer/eventcountercountingenable

0:Disable1:Enable

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Bit3 TEG:Timer/EventCounteractiveedgeselectionIneventcountermode(TM1~TM0=01)0:Countonrisingedge1:Countonfallingedge

Inpulsewidthmeasurementmode(TM1~TM0=11)0:Startcountingonfallingedge,stopontherisingedge1:Startcountingonrisingedge,stoponthefallingedge

Bit2~0 TPSC2~ TPSC0:Timerprescalarrateselection000:fS

001:fS/2010:fS/4011:fS/8100:fS/16101:fS/32110:fS/64111:fS/128

Timer ModeInthismode, theTimer/EventCountercanbeutilizedtomeasurefixedtimeintervals,providinganinternalinterruptsignaleachtimetheTimer/EventCounteroverflows.Tooperateinthismode,theOperatingModeSelectbitpair,TnM1/TnM0,intheTimerControlRegistermustbesettothecorrectvalueasshown.

Bit7 Bit61 0

Control Register Operating Mode Select Bits for the Timer Mode

Inthismodetheinternalclockisusedasthetimerclock.ThetimerinputclocksourceisfSYS,fSYS/4orfLIRC.However, this timerclocksourceisfurtherdividedbyaprescaler, thevalueofwhichisdeterminedbythebitsTPSC2~TPSC0intheTimerControlRegister.Thetimer-onbit,TONmustbesethightoenablethetimertorun.Eachtimeaninternalclockhightolowtransitionoccurs,thetimerincrementsbyone.Whenthetimerisfullandoverflows,aninterruptsignalisgeneratedandthetimerwillreloadthevaluealreadyloadedintothepreloadregisterandcontinuecounting.Atimeroverflowconditionandcorrespondinginternalinterruptsaretwoofthewake-upsources.However,theinternalinterruptscanbedisabledbyensuringthattheTEbitsoftheINTC0registerareresettozero.

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Timer Mode Timing Chart

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Event Counter ModeInthismode,anumberofexternallychanginglogicevents,occurringontheexternaltimerTMRpin,canberecordedbytheTimer/EventCounter.Tooperate in thismode, theOperatingModeSelectbitpair,TM1/TM0,intheTimerControlRegistermustbesettothecorrectvalueasshown.

Bit7 Bit60 1

Control Register Operating Mode Select Bits for the Timer Mode

Inthismode,theexternaltimerTMRpin,isusedastheTimer/EventCounterclocksource,howeveritisnotdividedbytheinternalprescaler.AftertheotherbitsintheTimerControlRegisterhavebeenset,theenablebitTON,whichisbit4oftheTimerControlRegister,canbesethightoenabletheTimer/EventCountertorun.IftheActiveEdgeSelectbit,TEG,whichisbit3oftheTimerControlRegister,islow,theTimer/EventCounterwillincrementeachtimetheexternaltimerpinreceivesalowtohightransition.IftheTEGishigh,thecounterwillincrementeachtimetheexternaltimerpinreceivesahightolowtransition.Whenitisfullandoverflows,aninterruptsignalisgeneratedandtheTimer/EventCounterwillreloadthevaluealreadyloadedintothepreloadregisterandcontinuecounting.TheinterruptcanbedisabledbyensuringthattheTimer/EventCounterInterruptEnablebitinthecorrespondingInterruptControlRegister.Itisresettozero.

AstheexternaltimerpinissharedwithanI/Opin,toensurethatthepinisconfiguredtooperateasaneventcounterinputpin,twothingshavetohappen.ThefirstistoensurethattheOperatingModeSelectbits in theTimerControlRegisterplace theTimer/EventCounter in theEventCountingMode.Thesecondistoensurethattheportcontrolregisterconfiguresthepinasaninput.Itshouldbenoted that in theeventcountingmode,evenif themicrocontroller is in theSleepMode, theTimer/EventCounterwillcontinuetorecordexternallychanginglogiceventsonthetimer inputTMRpin.Asaresultwhenthetimeroverflowsitwillgenerateatimerinterruptandcorrespondingwake-upsource.

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Event Counter Mode Timing Chart (TEG=1)

Pulse Width Capture ModeIn thismode, theTimer/EventCountercanbeutilised tomeasure thewidthofexternalpulsesappliedtotheexternaltimerpin.Tooperateinthismode,theOperatingModeSelectbitpair,TM1/TM0,intheTimerControlRegistermustbesettothecorrectvalueasshown.

Bit7 Bit61 1

Control Register Operating Mode Select Bits for the Pulse Width Capture Mode

Inthismodetheinternalclock,fSYS,fSYS/4orfLIRCisusedastheinternalclockforthe8-bitTimer/EventCounter.However,theclocksource,fSYS,forthe8-bittimerisfurtherdividedbyaprescaler,thevalueofwhichisdeterminedbythePrescalerRateSelectbitsTPSC2~TPSC0,whicharebit2~0oftheTimerControlRegister,AfterotherbitsintheTimerControlRegisterhavebeenset,theenablebitTON,whichisbit4oftheTimerControlRegister,canbesethightoenabletheTimer/EventCounter,howeveritwillnotactuallystartcountinguntilanactiveedgeisreceivedontheexternaltimerpin.

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IftheActiveEdgeSelectbitTEGwhichisbit3oftheTimerControlRegisterislow,onceahightolowtransitionhasbeenreceivedontheexternal timerpin, theTimer/EventCounterwillstartcountinguntiltheexternaltimerpinreturnstoitsoriginalhighlevel.AtthispointtheenablebitwillbeautomaticallyresettozeroandtheTimer/EventCounterwillstopcounting.IftheActiveEdgeSelectbit ishigh,theTimer/EventCounterwillbegincountingoncealowtohightransitionhasbeenreceivedontheexternaltimerpinandstopcountingwhentheexternaltimerpinreturnstoitsoriginallowlevel.Asbefore,theenablebitwillbeautomaticallyresettozeroandtheTimer/EventCounterwillstopcounting.Itisimportanttonotethatinthepulsewidthcapturemode,theenablebitisautomaticallyresettozerowhentheexternalcontrolsignalontheexternaltimerpinreturnstoitsoriginallevel,whereasintheothertwomodestheenablebitcanonlyberesettozerounderprogramcontrol.

TheresidualvalueintheTimer/EventCounter,whichcannowbereadbytheprogram,thereforerepresentsthelengthofthepulsereceivedontheTMRpin.Astheenablebithasnowbeenreset,anyfurthertransitionsontheexternaltimerpinwillbeignored.Thetimercannotbeginfurtherpulsewidthcaptureuntil theenablebit issethighagainbytheprogram.Inthisway,singleshotpulsemeasurementscanbeeasilymade.ItshouldbenotedthatinthismodetheTimer/EventCounteriscontrolledbylogicaltransitionsontheexternaltimerpinandnotbythelogiclevel.WhentheTimer/EventCounterisfullandoverflows,aninterruptsignalisgeneratedandtheTimer/EventCounterwillreloadthevaluealreadyloadedintothepreloadregisterandcontinuecounting.TheinterruptcanbedisabledbyensuringthattheTimer/EventCounterInterruptEnablebitinthecorrespondingInterruptControlRegister,it isresettozero.AstheTMRpinissharedwithanI/Opin,toensurethatthepinisconfiguredtooperateasapulsewidthcapturepin,twothingshavetobeimplemented.Thefirst is toensurethat theOperatingModeSelectbits intheTimerControlRegisterplacetheTimer/EventCounterinthepulsewidthcapturemode,thesecondistoensurethattheportcontrolregisterconfigurethepinasaninput.

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Pulse Width Capture Mode Timing Chart (TEG=0)

PrescalerBitsTPSC2~TPSC0of theTMRCregistercanbeusedtodefineadivisionratiofor theinternalclocksourceoftheTimer/EventCounterenablinglongertimeoutperiodstobeset.

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PFD FunctionTheProgrammableFrequencyDividerprovidesameansofproducingavariablefrequencyoutputsuitableforapplication,suchassomeinterfacesrequiringaprecisefrequencygenerator.

TheTimer/EventCounteroverflowsignal is theclocksource for thePFDfunction,which iscontrolledbyPFDCbit inCTRL0.For thisdevicetheclocksourcecancomefromTimer/EventCounter.Theoutputfrequencyiscontrolledbyloadingtherequiredvaluesintothetimerprescalerandtimerregisterstogivetherequireddivisionratio.Thecounterwillbegintocount-upfromthispreloadregistervalueuntilfull,atwhichpointanoverflowsignalisgenerated,causingboththePFDoutputstochangestate.Thenthecounterwillbeautomaticallyreloadedwiththepreloadregistervalueandcontinuecounting-up.IftheCTRL0registerhasselectedthePFDfunction,thenforPFDoutputtooperate,itisessentialforthePortBcontrolregisterPBCtosetthePFDpinsasoutputs.PB5mustbesethightoactivatethePFD.Theoutputdatabitscanbeusedastheon/offcontrolbitforthePFDoutputs.Notethat thePFDoutputswillallbelowif theoutputdatabit isclearedtozero.

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PFD Function

I/O InterfacingTheTimer/EventCounter,whenconfigured to run in theeventcounterorpulsewidthcapturemode,requirestheuseofanexternaltimerpinforitsoperation.Asthispinisasharedpinitmustbeconfiguredcorrectlytoensurethatit issetforuseasaTimer/EventCounterinputpin.ThisisachievedbyensuringthatthemodeselectsbitsintheTimer/EventCountercontrolregister,eithertheeventcounterorpulsewidthcapturemode.AdditionallythecorrespondingPortControlRegisterbitmustbesethightoensurethatthepinissetasaninput.Anypull-highresistorconnectedtothispinwillremainvalidevenifthepinisusedasaTimer/EventCounterinput.

Programming ConsiderationsWhenrunninginthetimermode,theinternalsystemclockisusedasthetimerclocksourceandis thereforesynchronisedwith theoveralloperationof themicrocontroller. In thismodewhentheappropriatetimerregister isfull, themicrocontrollerwillgenerateaninternal interruptsignaldirectingtheprogramflowtotherespectiveinternal interruptvector.Forthepulsewidthcapturemode,theinternalsystemclockisalsousedasthetimerclocksourcebutthetimerwillonlyrunwhen thecorrect logicconditionappearson theexternal timer inputpin.As this isanexternaleventandnotsynchronisedwith the internal timerclock, themicrocontrollerwillonlysee thisexternaleventwhenthenexttimerclockpulsearrives.Asaresult,theremaybesmalldifferencesinmeasuredvaluesrequiringprogrammerstotakethisintoaccountduringprogramming.Thesameappliesifthetimerisconfiguredtobeintheeventcountingmode,whichagainisanexternaleventandnotsynchronisedwiththeinternalsystemortimerclock.

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WhentheTimer/EventCounter is read,or ifdata iswritten to thepreloadregister, theclock isinhibitedtoavoiderrors,howeverasthismayresultinacountingerror,thisshouldbetakenintoaccountbytheprogrammer.Caremustbetakentoensurethat thetimersareproperlyinitialisedbeforeusing themfor the first time.Theassociated timerenablebits in the interruptcontrolregistermustbeproperlysetotherwisetheinternalinterruptassociatedwiththetimerwillremaininactive.Theedgeselect, timermodeandclocksourcecontrolbits intimercontrolregistermustalsobecorrectlyset toensure thetimer isproperlyconfiguredfor therequiredapplication.It isalsoimportanttoensurethataninitialvalueisfirstloadedintothetimerregistersbeforethetimerisswitchedon;thisisbecauseafterpower-ontheinitialvaluesofthetimerregistersareunknown.Afterthetimerhasbeeninitialisedthetimercanbeturnedonandoffbycontrollingtheenablebitinthetimercontrolregister.

WhentheTimer/EventCounteroverflows,itscorrespondinginterruptrequestflagintheinterruptcontrolregisterwillbeset.IftheTimer/EventCounterinterruptisenabledthiswillinturngenerateaninterruptsignal.Howeverirrespectiveofwhethertheinterruptsareenabledornot,aTimer/EventCounteroverflowwillalsogenerateawake-upsignalifthedeviceisinaPower-downcondition.ThissituationmayoccuriftheTimer/EventCounterisintheEventCountingModeandiftheexternalsignalcontinues tochangestate.Insuchacase, theTimer/EventCounterwillcontinuetocounttheseexternaleventsandifanoverflowoccursthedevicewillbewokenupfromitsPower-downcondition.Topreventsuchawake-upfromoccurring,thetimerinterruptrequestflagshouldfirstbesethighbeforeissuingthe“HALT”instructiontoentertheSleepMode.

Timer Program ExampleTheprogramshowshowtheTimer/EventCounterregistersaresetalongwithhowtheinterruptsareenabledandmanaged.NotehowtheTimer/EventCounteristurnedon,bysettingbit4oftheTimerControlRegister.TheTimer/EventCountercanbeturnedoffinasimilarwaybyclearingthesamebit.ThisexampleprogramsetstheTimer/EventCounterstobeinthetimermode,whichusestheinternalsystemclockastheirclocksource.

PFD Programming Exampleorg 04h ; external interrupt vectororg 08h ; Timer/Event Counter interrupt vectorjmptmrint ;jumpherewhenTimeroverflows: :org 20h ; main program: : ; internal Timer interrupt routinetmrint:: ; Timer main program placed here:begin: ; set Timer registersmov a,09bh ; set Timer preload valuemov tmr,amov a,081h ; set Timer control registermov tmrc,a ; timer mode and prescaler set to /2mov a, 0c0H ; select fSYSfortheTMRclocksourcemov wdtc, a ; set interrupt registermov a,05h ; enable master interrupt and both timer interruptsmov intc0,a: :set tmrc.4 ; start Timer: :

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Time BaseThedeviceincludesaTimeBasefunctionwhichisusedtogeneratearegulartimeintervalsignal.

TheTimeBasetimeintervalmagnitudeisdeterminedusinganinternal13stagecountersets thedivisionratiooftheclocksource.ThisdivisionratioiscontrolledbyboththeTBSEL0andTBSEL1bitsintheCTRL1register.TheclocksourceisselectedusingtheWDTCLS1~WDTCLS0bitsintheWDTCregister.

WhentheTimeBasetimeout,aTimeBaseinterruptsignalwillbegenerated.ItshouldbenotedthatastheTimeBaseclocksourceisthesameastheTimer/EventCounterclocksource,careshouldbetakenwhenprogramming.

Pulse Width ModulatorThedevice includesone8-bitPWMfunction.Useful for theapplicationssuchasmotorspeedcontrol,thePWMfunctionprovidesoutputswithafixedfrequencybutwithadutycyclethatcanbevariedbysettingparticularvaluesintothecorrespondingPWMregister.

PWM OperationTheregister,knownasPWMand located in theDataMemory isassigned toeachPulseWidthModulatorchannel.It isherethat the8-bitvalue,whichrepresents theoveralldutycycleofonemodulationcycleof theoutputwaveform,shouldbeplaced.To increase thePWMmodulationfrequency,eachmodulationcycleissubdividedintotwoorfourindividualmodulationsubsections,knownasthe7+1modeor6+2moderespectively.Therequiredmodeandtheon/offcontrolforeachPWMchannelisselectedusingtheCTRL0register.NotethatwhenusingthePWM,itisonlynecessarytowritetherequiredvalueintothePWMregisterandselecttherequiredmodesetandon/offcontrolusingtheCTRL0register,thesubdivisionofthewaveformintoitssub-modulationcyclesisimplementedautomaticallywithinthemicrocontrollerhardware.ThePWMclocksourcefScomesfromthesystemclockfSYS,fSYS/4orfLIRC.

Thismethodofdividingtheoriginalmodulationcycleintoafurther2or4sub-cyclesenablethegenerationofhigherPWMfrequencieswhichallowawiderrangeofapplications tobeserved.Thedifferencebetweenwhat isknownas thePWMcyclefrequencyand thePWMmodulationfrequencyshouldbeunderstood.AsthePWMvalueis8-bitwide,theoverallPWMcyclefrequencyisfSYS/256.However,wheninthe7+1modeofoperationthePWMmodulationfrequencywillbefS/128,whilethePWMmodulationfrequencyforthe6+2modeofoperationwillbefS/64.

PWM Modulation PWM Cycle Frequency PWM Cycle DutyfS/6� for (6+�) bits modefS/1�8 for (7+1) bits mode fS /�56 [PWM]/�56

6+2 PWM ModeEachfullPWMcycle,asitiscontrolledbyan8-bitPWMregister,has256clockperiods.However,inthe6+2PWMmode,eachPWMcycleissubdividedintofourindividualsub-cyclesknownasmodulationcycle0~modulationcycle3,denotedasiinthetable.Eachoneofthesefoursub-cyclescontains64clockcycles.Inthismode,amodulationfrequencyincreaseoffourisachieved.The8-bitPWMregistervalue,whichrepresentstheoveralldutycycleofthePWMwaveform,isdividedintotwogroups.Thefirstgroupwhichconsistsofbit2~bit7isdenotedhereastheDCvalue.Thesecondgroupwhichconsistsofbit0~bit1isknownastheACvalue.Inthe6+2PWMmode,thedutycyclevalueofeachofthefourmodulationsub-cyclesisshowninthefollowingtable.

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Parameter AC (0~3) DC DC (Duty Cycle)

Mod�lation cycle i(i=0~3)

i<AC (DC+1)/6�i>AC DC/6�

6+2 Mode Modulation Cycle Values

Thefollowingdiagramillustratesthewaveformsassociatedwiththe6+2modeofPWMoperation.ItisimportanttonotehowthesinglePWMcycleissubdividedinto4individualmodulationcycles,numberedfrom0~3andhowtheACvalueisrelatedtothePWMvalue.

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6+2 PWM Mode

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PWM Register for 6+2 Mode

7+1 PWM ModeEachfullPWMcycle,asitiscontrolledbyan8-bitPWMregister,has256clockperiods.However,inthe7+1PWMmode,eachPWMcycleissubdividedintotwoindividualsub-cyclesknownasmodulationcycle0~modulationcycle1,denotedasiinthetable.Eachoneofthesetwosub-cyclescontains128clockcycles.Inthismode,amodulationfrequencyincreaseoftwoisachieved.The8-bitPWMregistervalue,whichrepresentstheoveralldutycycleofthePWMwaveform,isdividedintotwogroups.Thefirstgroupwhichconsistsofbit1~bit7isdenotedhereastheDCvalue.Thesecondgroupwhichconsistsofbit0isknownastheACvalue.Inthe7+1PWMmode,thedutycyclevalueofeachofthetwomodulationsub-cyclesisshowninthefollowingtable.

Parameter AC(0~1) DC (Duty Cycle)

Mod�lation cycle i(i=0~1)

i<AC (DC+1)/1�8i>=AC DC/1�8

Thefollowingdiagramillustratesthewaveformsassociatedwiththe7+1modePWMoperation.ItisimportanttonotehowthesinglePWMcycleissubdividedinto2individualmodulationcycles,numberedfrom0and1andhowtheACvalueisrelatedtothePWMvalue.

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7+1 Mode

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PWM Register for 7+1 Mode

PWM Output ControlThePWMoutputsarepin-sharedwiththeI/OpinPA4.TooperateasaPWMoutputandnotasanI/Opin,thecorrectbitsmustbesetintheCTRL0register.AzerovaluemustalsobewrittentothecorrespondingbitintheI/OportcontrolregisterPAC.4toensurethatthecorrespondingPWMoutputpin issetasanoutput.After these twoinitialstepshavebeencarriedout,andofcourseafter therequiredPWMvaluehasbeenwritten into thePWMregister,writingahighvalue tothecorrespondingbit intheoutputdataregisterPA.4willenablethePWMdatatoappearonthepin.WritingazerovaluewilldisablethePWMoutputfunctionandforcetheoutput low.Inthisway, thePortdataoutputregisterscanbeusedasanon/offcontrolfor thePWMfunction.NotethatiftheCTRL0registerhasselectedthePWMfunction,butahighvaluehasbeenwrittentoitscorrespondingbitinthePACcontrolregistertoconfigurethepinasaninput,thenthepincanstillfunctionasanormalinputline,withpull-highresistoroptions.

PWM Programming Examplemova,64h ;setPWMvalueofdecimal100mov pwm0,asetctrl0.5 ;selectthe7+1PWMmodesetctrl0.3 ;selectpinPA4tohaveaPWMfunctionclrpac.4 ;setpinPA4asanoutputsetpa.4 ;enablethePWMoutput: :clrpa.4 ;disablethePWMoutput_pinPA4forcedlow

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Analog to Digital Converter Theneedtointerfacetorealworldanalogsignals isacommonrequirementformanyelectronicsystems.However, toproperlyprocess these signalsbyamicrocontroller, theymust firstbeconverted intodigitalsignalsbyA/Dconverters.By integrating theA/Dconversionelectroniccircuitryintothemicrocontroller,theneedforexternalcomponentsisreducedsignificantlywiththecorrespondingfollow-onbenefitsoflowercostsandreducedcomponentspacerequirements.

A/D OverviewThedevicecontainsa5-channelanalogtodigitalconverterwhichcandirectlyinterfacetoexternalanalogsignals,suchasthatfromsensorsorothercontrolsignalsandconvertthesesignalsdirectlyintoeithera12-bitdigitalvalue.

TheaccompanyingblockdiagramshowstheoverallinternalstructureoftheA/Dconverter,togetherwithitsassociatedregisters.

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A/D Converter Structure

A/D Converter Data Registers – ADRL, ADRHThedevice,whichhasan internal12-bitA/Dconverter, require twodataregisters,ahighbyteregister,knownasADRH,andalowbyteregister,knownasADRL.Aftertheconversionprocesstakesplace, these registerscanbedirectly readby themicrocontroller toobtain thedigitisedconversionvalue.Onlythehighbyteregister,ADRH,utilisesitsfull8-bitcontents.Thelowbyteregisterutilisesonly4bitsof its8-bitcontentsas itcontainsonly the lowestbitsof the12-bitconvertedvalue.

Inthefollowingtable,D0~D11istheA/Dconversiondataresultbits.

ADRH, ADRL Register

BitADRH ADRL

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Name D11 D10 D� D8 D7 D6 D5 D� D3 D� D1 D0 — — — —R/W R R R R R R R R R R R R — — — —POR x x x x x x x x x x x x — — — —

“x” �nknownUnimplemented,readas“0”D11~D0:A/Dconversiondata

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A/D Converter Control Registers – ADCR, ACSR, ADPCRTocontrolthefunctionandoperationoftheA/Dconverter,twocontrolregistersknownasADCR,ACSRandADPCRareprovided.These8-bitregistersdefinefunctionssuchastheon/offfunction,theselectionofwhichanalogchannel isconnectedtotheinternalA/Dconverter,whichpinsareusedasanaloginputsandwhichareusedasnormalI/Os,theA/DclocksourceaswellascontrollingthestartfunctionandmonitoringtheA/Dconverterendofconversionstatus.

TheACS2~ACS0bitsintheADCRregisterdefinethechannelnumber.Asthedevicecontainsonlyoneactualanalogtodigitalconvertercircuit,eachoftheindividual5analoginputsmustberoutedtotheconverter.ItisthefunctionoftheACS2~ACS0bitsintheADCRregistertodeterminewhichanalogchannelisactuallyconnectedtotheinternalA/Dconverter.

ThePCR4~PCR0bitscontained in theADPCRregisterwhichdeterminewhichpinsonPA5,PA3~PA0areusedasanaloginputsfortheA/DconverterandwhichpinsaretobeusedasnormalI/Opins.If thePCRnbithasavalueof1, thenthecorrespondingpin,namelyoneoftheAN0~AN3analog inputs,willbe setasanalog inputs.Note that if thePCRnbit is set tozero, then thecorrespondingpinonPA5,PA3~PA0willbesetasanormalI/Opin,theanaloginputchannelswillbealldisabledandtheA/Dconvertercircuitrywillbepoweredoff.

TheADPCRcontrol register contains thePCR4~PCR0bitswhichdeterminewhichpinsonPA0~PA3,PA5areusedasanaloginputsfortheA/DconverterandwhichpinsaretobeusedasnormalI/Opins.Notethatif thePCR4~PCR0bitsareallset tozero,thenall thePA5,PA3~PA0pinswillbesetasnormalI/Os.

ADCR Register

Bit 7 6 5 4 3 2 1 0Name START EOCB — — — ACS� ACS1 ACS0R/W R/W R — — — R/W R/W R/WPOR 0 1 — — — 0 0 0

Bit7 START:StarttheA/Dconversion0→1→0:Start0→1:ResettheA/DconverterandsetEOCBto"1"

ThisbitisusedtoinitiateanA/Dconversionprocess.Thebitisnormallylowbutifsethighandthenclearedlowagain,theA/Dconverterwillinitiateaconversionprocess.WhenthebitissethightheA/Dconverterwillbereset.

Bit6 EOCB:EndofA/Dconversionflag0:A/Dconversionended1:A/Dconversioninprogress

ThisreadonlyflagisusedtoindicatewhenanA/Dconversionprocesshascompleted.Whentheconversionprocessisrunning,thebitwillbehigh.

Bit5~3 Unimplemented,readas“0”Bit2~0 ACS2~ACS0:A/Dchannelselection

000:AN0001:AN1010:AN2011:AN3100:AN4101:AN4110:AN4111:AN3

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ACSR Register

Bit 7 6 5 4 3 2 1 0Name TEST ADONB — — — ADCS� ADCS1 ADCS0R/W R/W R/W — — — R/W R/W R/WPOR 1 1 — — — 0 0 0

Bit7 TEST:FortestmodeuseonlyBit6 ADONB:A/DConvertermoduleon/offcontrolbit

0:A/DConvertermoduleison1:A/DConvertermoduleisoff

Note:1.ItisrecommendedtosetADONB=1beforeenteringsleepforsavingpower.2.ADONB=1willpowerdowntheA/DConvertermodule.

Bit5~3 Unimplemented,readas“0”Bit2~0 ADCS2~ADCS0:SelectA/DConverterclocksource

000:fSYS/2001:fSYS/8010:fSYS/32011:Undefined100:fSYS

101:fSYS/4110:fSYS/16111:Undefined

ThesethreebitsareusedtoselecttheclocksourcefortheA/Dconverter.

ADPCR Register

Bit 7 6 5 4 3 2 1 0Name — — — PCR� PCR3 PCR� PCR1 PCR0R/W — — — R/W R/W R/W R/W R/WPOR — — — 0 0 0 0 0

Bit7~5 Unimplemented,readas“0”Bit4 PCR4:DefinePA5isA/Dinputornot

0:NotA/Dinput1:A/Dinput,AN4

Bit3 PCR3:DefinePA3isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN3




IfPCR4~PCR0areallzero, theA/DConvertercircuitwillbeoff toreducepowerconsumption.

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A/D OperationTheSTARTbitintheregisterisusedtostartandresettheA/Dconverter.Whenthemicrocontrollersets thisbit fromlowtohighandthen lowagain,ananalog todigitalconversioncyclewillbeinitiated.WhentheSTARTbitisbroughtfromlowtohighbutnotlowagain,theEOCBbitintheADCRregisterwillbesettoa“1”andtheanalogtodigitalconverterwillbereset.ItistheSTARTbitthatisusedtocontroltheoverallstartoperationoftheinternalanalogtodigitalconverter.

TheEOCBbitintheADCRregisterisusedtoindicatewhentheanalogtodigitalconversionprocessiscomplete.Thisbitwillbeautomaticallysetto“0”bythemicrocontrollerafteraconversioncyclehasended.Inaddition, thecorrespondingA/Dinterruptrequestflagwillbeset in the interruptcontrolregister,andif the interruptsareenabled,anappropriate internal interruptsignalwillbegenerated.ThisA/Dinternal interruptsignalwilldirect theprogramflowto theassociatedA/Dinternalinterruptaddressforprocessing.IftheA/Dinternalinterruptisdisabled,themicrocontrollercanbeusedtopolltheEOCBbitintheADCRregistertocheckwhetherithasbeenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle.

TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,isfirstdividedbyadivisionratio,thevalueofwhichisdeterminedbytheADCS2,ADCS1andADCS0bitsintheACSRregister.

TheA/Dconverteroverallon/offcontrolisafunctionofboththeADONBbitintheACSRregisterand thePCR4~PCR0bits in theADPCRregisterasshownin the table.Either theADONBbitclearedtozeroorthePCR4~PCR0bitssettoazerovaluewillswitchofftheA/Dconverter.Theseareimportantconsiderationinpowersensitiveapplicationsandmustbetakenintoaccountifpowerconsumptionistobeminimised.Asthetableillustrates,executionoftheHALTinstructionhasnoeffectontheA/Dconverteron/offcontrolandsubsequentlyitspowerconsumption.

PCR4~PCR0 Bits HALT Instruction ADONB Bit A/D Converter On/Off= 0 x x Off> 0 x 0 On> 0 x 1 Off

“x”: Don’t careA/D Converter On/Off Control

AlthoughtheA/DclocksourceisdeterminedbythesystemclockfSYS,andbybitsADCS2,ADCS1andADCS0, therearesome limitationson themaximumA/Dclocksourcespeed thatcanbeselected.AstheminimumvalueofpermissibleA/Dclockperiod,tAD,is0.5μs~10μs,caremustbetakenforsystemclockspeedsinexcessof4MHz.Forsystemclockspeedsinexcessof4MHz,theADCS2,ADCS1andADCS0bitsshouldnotbesetto“000”.DoingsowillgiveA/DclockperiodsthatarelessthantheminimumA/Dclockperiodwhichmayresult ininaccurateA/Dconversionvalues.

Refer to thefollowingtableforexamples,wherevaluesmarkedwithanasterisk*showwhere,dependinguponthedevice,specialcaremustbetaken,asthevaluesmaybelessthanthespecifiedminimumA/DClockPeriod.

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fSYS

A/D Clock Period (tAD)ADCS2,ADCS1,ADCS0= 000(fSYS/2)

ADCS2,ADCS1,ADCS0= 001(fSYS/8)

ADCS2,ADCS1,ADCS0= 010

(fSYS/32)

ADCS2,ADCS1,ADCS0

=100(fSYS)

ADCS2,ADCS1,ADCS0= 101(fSYS/4)

ADCS2,ADCS1,ADCS0= 110

(fSYS/16)

ADCS2,ADCS1,ADCS0

= 011,111

1MHz 2μs 8μs 32μs* 1μs 4μs 16μs* Undefined�MHz 1μs 4μs 16μs* 500ns 2μs 8μs Undefined�MHz 500ns 2μs 8μs 250ns* 1μs 4μs Undefined8MHz 250ns* 1μs 4μs 125ns* 500ns 2μs Undefined

A/D Clock Period Examples

A/D Input PinsAlloftheA/Danaloginputpinsarepin-sharedwiththeI/OpinsonPortA.BitsPCR4~PCR0intheADPCRregisterdeterminewhethertheinputpinsaresetasnormalinput/outputpinsorwhethertheyaresetasanaloginputs.Inthisway,pinscanbechangedunderprogramcontroltochangetheirfunctionfromnormalI/Ooperationtoanaloginputsandviceversa.Pull-highresistors,whichareset throughregisterprogramming,applytotheinputpinsonlywhentheyareusedasnormalI/Opins,ifsetasA/Dinputsthepull-highresistorswillbeautomaticallydisconnected.Notethatit isnotnecessarytofirstsettheA/DpinasaninputintheI/OportcontrolregisterstoenabletheA/DinputaswhenthePCR4~PCR0bitsenableanA/Dinput,thestatusoftheportcontrolregisterwillbeoverridden.

Summary of A/D Conversion StepsThefollowingsummarisestheindividualstepsthatshouldbeexecutedinordertoimplementanA/Dconversionprocess.

• Step1SelecttherequiredA/DconversionclockbycorrectlyprogrammingbitsADCS2~ADCS0intheACSRregister.

• Step2SelectwhichpinsaretobeusedasA/DinputsandconfigurethemasA/DinputpinsbycorrectlyprogrammingthePCR4~PCR0bitsintheADPCRregister.

• Step3EnabletheA/DbyclearingtheADONBintheACSRregistertozero.

• Step4SelectwhichchannelistobeconnectedtotheinternalA/DconverterbycorrectlyprogrammingtheACS2~ACS0bitswhicharealsocontainedintheregister.

• Step5If the interruptsare tobeused, the interruptcontrolregistersmustbecorrectlyconfiguredtoensuretheA/Dconverterinterruptfunctionisactive.Themasterinterruptcontrolbit,EMI,theINTC0interruptcontrolregistermustbesetto“1”,theA/Dconverterinterruptbit,ADE,mustalsobesetto“1”.

• Step6Theanalog todigitalconversionprocesscannowbe initialisedbysetting theSTARTbit intheADCRregisterfromlowtohighandthenlowagain.Note that thisbitshouldhavebeenoriginallyclearedtozero.

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• Step7Tocheckwhentheanalogtodigitalconversionprocessiscomplete,theEOCBbitintheADCRregistercanbepolled.Theconversionprocessiscompletewhenthisbitgoeslow.WhenthisoccurstheA/DdataregistersADRLandADRHcanbereadtoobtaintheconversionvalue.Asanalternativemethod,iftheinterruptsareenabledandthestackisnotfull,theprogramcanwaitforanA/Dinterrupttooccur.Note:Whencheckingfortheendoftheconversionprocess,ifthemethodofpollingtheEOCB

bitintheADCRregisterisused,theinterruptenablestepabovecanbeomitted.

Theaccompanyingdiagramshowsgraphicallythevariousstagesinvolvedinananalogtodigitalconversionprocessanditsassociatedtiming.

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A/D Conversion Timing

Thesettingupandoperationof theA/Dconverter function is fullyunder thecontrolof theapplicationprogramastherearenoconfigurationoptionsassociatedwiththeA/Dconverter.

AfteranA/Dconversionprocesshasbeeninitiatedbytheapplicationprogram,themicrocontrollerinternalhardwarewillbegin tocarryout theconversion,duringwhich time theprogramcancontinuewithotherfunctions.ThetimetakenfortheA/Dconversionis16tADwheretADisequaltotheA/Dclockperiod.

Programming ConsiderationsWhenprogramming,thespecialattentionmustbegiventothePCR[4:0]bitsintheregister.Ifthesebitsareallclearedtozero,noexternalpinswillbeselectedforuseasA/Dinputpinsallowingthepins tobeusedasnormalI/Opins.Whenthishappens, theinternalA/Dcircuitrywillbepowerdown.SettingtheADONBbithighhastheabilitytopowerdowntheinternalA/Dcircuitry,whichmaybeanimportantconsiderationinpowersensitiveapplications.

A/D Transfer FunctionAsthedevicecontainsa12-bitA/Dconverter, itsfull-scaleconverteddigitisedvalueisequal toFFFH.Sincethefull-scaleanaloginputvalueisequal to theVDDvoltage, thisgivesasinglebitanaloginputvalueofVDDdividedby4096.ThediagramshowstheidealtransferfunctionbetweentheanaloginputvalueandthedigitisedoutputvaluefortheA/Dconverter.

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Notethat toreducethequantisationerror,a0.5LSBoffset isaddedtotheA/DConverter input.Exceptforthedigitisedzerovalue,thesubsequentdigitisedvalueswillchangeatapoint0.5LSBbelowwheretheywouldchangewithouttheoffset,andthelastfullscaledigitizedvaluewillchangeatapoint1.5LSBbelowtheVDDlevel.

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Ideal A/D Transfer Function

A/D Programming ExampleThefollowingtwoprogrammingexamplesillustratehowtosetandimplementanA/Dconversion.Inthefirstexample, themethodofpollingtheEOCBbit in theADCRregister isusedtodetectwhentheconversioncycleiscomplete,whereasinthesecondexample,theA/Dinterruptisusedtodeterminewhentheconversioniscomplete.

Example: using an EOCB polling method to detect the end of conversionclr ADE ; disable A/D Converter interruptmov a,00000001BmovACSR,a ;selectfSYS/8 as A/D clock and ADONB=0mov a,00011111BmovADPCR,a ;setupADCRregistertoconfigureI/OPortasA/Dinputsmov a,00000000BmovADCR,a ;selectAN0tobeconnectedtotheA/Dconverter::Start_conversion:clrSTARTsetSTART ;resetA/DclrSTART ;startA/DPolling_EOC:sz EOCB ;polltheADCRregisterEOCBbittodetectend ; of A/D conversionjmppolling_EOC ;continuepollingmova,ADRL ;readlowbyteconversionresultvaluemovadrl_buffer,a ;saveresulttouserdefinedregistermova,ADRH ;readhighbyteconversionresultvaluemovadrh_buffer,a ;saveresulttouserdefinedregister:jmpstart_conversion ;startnextA/Dconversion

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Example: using the interrupt method to detect the end of conversionclr ADE ; disable A/D Converter interruptmov a,00000001BmovACSR,a ;selectfSYS/8 as A/D clock and ADONB=0mov a,00011111BmovADPCR,a ;setupADCRregistertoconfigureI/OPortasA/Dinputsmov a,00000000BmovADCR,a ;selectAN0tobeconnectedtotheA/Dconverter:::Start_conversion:clrSTARTsetSTART ;resetA/DclrSTART ;startA/DclrADF ;clearA/DConverterinterruptrequestflagset ADE ; enable A/D Converter interruptsetEMI ;enableglobalinterrupt:: ; A/D Converter interrupt service routineADC_ISR:movacc_stack,a ;saveACCtouserdefinedmemorymov a,STATUSmovstatus_stack,a ;saveSTATUStouserdefinedmemory::mova,ADRL ;readlowbyteconversionresultvaluemovadrl_buffer,a ;saveresulttouserdefinedregistermova,ADRH ;readhighbyteconversionresultvaluemovadrh_buffer,a ;saveresulttouserdefinedregister::EXIT_ISR:mova,status_stackmovSTATUS,a ;restoreSTATUSfromuserdefinedmemorymova,acc_stack ;restoreACCfromuserdefinedmemoryclrADF ;clearA/DConverterinterruptflagreti

Note:TopoweroffA/DConvertermodule, it isnecessary to setADONBas “1”or set thePCR4~PCR0bitsasazerovalue.

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InterruptsInterruptsareanimportantpartofanymicrocontrollersystem.WhenanexternaleventoraninternalfunctionsuchasaTimer/EventCounter requiresmicrocontrollerattention, theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogramallowingthemicrocontrollertodirectattentiontotheirrespectiveneeds.

Thedevicecontainsonlyoneexternal interruptandmultiple internal interrupts.Theexternalinterruptsarecontrolledbytheactionoftheexternal interruptpin,whiletheinternal interrupt iscontrolledbytheTimer/EventCounter,theA/DconverterinterruptandTimerBaseinterrupt.

Interrupt RegisterOverallinterruptcontrol,whichmeansinterruptenablingandrequestflagsetting,iscontrolledbyusingregisters,INTC0andINTC1.Bycontrollingtheappropriateenablebitsintheregistereachindividual interruptcanbeenabledordisabled.Alsowhenaninterruptoccurs, thecorrespondingrequestflagwillbesetbythemicrocontroller.Theglobalenableflagclearedtozerowilldisableallinterrupts.

Function Enable Bit Request FlagGlobal EMI —INT Pin INTE INTFTimer TE TFA/D Converter ADE ADFTimer Base TBE TBF

INTC0 Register

Bit 7 6 5 4 3 2 1 0Name — ADF TF INTF ADE TE INTE EMIR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas"0"Bit5 ADF:A/Dinterrruptrequestflag

0:Norequest1:Interruptrequest

Bit5 TF:Timer/EventCounterinterrruptrequestflag0:Norequest1:Interruptrequest

Bit4 INTF:INTpininterruptrequestflag0:Norequest1:Interruptrequest

Bit3 ADE:A/Dinterruptcontrol0:Disable1:Enable

Bit2 TE:Timer/EventCounterinterruptcontrol0:Disable1:Enable

Bit1 INTE:INTinterruptcontrol0:Disable1:Enable

Bit0 EMI:Globalinterruptcontrol0:Disable1:Enable

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INTC1 Register

Bit 7 6 5 4 3 2 1 0Name — — — TBF — — — TBER/W — — — R/W — — — R/WPOR — — — 0 — — — 0

Bit7~5 Unimplemented,readas"0"Bit4 TBF:timebaseeventinterruptrequestflag

0:Norequest1:Interruptrequest

Bit3~1 Unimplemented,readas“0”Bit0 TBE:timebaseeventinterruptenable

0:Disable1:Enable

Interrupt OperationATimer/EventCounteroverflow,acompletionofA/Dconversionoranactiveedgeontheexternalinterruptpinwillallgeneratean interruptrequestbysettingtheircorrespondingrequestflag, iftheirappropriateinterruptenablebitisset.Whenthishappens,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwill thenbe loadedwithanewaddresswhichwillbe thevalueof thecorrespondinginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.

Theinstructionat thisvectorwillusuallybeaJMPstatementwhichwill jumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriate interrupt.The interruptserviceroutinemustbe terminatedwithaRETI instruction,whichretrievestheoriginalProgramCounteraddressfromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.

Thevarious interruptenablebits, togetherwith theirassociatedrequest flags,areshownin thefollowingdiagramwiththeirorderofpriority.

04H

08H

0CH

Vector

Low

PriorityHigh

RequestFlags

EnableBits

MasterEnable

EMI auto disabled in ISR

InterruptName

EMI

EMI

EMIINTFINT Pin INTE

TFTimer TE

ADFA/D ADE

Legend

xxF Request Flag - auto reset in ISR

xxE Enable Bit

10HEMITBFTime Base TBE

Interrupt Scheme

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Onceaninterruptsubroutineisserviced,alltheotherinterruptswillbeblocked,astheEMIbitwillbeclearedautomatically.Thiswillpreventanyfurtherinterruptnestingfromoccurring.However,ifotherinterruptrequestsoccurduringthisinterval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillberecorded.Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.

Whenaninterruptrequestisgeneratedittakes2or3instructioncyclesbeforetheprogramjumpstotheinterruptvector.IfthedeviceisintheSleepModeandiswokenupbyaninterruptrequestthenitwilltake3cyclesbeforetheprogramjumpstotheinterruptvector.

MainProgram

Enable bit set?

MainProgram

Automatically Disable Interrupt Clear EMI & Request Flag

Wait for 2~3 Instruction Cycles

ISR Entry......

RETI(it will set EMI automatically)

Interrupt Request orInterrupt Flag Set by Instruction

N

Y

Interrupt Flow

Interrupt PriorityInterrupts,occurringintheintervalbetweentherisingedgesoftwoconsecutiveT2pulses,willbeservicedonthelatterofthetwoT2pulses,if thecorrespondinginterruptsareenabled.Incaseofsimultaneousrequests,thefollowingtableshowstheprioritythatisapplied.ThesecanbemaskedbyresettingtheEMIbit.

Interrupt Source Priority VectorExternal interr�pt 1 0�HTimer/Event Counter overflow � 08HA/D converter complete 3 0CHTime Base Overflow � 10H

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Incaseswherebothexternalandinternalinterruptsareenabledandwhereanexternalandinternalinterruptoccurssimultaneously,theexternalinterruptwillalwayshavepriorityandwillthereforebeservicedfirst.Suitablemaskingoftheindividualinterruptsusingtheinterruptregisterscanpreventsimultaneousoccurrences.

External InterruptForanexternalinterrupttooccur,theglobalinterruptenablebit,EMI,andexternalinterruptenablebit,INTE,mustfirstbeset.Anactualexternalinterruptwilltakeplacewhentheexternalinterruptrequestflag,INTFisset,asituationthatwilloccurwhenanedgetransitionappearsontheexternalINTline.Thetypeoftransitionthatwilltriggeranexternalinterrupt,whetherhightolow,lowtohighorbothisdeterminedbytheINTES0andINTES1bits,whicharebits6and7respectivelyintheCTRL1controlregister.Thesetwobitscanalsodisabletheexternalinterruptfunction.

INTES1 INTES0 Request Flag0 0 External interr�pt disable0 1 Rising edge trigger1 0 Falling edge trigger1 1 D�al edge trigger

Theexternal interruptpinispin-sharedwiththeI/OpinPA6andcanonlybeusedasanexternalinterruptpinif thecorrespondingexternal interruptenablebit intheINTC0registerhasbeensetandtheedgetriggertypehasbeenselectedusingtheCTRL1register.ThepinmustalsobesetasaninputbysettingthecorrespondingPAC.6bit intheportcontrolregister.Whentheinterruptisenabled, thestack isnotfullanda transitionappearson theexternal interruptpin,asubroutinecalltotheexternalinterruptvectoratlocation04H,willtakeplace.Whentheinterruptisserviced,theexternal interrupt request flag, INTF,willbeautomatically resetand theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.Notethatanypull-highresistorconnectionsonthispinwillremainvalidevenifthepinisusedasanexternalinterruptinput

Timer/Event Counter InterruptFor aTimer/EventCounter interrupt tooccur, theglobal interrupt enablebit,EMIand thecorresponding timer interruptenablebitTEmust firstbeset.AnactualTimer/EventCounterinterruptwilltakeplacewhentheTimer/EventCounterrequestflagTFisset,asituationthatwilloccurwhentherelevantTimer/EventCounteroverflows.Whentheinterruptisenabled,thestackisnotfullandaTimer/EventCounteroverflowoccurs,asubroutinecalltotherelevanttimerinterruptvector,will takeplace.Whentheinterruptisserviced,thetimerinterruptrequestflagTFwillbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

A/D Converter InterruptThedeviceincludesA/Dinterrupt.ForanA/Dinterrupt tooccur, theglobal interruptenablebitEMIandthecorrespondinginterruptenablebitADEmustbefirstset.AnactualA/DinterruptwilltakeplacewhentheA/DconverterrequestflagADFisset,asituationthatwilloccurwhenanA/Dconversionprocesshascompleted.Whentheinterruptisenabled,thestackisnotfullandanA/Dconversionprocessfinishesexecution,asubroutinecall totherelevantA/Dinterruptvector,willtakeplace.Whentheinterruptisserviced,theA/DinterruptrequestflagADFwillbeautomaticallyresetandtheEMIbitwillbeautomaticallycleared todisableother interrupts.As this interruptvectorlocationissharedwithotherinterrupts,tobeeffectiveitmustbeselectedviaconfigurationoption.

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Time Base InterruptForatimebaseinterrupttooccurtheglobalinterruptenablebitEMIandthecorrespondinginterruptenablebitTBE,must firstbeset.AnactualTimeBase interruptwill takeplacewhen the timebaserequestflagTBFisset,asituationthatwilloccurwhentheTimeBaseoverflows.Whentheinterruptisenabled,thestackisnotfullandatimebaseoverflowoccursasubroutinecalltotimebasevectorwilltakeplace.Whentheinterruptisserviced,thetimebaseinterruptflag.TBFwillbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

Interrupt Wake-up FunctionEachof the interruptfunctionshas thecapabilityofwakingupthemicrocontrollerwhenin theSleepMode.Awake-upisgeneratedwhenaninterruptrequestflagchangesfromlowtohighandisindependentofwhethertheinterruptisenabledornot.Therefore,eventhoughthedeviceisintheSleepModeanditssystemoscillatorisstopped,situationssuchasexternaledgetransitionsontheexternalinterruptpins,alowpowersupplyvoltageormaycausetheirrespectiveinterruptflagtobesethighandconsequentlygenerateaninterrupt.Caremustthereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-upfunctionistobedisabledthenthecorrespondinginterruptrequestflagshouldbesethighbefore thedeviceenters theSleepMode.Theinterruptenablebitshavenoeffectontheinterruptwake-upfunction.

Programming ConsiderationsBydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,oncean interrupt request flag is set, itwill remain in thiscondition in theinterruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbytheapplicationprogram.

It isrecommendedthatprogramsdonotusethe“CALL”instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.

Allof these interruptshave thecapabilityofwakingup themicrocontrollerwhenit is inSleepMode,thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeenteringtheSleepMode.

AsonlytheProgramCounterispushedontothestack,thenifthecontentsoftheaccumulator,statusregisterorotherregistersarealteredbytheinterruptserviceprogram,whichmaycorruptthedesiredcontrolsequence,thenthecontentsshouldbesavedinadvance.

Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETIinstructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.

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Application Circuits

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Instruction Set

IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontroller,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.

Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5μsandbranchorcall instructionswouldbeimplementedwithin1μs.Although instructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe“CLRPCL”or“MOVPCL,A”.Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.

Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofseveralkindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsistoreceivedatafromtheinputportsandtransferdatatotheoutputports.

Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandless than0forsubtraction.Theincrementanddecrement instructionssuchasINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.

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Logical and Rotate OperationThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhichrotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionor toa subroutineusing theCALL instruction.Theydiffer in the sense that in thecaseofasubroutinecall, theprogrammustreturn to the instruction immediatelywhenthesubroutinehasbeencarriedout.Thisisdonebyplacingareturninstruction“RET”inthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingtheconditionofacertaindatamemoryor individualbits.Dependingupon theconditions, theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These instructionsare thekey todecisionmakingandbranchingwithin theprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.

Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe“SET[m].i”or“CLR[m].i”instructionsrespectively.Thefeatureremovestheneedforprogrammerstofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.

Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemorytobesetupasatablewheredatacanbedirectlystored.Asetofeasytouseinstructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.

Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe“HALT”instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.

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Instruction Set SummaryThefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbeconsultedasabasicinstructionreferenceusingthefollowinglistedconventions.

Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress

Mnemonic Description Cycles Flag AffectedArithmeticADD A�[m] Add Data Memory to ACC 1 Z� C� AC� OVADDM A�[m] Add ACC to Data Memory 1Note Z� C� AC� OVADD A�x Add immediate data to ACC 1 Z� C� AC� OVADC A�[m] Add Data Memory to ACC with Carry 1 Z� C� AC� OVADCM A�[m] Add ACC to Data memory with Carry 1Note Z� C� AC� OVSUB A�x S�btract immediate data from the ACC 1 Z� C� AC� OVSUB A�[m] S�btract Data Memory from ACC 1 Z� C� AC� OVSUBM A�[m] S�btract Data Memory from ACC with res�lt in Data Memory 1Note Z� C� AC� OVSBC A�[m] S�btract Data Memory from ACC with Carry 1 Z� C� AC� OVSBCM A�[m] S�btract Data Memory from ACC with Carry� res�lt in Data Memory 1Note Z� C� AC� OVDAA [m] Decimal adj�st ACC for Addition with res�lt in Data Memory 1Note CLogic OperationAND A�[m] Logical AND Data Memory to ACC 1 ZOR A�[m] Logical OR Data Memory to ACC 1 ZXOR A�[m] Logical XOR Data Memory to ACC 1 ZANDM A�[m] Logical AND ACC to Data Memory 1Note ZORM A�[m] Logical OR ACC to Data Memory 1Note ZXORM A�[m] Logical XOR ACC to Data Memory 1Note ZAND A�x Logical AND immediate Data to ACC 1 ZOR A�x Logical OR immediate Data to ACC 1 ZXOR A�x Logical XOR immediate Data to ACC 1 ZCPL [m] Complement Data Memory 1Note ZCPLA [m] Complement Data Memory with res�lt in ACC 1 ZIncrement & DecrementINCA [m] Increment Data Memory with res�lt in ACC 1 ZINC [m] Increment Data Memory 1Note ZDECA [m] Decrement Data Memory with res�lt in ACC 1 ZDEC [m] Decrement Data Memory 1Note ZRotateRRA [m] Rotate Data Memory right with res�lt in ACC 1 NoneRR [m] Rotate Data Memory right 1Note NoneRRCA [m] Rotate Data Memory right thro�gh Carry with res�lt in ACC 1 CRRC [m] Rotate Data Memory right thro�gh Carry 1Note CRLA [m] Rotate Data Memory left with res�lt in ACC 1 NoneRL [m] Rotate Data Memory left 1Note NoneRLCA [m] Rotate Data Memory left thro�gh Carry with res�lt in ACC 1 CRLC [m] Rotate Data Memory left thro�gh Carry 1Note C

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Mnemonic Description Cycles Flag AffectedData MoveMOV A�[m] Move Data Memory to ACC 1 NoneMOV [m]�A Move ACC to Data Memory 1Note NoneMOV A�x Move immediate data to ACC 1 NoneBit OperationCLR [m].i Clear bit of Data Memory 1Note NoneSET [m].i Set bit of Data Memory 1Note NoneBranch�MP addr ��mp �nconditionally � NoneSZ [m] Skip if Data Memory is zero 1Note NoneSZA [m] Skip if Data Memory is zero with data movement to ACC 1Note NoneSZ [m].i Skip if bit i of Data Memory is zero 1Note NoneSNZ [m].i Skip if bit i of Data Memory is not zero 1Note NoneSIZ [m] Skip if increment Data Memory is zero 1Note NoneSDZ [m] Skip if decrement Data Memory is zero 1Note NoneSIZA [m] Skip if increment Data Memory is zero with res�lt in ACC 1Note NoneSDZA [m] Skip if decrement Data Memory is zero with res�lt in ACC 1Note NoneCALL addr S�bro�tine call � NoneRET Ret�rn from s�bro�tine � NoneRET A�x Ret�rn from s�bro�tine and load immediate data to ACC � NoneRETI Ret�rn from interr�pt � NoneTable ReadTABRD [m] Read table (specific page) to TBLH and Data Memory �Note NoneTABRDC [m] Read table (c�rrent page) to TBLH and Data Memory �Note NoneTABRDL [m] Read table (last page) to TBLH and Data Memory �Note NoneMiscellaneousNOP No operation 1 NoneCLR [m] Clear Data Memory 1Note NoneSET [m] Set Data Memory 1Note NoneCLR WDT Clear Watchdog Timer 1 TO� PDFCLR WDT1 Pre-clear Watchdog Timer 1 TO� PDFCLR WDT� Pre-clear Watchdog Timer 1 TO� PDFSWAP [m] Swap nibbles of Data Memory 1Note NoneSWAPA [m] Swap nibbles of Data Memory with res�lt in ACC 1 NoneHALT Enter power down mode 1 TO� PDF

Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.

2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.3.For the“CLRWDT1”and“CLRWDT2”instructionstheTOandPDFflagsmaybeaffectedbytheexecution status.TheTOandPDFflagsareclearedafterboth“CLRWDT1”and“CLRWDT2”instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.

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Instruction Definition

ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C

ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C

ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C

AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z

ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z

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CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None

CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT1 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksin conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will havenoeffect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT2 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect. RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno effect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z

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CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

DECA[m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF

INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z

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JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None

MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None

MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None

OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z

ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None

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RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None

RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None

RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None

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RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None

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SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

SNZ [m].i SkipifbitiofDataMemoryisnot0Description IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C

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SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C

SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C

SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None

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TABRD [m] Readtable(specificpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(specificpage)addressedbythetablepointerpair (TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDC [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z

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Package Information

Note that thepackage informationprovidedhere is for consultationpurposesonly.As thisinformationmaybeupdatedatregularintervalsusersareremindedtoconsulttheHoltekwebsiteforthelatestversionofthepackageinformation.

Additionalsupplementaryinformationwithregardtopackagingislistedbelow.Clickontherelevantsectiontobetransferredtotherelevantwebsitepage.

• FurtherPackageInformation(includeOutlineDimensions,ProductTapeandReelSpecifications)

• PackingMeterialsInformation

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Rev. 1.00 7� ��ne 1�� 01� Rev. 1.00 73 ��ne 1�� 01�



16-pin DIP (300mil) Outline Dimensions

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SymbolDimensions in inch

Min. Nom. Max.A 0.780 0.7�0 0.800 B 0.��0 0.�50 0.�80 C 0.115 0.130 0.1�5 D 0.115 0.130 0.150 E 0.01� 0.018 0.0�� F 0.0�5 0.060 0.070 G — 0.1 BSC —H 0.300 0.310 0.3�5 I — — 0.�30

SymbolDimensions in mm

Min. Nom. Max.A 1�.81 �0.07 �0.3� B 6.10 6.35 7.11C �.�� 3.30 �.�5D �.�� 3.30 3.81E 0.36 0.�6 0.56F 1.1� 1.5� 1.78G — �.5� BSC —H 7.6� 7.87 8.�6I — — 10.��

Rev. 1.00 7� ��ne 1�� 01� Rev. 1.00 75 ��ne 1�� 01�



Fig 2 (Type 1)


Min. Nom. Max.A 0.7�5 0.765 0.785 B 0.�75 0.�85 0.��5 C 0.1�0 0.135 0.150 D 0.110 0.130 0.150 E 0.01� 0.018 0.0�� F 0.0�5 0.050 0.060 G — 0.1 BSC —H 0.300 0.310 0.3�5 I — — 0.�30


Min. Nom. Max.A 18.�� 1�.�3 1�.�� B 6.�� 7.�� 7.�� C 3.05 3.�3 3.81 D �.7� 3.30 3.81 E 0.36 0.�6 0.56 F 1.1� 1.�7 1.5� G — �.5� BSC —H 7.6� 7.87 8.�6 I — — 10.��

Fig 2 (Type2)


Min. Nom. Max.A 0.735 0.755 0.775 B 0.��0 0.�50 0.�80 C 0.115 0.130 0.1�5 D 0.115 0.130 0.150 E 0.01� 0.018 0.0�� F 0.0�5 0.060 0.070 G — 0.1 BSC —H 0.300 0.310 0.3�5 I — — 0.�30


Min. Nom. Max.A 18.67 1�.18 1�.6� B 6.10 6.35 7.11 C �.�� 3.30 �.�5 D �.�� 3.30 3.81 E 0.36 0.�6 0.56 F 1.1� 1.5� 1.78 G — �.5� BSC —H 7.6� 7.87 8.�6 I — — 10.��

Rev. 1.00 7� ��ne 1�� 01� Rev. 1.00 75 ��ne 1�� 01�



16-pin NSOP (150mil) Outline Dimensions

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Min. Nom. Max.A — 0.�36 BSC —B — 0.15� BSC —C 0.01� — 0.0�0C’ — 0.3�0 BSC —D — — 0.06�E — 0.050 BSC —F 0.00� — 0.010G 0.016 — 0.050H 0.00� — 0.010α 0° — 8°


Min. Nom. Max.A — 6.0 BSC —B — 3.� BSC —C 0.31 — 0.51C’ — �.� BSC —D — — 1.75E — 1.�7 BSC —F 0.10 — 0.�5G 0.�0 — 1.�7H 0.10 — 0.�5α 0° — 8°

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The information appearing in this Data Sheet is believed to be acc�rate at the time of p�blication. However� Holtek ass�mes no responsibility arising from the �se of the specifications described. The applications mentioned herein are used solely for the p�rpose of ill�stration and Holtek makes no warranty or representation that s�ch applications will be s�itable witho�t f�rther modification� nor recommends the �se of its prod�cts for application that may present a risk to h�man life d�e to malf�nction or otherwise. Holtek's prod�cts are not a�thorized for �se as critical components in life s�pport devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit o�r web site at http://www.holtek.com.tw.

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