cooling system using nanotechnology

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A complete carbon-nanotube-basedon-chip cooling solution with very highheat dissipation capacity

AbstractHeat dissipation is one of the factors limiting the continuous miniaturization of electronics. In

the study presented in this paper, we designed an ultra-thin heat sink using carbon nanotubes

(CNTs) as micro cooling fins attached directly onto a chip. A metal-enhanced CNT transfer

technique was utilized to improve the interface between the CNTs and the chip surface by

minimizing the thermal contact resistance and promoting the mechanical strength of the

microfins. In order to optimize the geometrical design of the CNT microfin structure,

multi-scale modeling was performed. A molecular dynamics simulation (MDS) was carried

out to investigate the interaction between water and CNTs at the nanoscale and a finite

element method (FEM) modeling was executed to analyze the fluid field and temperaturedistribution

at the macroscale. Experimental results show that water is much more efficient than air as a

cooling medium due to its three orders-of-magnitude higher heat capacity. For a hotspot with

a

high power density of 5000 W cm2 , the CNT microfins can cool down its temperature by

more than 40

C. The large heat dissipation capacity could make this cooling solution meet the

thermal management requirement of the hottest electronic systems up to date.

(Some figures may appear in colour only in the online journal)

Introduction:

The development of integrated

circuits has followed Moores law

for more than 40 years.

Continuous size shrinking of the

transistors has allowed more

components to be integrated in asingle unit area but

simultaneously increased the

power density in electronics to a

high level that brings huge

challenges [15] to traditional

cooling schemes with

a typical cooling capability ofabout 50 W cm2 [6, 7].Furthermore, the growth of chipfunctionality and complexity

has introduced hotspots onto chipsurfaces, resulting in localizedheat fluxes up to 3001000 Wcm2 [810]. This adds extradifficulties to an efficient coolingbecause the high power densitydramatically decreases thecooling capability ofconventional heat sinks [8, 1114]. A poor cooling not only

lowers the performance ofelectronic products but alsosignificantly shortens theirlifetime. Therefore, there is astrong demand in the electronicsindustry to develop highperformance cooling solution.


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Figure 1. Design and fabrication process of the interface-enhanced CNT microfin on-chip cooling system. (a) Clean Si wafer with SiO2layer. (b) Fabrication of heating elements and temperature sensors on test chips. Temperature sensors are calibrated by standard RTD.(c) Evaporation of Ti/Au/In for CNTsubstrate interface enhancement. (d) Patterning of Al2 O3 /Fe catalyst layer (10/1 nm thick) for CNTgrowth on Si substrate by standard photolithography and lift-off processes. (e) Growth of CNT microfins by TCVD using acetylene ascarbon precursor. (f) Metal-enhanced CNT transfer onto the test chip surface acting as on-chip cooling microfins. Contact resistance isreduced and adhesion between CNTs and substrate is improved due to the metal enhancing layer. (g) A plastic cover is assembled ontothe test chip to form microchannels. The cover is transparent so thatthe CNT microfins and coolant flow in the microchannels are visible.(h) CNT cooling fin integrated test chip soldered onto supporting substrate. (i) 3D structure in (h). (j), (k) Coolant flow path assembledonto the test chip using adhesive. (l) The test chip with on-chip CNT cooling fins packaged by PDMS for mechanical protection.

As a potential solution, a liquid-assisted microchannel

cooling scheme was proposed because of the large heat

exchange area, small size, light weight, etc [15]. In

the past few decades, progress has been reported on

developing integration schemes and realizing the great

potential for electronics cooling by this approach [2, 3,

1518]. Experimental results showed that a coolingcapability of 38790 W cm

2 could be achieved.However, it shouldbe mentioned that all these cooling effects were obtained

on uniformly heated chip surfaces. Introducing hotspots intothe chips, thus increasing the power density factor (power

density factor is the ratio of package thermal resistance at

the hottest spot to the die-area-normalized uniform power

resistance [11], e.g. for a hotspot with area A1 located at the

center of a die with area A2 , the power density factor equals

A2 /A1 ), the cooling performance of these demonstrators

could be degraded by an order of magnitude [8, 10, 11, 13].

This is attributed to the highly non-uniform temperature

distribution. In order to make full use of the advantage of the

microchannel cooler, more efficient cooling fins, better heat

spreading on the chip surface and through the chipcooler

interface need to be created.

Carbon nanotubes (CNTs) have been reported to possesshigh thermal conductivity up to 6600 W m

1 K1 [1924]

and have thus attracted intensive interest in using them as

high performance thermal interface materials (TIMs) [25

30] for effectively dissipating heat from active components

to heat sinks. However, this alone cannot fully realize the

cooling

purpose if the thermal energy generated by components

exceeds the cooling capability of the heat sinks [1, 31].

Therefore, CNTs were proposed to be used as

microchannel cooling fins due to their special geometrical

structure, outstanding mechanical properties [32, 33] and

exceptional thermal performance. A primary enhancement of

15 W cm2 of heat dissipation was achieved using water as

the coolant [34, 35]. A more recent investigation by Kordas

et al showed that CNT microfins can dissipate 100 W cm2

more power under forced nitrogen (N2 ) convection [36].Having these gains in cooling capability demonstrated, we

report a design of directly fabricating CNT microfins onto

chip surfaces to make microchannels for extremely high

efficiency water-assisted cooling, thus integrating the

benefits from both the microchannel structure and the high

thermally conductive CNTs (figure 1). The fabrication

process was based on an active thermal test chip with

integrated heating elements and thermal sensing function

(figure 1(b)). A unique metal-enhanced CNT transfer method

was applied to plant the previously grown CNT microfins

onto the test chip surface (figures 1(b) and (f)) so that the

contact resistance was reduced and the mechanical

connection was improved [37]. The test chip was then

soldered onto a supporting substrate (figures 1(g) and (h)).

After the assembly of the coolant flow path (figures 1(i)

(k)), the entire functional system was packaged in

polydimethylsiloxane (PDMS) (figure 1(l)). To assist

designing the cooling system, multi-scale modeling was

performed to optimize the CNT microfin structures.


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Nanotechnology 23 (2012) 045304 Y Fu etal

Figure 2. (a) Configuration of a (5, 5) CNT and water contact interface Since a periodic boundary condition is applied inthis simulation,the CNT and water structure can be considered as having an infinite length. (b) Temperature distribution on the Si chip and microfinstructure, under a power density of 400 W cm

2, a water velocity of 0.1 m s1 and a channel width of 50 m. (c) Dependence of on-chip

temperature and pressure drop on the microchannel width. The on-chip temperature decreases linearly with smaller channel width whilepressure drop between channel inlet and outlet increases exponentially with decreasing channel width. The coolant velocity is 0.1 m s

1.

2. Experiments and modeling

2.1. Fabrication of the test chip

layer. These two water layers both remain a thickness of 2 A

. The interfacial contact resistance between CNT and wateris then calculated by

The test chip was integrated with heating resistors and

temperature sensors, acting as a platform for simulating a

real

1Rthermal =

T A

Q(1)

electronic component to demonstrate the cooling capability

of the entire system. The temperature sensors were made

of titanium/platinum/gold (Ti/Pt/Au) with a thickness of

20/180/50 nm. The Ti layer was used to promote theadhesion between Pt and the SiO2 surface. Pt was

selected as the temperature-sensing material due to itsexcellent temperature

resistance linear relationship up to 800 C [38]. The Au

layer

on the top can protect the sensor from erosion and ease the

soldering of the test chip onto a supporting substrate. Once

fabricated, the sensors were calibrated by a standard

resistance temperature detector (RTD) [39]. The repeatable

and stable reading from the sensors ensures a reliable

temperature measurement for characterizing the cooling

system.

2.2. Multi-scale modeling foroptimizing CNTmicrofin structure

Because the performance of heat sinks is closely related to

the geometry of the cooling fins and the water flow in the

microchannels [31, 40], multi-scale modeling was carried out

to optimize the CNT microfin structure.

It has been known that the contact resistance between

CNTs and the surrounding medium plays an important role

on the thermal transportation through the interfaces [4143].

In our study, water is driven to flow through the

microchannels to remove thermal energy from the CNT

microfins. It is therefore crucial to clarify how efficient is the

heat transferred through the CNTwater interface. Molecular

dynamics simulation (MDS) was herein executed to

investigate the interaction between water and CNTs. Figure2(a) shows the configuration of a (5, 5) CNT (lies at the

center) and the surrounding water molecules. A heat flux Q

is loaded onto the CNT wall and spreads outwards the

water. The blue layer highlights the water layer which is the

most adjacent to the CNT surface,

while a heat flux ofQ is loaded on the outer green water

where 1T is the temperature difference between the CNT

surface and the blue water layer, and A is the area of the

CNT wall. More details on the MDS are presented in figure

S1 (available atstacks.iop.o r g/Nano/23/045304/mmedia).

Calculation results show that a contact resistance of

1.47 107 K m2 W

1 exists on the interface, which

is subsequently applied as the input to the finite elementmethod (FEM) simulation. As a result of the comprise

of the computational time and modeling precision, five

microfins are bonded by a thin TIM layer to the chip

surface in the FEM model. Figure 2(b) shows an example

of how the coolant flows through the microchannels and the

final temperature distribution on the Si chip and microfins.

The dependence of temperature and pressure drop on the

microchannel dimension is extracted after the numerical

calculations, as plotted in figure 2(c) (more details are

available in the supporting material available at stacks.iop.

org/Nano/23/045304/mmedia). The temperature on the chip

decreases approximately linearly with smaller channel width.

Nevertheless the pressure drop between the channel inlet and

outlet increases exponentially with decreasing channel width.

Therefore, from a thermal dissipation point of view, smaller

channel width is favorable. However, for the energy-saving

and reliability consideration, a larger channel width is

preferable. To handle this trade-off, a microchannel width of

50 m is selected for building up the demonstrator.

In the FEM modeling, thermal conductivity of theCNT fins was set to be 50 W m

1 K1 in the direction

perpendicular to the tubes and 3000 W m1 K

1 [22]along the tube axis. In order to compare with traditional

materials such as copper and take the porosity of CNT fins

into consideration, thermal conductivity of the cooling fins

along the tube axis varying from 10 to 3000 W m1 K1

were simulated. The thermal conductivity in the direction
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Figure 3. CNT microfins transferred onto the test chip. (a) The test chip with integrated heating elements and temperature sensors. (b)CNT microfins grown on Si substrate with a height of about 250 m and in a pitch of 100 m, following the optimized dimension bymulti-scale modeling. 10/1 nm Al2 O3 /Fe was utilized as the catalyst for CNT growth and acetylene (C2 H2 ) is utilized as carbon precursor.The growthwas performed at a low pressure 10 mbar. (c) Locally magnified image of CNT appearance in the microfins. (d) CNT microfinstransferring from the growth chip to the test chip. Prior to contact with the melting In on the test chip, the as-grown CNT microfins weresputtered by 20/100 nm thick Ti/Au on the tips in order to enhance the interface. A multilayer of 20/100/1000 nm thick Ti/Au/In wasevaporated onto the test chip as the transfer receptor. The transfer process was performed using a flip chip bonder so that the temperatureon both of the two chips can be controlled and the CNT microfins can be placed at the desired position. (e) CNT microfins transferred ontothe test chip.

perpendicular to the tube axis was correspondingly modified

with the same factor. Results show that, when the thermal

conductivity is relatively low, the cooling effect of the

microfins increases exponentially with increasing thermal

conductivity, whereas the improvement of the cooling effect

becomes smaller and smaller when the thermal conductivity

is higher than 100 W m1 K

1 (see figure S1(c) available

at stacks.iop.o r g/Nano/23/045304/mmedia). This agrees well

with the theoretical calculation for rectangular fins mounted

on a flat surface [44].

2.3. CNT microfin transfer

Although CNTs themselves possess outstanding thermal and

mechanical properties, their real performance in devices is

greatly limited and degraded by three factors, (a) the huge

contact resistance between the CNT ends and the substrate

surface [27, 30, 45], (b) the high growth temperature [46, 47]

of CNTs and (c) the weak van der Waals binding between

the CNTs and the growth substrate [48, 49]. In order to

remove these obstacles, we developed an interface-enhanced

CNT transfer technique to plant the CNT microfins onto the

test chip from the original growth substrate [37].The microfin structures were defined by standard

photolithography and lift-off processes. The CNTs were

grown by thermal chemical vapor deposition (TCVD) at low

pressure with a 10/1 nm thick Al2 O3 /Fe layer as catalyst

[50]. The height of the CNT microfins was controlled by

adjusting the growth time to be about 250 m in this study

(figures 3(b) and (c)). After growth, 20/100 nm thick Ti/Au

was sputtered onto the CNT tips. On the other hand, a

multilayer of Ti/Au/In with thicknesses of 20/100/1000 nm

was evaporated onto the test chip surface for CNT microfin

transfer (figure 1(c)). The Ti layer sputtered onto the CNT

tips can effectively decreases the contact resistance [37, 51]

and Au was demonstrated to have very good interaction

behavior with low melting point metal In [52]. The transfer

process was performed using a flip chip bonder so that

both the test chip and the growth chip can be properly

heated up, and the CNT microfins can be placed at the

desired position (figures 1(f) and

3(d)). After the transfer process, electrical characterization

on the CNT structures indicated that the CNTsubstrate

resistance is reduced by one order of magnitude with the

presence of a Ti/Au enhancing layer [37]. Shear test on

the substrate (growth)CNTsubstrate (target chip) bonding

structure showed that the shear strength between CNTs and

the target substrate surface is improved by about two ordersof magnitude [37]. More details on the electrical

characterization and shear test of the transferred CNTs are

presented in figure S2 (available at

stacks.iop.o r g/Nano/23/045304/mmedia).

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Figure 4. CNT on-chip cooling system assembly. (a) Side view of the CNT microfin mounted test chip soldered onto the supportingsubstrate. The total thickness including the test chip itself is about 1.5 mm. (b) Top view of the test chip soldered onto the supportingsubstrate. The CNT microfins are visible through the transparent lid which eases the observation when coolant flows through themicrochannels. (c) Coolant flow path is assembled using adhesive. (d) PDMS-encapsulated CNT on-chip cooling system. The circuit onthe substrate is used for electrical powering and temperature measurement. The two nozzles are used for coolant flowing through themicrochannels.

2.4. On-chip cooling systempackaging

Once the CNT microfins were transferred onto the test chipsurface, a plastic lid was covered on the top of the CNT

microfins to create microchannels (figure 1(g)). The lid is

transparent so that the CNT fins and water flow are visible

during the whole experiment process. Then, the test chip

with on-chip microfin channels was soldered onto a

supporting Si substrate for electrical connection (figures

1(h), 4(a) and (b)). Afterwards, two aluminum chambers

were attached onto two ends of the test chip to introduce

coolant into and out of the microchannels (figure 1(j)).

Finally, the coolant inlet and outlet nozzles were mounted

onto the aluminum chamber using an adhesive (figures 1(k)

and 4(c)). After the coolant flow path was assembled,

PDMS was used to encapsulate the whole system (figure4(d)) to protect it from mechanical damage and to prevent

coolant leakage.

3. Results and discussion

In order to characterize the on-chip cooling performance

of the CNT microfins, a pump was used to drive air

and water flowing through the microchannels as coolant

(figure 5(a) and the supplementary movie available at stacks.

iop.org/Nano/23/045304/mmedia). The test chip was heated

up by a small hotspot (390 400 m2 ) located at the

center of the chip, which results in a very large powerdensity factor of 320 cm

2 [11]. Thermal energy was spreadoutward to the entire chip surface and to the CNT microfins

through the TiAuInAuTi metal interfaces. Results show

that, with water as coolant, the chip temperature can be

dramatically decreased from an up-limit point (150

C,which is close to the melting point of transfer materialIn) to below 100

C under an extremely high local heatflux of 5000 W cm

2 (figure 5(b)). With a higher watervelocity, there is stronger heat exchange between the CNT

microfins and water, thereby leading to a continuous

decrease of chip temperature. On the other hand, keeping the

constant

temperature on the chip surface, 100

C for instance, the

on-chip cooling system can easily dissipate 2000 W cm2

more power with water velocity increased from 0.048 m s1

to relatively higher, 0.323 m s1 . In order to compare

with traditional air cooling, air was also driven through the

microchannel structure prior to the water cooling. With anair flow velocity of 3.23 m s

1 , which is almost two orders

of magnitude higher than water velocity at 0.048 m s1 ,

the chip temperature is still much higher than that of watercooling (for example, under a heat flux of 3000 W cm

2 ,chip temperature is about 120

C with air cooling comparedto105

C with water

cooling).

Compared with the traditional forced air convectioncooling method which can achieve 50 W cm

2 coolingcapability [6, 7], the CNT microfin on-chip cooling scheme

has demonstrated the ability to handle a heat flux as

high as 7000 W cm2 , and this can be even higher

with thicker CNT microfins and higher water velocity. In

contrast to previous research results using other materials

as microchannel cooling fins, the structure demonstrated in

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Figure 5. (a) PDMS-packaged CNT microfin on-chip cooling system connected with coolant source and power source. CNT microfinsare still visible after packaging. (b) CNT microfin on-chip cooling performance characterization using water and air as coolant. Althoughair velocity is more than one order of magnitude higher, the cooling capability is still much lower than that of water. With increasing watervelocity, the temperature on the test chip is dramatically decreased under the same power load. For instance, at a local heat flux of5000 W cm

2, the chip can be cooled down from 138 to 98

C with water velocity increases from 0.081 to 0.323 m s1. (c) Cooling

efficiency comparison between the on-chip cooler with and without cooling fins. Using air as coolant, the two coolers havesimilar efficiency, whereas using water as coolant, the cooler with CNT fins has higher efficiency.

this study has a power density factor which is two ordersof magnitude higher(320 cm2 versus 14 cm2 ) [2,3,1317, 53] while still dissipating much higher heat flux on

the chip. More detailed comparisons with previous results are

listed in table S2 (available at

stacks.iop.o r g/Nano/23/045304/ mmedia). We attribute the

high cooling efficiency to three factors: (a) low contact

thermal resistance due to the enhanced CNTsubstrate

interface. The TiAuInAuTi-enhancing layer can

decrease the contact resistance by more than one order

of magnitude [37]. (b) Effective heat transport originated

from the intrinsic high thermal conductivity of the

CNTs [1924] and (c) from the extremely large

surface/volume ratio of the unique one-dimensional CNTstructure. In figure S3 (available at stacks.iop.o r g/Nano/23/

045304/mmedia), we have verified that water can enter the

space between the CNTs in the microfins. Assume the

CNTs in the forest have a configuration as shown in figure

S4 (available at stacks.iop.o r g/Nano/23/045304/mmedia), the

porosity in the CNT forest is about 91.4%, which is very

close to the experimentally measured value (92%) for typical

CVD-synthesized multi-walled CNTs [54]. In this case, the

heat exchange area of the CNT microfins is about 1000

times higher than that of traditional copper fins (see detailed

calculation in figure S4 available at stacks.iop.o r g/Nano/23/

045304/mmedia).

Air was also driven through the CNT microfins.However, the cooling capability is much lower even if the air

velocity is about two orders of magnitude higher than the

water velocity. This is reasonable since water has three

orders-of-magnitude higher volume heat capacity than air,

i.e. assuming the same temperature difference between

water/air and CNT microfins, the air velocity has to be three

orders of magnitude higher than that of water in order to

dissipate the same amount of thermal energy.

An on-chip cooler without CNT cooling fins was

also fabricated following the same processes as described

above for comparison. The packaged device is shown in

figure S5(a) (available at stacks.iop.o r g/Nano/23/045304/mmedia). Cooling examination was carried out under the

same conditions as loaded on the CNT cooler. Detailed

experimental results are displayed in figure S5(b) (availableat stacks.iop.o r g/Nano/23/045304/mmedia). Similar to the

CNT cooler, the cooling efficiency of the cooler without

cooling fins increases with increasing coolant velocity.

Furthermore, the cooler without cooling fins presented

similar cooling efficiency, compared to the CNT cooler,

when air was used as the coolant, as shown in figure 5(c).

However, replacing air by water as coolant, the cooling

efficiency of the CNT cooler was obviously higher than the

cooler without cooling fins. We attribute the different

cooling behavior (little difference in cooling efficiency

when using air as coolant but large difference when using

water as coolant) to the different heat capacity of air andwater.

4. Conclusions

We have demonstrated the application of interface-enhanced

CNTs as on-chip cooling fins in a microchannel heat

sink. Although the cooling performance becomes more and

more stable after the thermal conductivity of the cooling

fins is higher than 100 W m1 K

1 , the extremely large

heat exchange area in the CNT microfins makes the heat

dissipation very efficient so that the on-chip cooling structure

can handle a heat flux at 1000 W cm2 scale with the

assistance of water. Benefiting from the metal-enhanced

CNT interface, the excellent thermal performance and the

huge surface/volume ratio of CNTs, this water-assisted CNT

microfin on-chip cooling solution exhibits a great capability

of cooling down very high power density electric

components, and is possible to meet the requirement for

managing the thermal budget of the hottest electronic

systems to date.

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