Goran wnis hama AliSystem Bus in Computer Architecture1The CPU sends various data values, instructions and information to all the devices and components inside the computer.

If you look at the bottom of a motherboard you'll see a whole network of lines or electronic pathways that join the different components together.

This network of wires or electronic pathways is called the 'Bus'.

INTRODUCTIONBottom of motherboard

INTRODUCTION (contd)

A bus is a communication pathway connecting two or more devices.A key characteristic of a bus is that it is a shared transmission medium.Multiple devices connect to the bus, and a signal transmitted by any one device is available for reception by all other devices attached to the bus.If two devices transmit during the same time period, their signals will overlap and become garbled. Thus, only one device at a time can successfully transmit.BUSTypically, a bus consists of multiple communication pathways, or lines. Each line is capable of transmitting signals representing binary 1 and binary 0. several lines of a bus can be used to transmit binary digits simultaneously (in parallel).For example, an 8-bit unit of data can be transmitted over eight bus lines.Computer systems contain a number of different buses that provide pathways between components at various levels of the computer system hierarchy. BUS contdA bus that connects major computer components (processor, memory, I/O) is called a system bus.A system bus consists, typically, of from about fifty to hundreds of separate lines. Each line is assigned a particular meaning or functionSystem bus usually is separated into three functional groups . Data Bus Address Bus Control BusIn addition, there may be power distribution lines that supply power to the attached modules.

SYSTEM BUS

SYSTEM BUS MODELA collection of wires through which data is transmitted from one part of a computer to another.Data Bus can be thought of as a highway on which data travels within a computer.This bus connects all the computer components to the CPU and main memory.The data bus may consist of 32, 64, 128, or even more separate lines.The number of lines being referred to as the width of the data bus. Because each line can carry only 1 bit at a time, the number of lines determines how many bits can be transferred at a time.DATA BUSIt is a bidirectional bus.The size (width) of bus determines how much data can be transmitted at one time.E.g. A 16-bit bus can transmit 16 bits (2 bytes)of data at a time. 32-bit bus can transmit 32 bits(4 bytes) at a time.The size (width) of bus is a critical parameter in determining system performance.The wider the data bus, the better, but they are expensive. DATA BUS contdADDRESS BUSIt is an unidirectional bus.

The CPU sends address to a particular memory locations and I/O ports.

The address bus consists of 16 , 20 , 24 or more parallel signal lines.

ADDRESS BUS contd 8086: 20 address lines Could address 1 MB of memory Pentium: 32 address lines Could address 4 GB of memory Itanium: 64 address lines Could address 264 bytes of memoryADDRESS BUS contdCONTROL BUSBecause the data and address lines are shared by all components, there must be a means of controlling their use.The control lines regulates the activity on the bus. Control signals transmit both command and timing information among system modules.The control bus carries signals that report the status of various devices. Typical control bus signals are :Memory Read : causes data from the addressed location to be placed on the data bus.Memory Write : causes data on the bus to be written into the addressed locationI/O write: causes data on the bus to be output to the addressed I/O portI/O read: causes data from the addressed I/O port to be placed on the busCONTROL BUSThe following figure shows how the CPU reads the value 12 from the memory location 2453:Example : Memory Read

CPU sends out the address value 2453 on theaddress busSimultaneously, CPU sends out the signalR/W = 1on thecontrol bus,which indicates aREADoperationCPU then waits for the data from memory on thedata busTheR/W = 1signal and the address bus value 2453 will cause the memory to retrieve the value at memory location 2453 to be sent out on the data bus

Example: Memory Read contdAddress of next instruction is in PCAddress (MAR) is placed on address busControl unit issues READ commandResult (data from memory) appears on data busData from data bus copied into MBRPC incremented by 1 .Data (instruction) moved from MBR to IRMBR is now free for further data fetches

Memory Read a Closer look The following figure shows how the CPU writes the value 53 from the memory location 2453:Example: Memory Write

CPU sends out the address value 2453 on theaddress busSimultaneously, CPU also sends out the value 53 on thedata busAnd the signalR/W = 0on thecontrol buswhich indicating a WRITE operationTheR/W = 0signal along with the address bus value 2453 and data bus value 53 will cause the memory to store the value 53 at the location 2453...

Example: Memory Write contdControl lines also include :Transfer ACK: indicates that data have been accepted from or placed on the bus.Bus request: indicates that a module needs to gain control of the bus. Bus grant: indicates that a requesting module has been granted control of the bus.Control Bus contd Interrupt request: indicates that an interrupt is pending. Interrupt ACK: acknowledges that the pending interrupt has been recognized.Reset: initializes all modules.

Control Bus contdNeed to consider several design issues : Bus width Data and address buses. Bus type Dedicated or multiplexed. Bus operations Read, write, block transfer, interrupt, Bus arbitration Centralized or distributed. Bus timing Synchronous or asynchronousBus Design IssuesDedicated buses Separate buses dedicated to carry data and address information. Good for performance. But increases cost. Multiplexed busesData and address information is time multiplexed(defined in the next slide ) on a shared bus.Poor PerformanceBut Reduces cost.Bus TypeAddress and data information may be transmitted over the same set of lines using an Address Valid control line. At the beginning of a data transfer, the address is placed on the bus and the Address Valid line is activated. At this point, each module has a specified period of time to copy the address and determine if it is the addressed module. The address is then removed from the bus, and the same bus connections are used for the subsequent read or write data transfer. This method of using the same lines for multiple purposes is known as time multiplexing. The advantage of time multiplexing is the use of fewer lines.Time Multiplexed BusBasic operationsRead and write.Block transfer operations. Read or write several contiguous memory locations. Example: cache line fill.

Interrupt operation.Bus OperationsIn all but the simplest systems, more than one module may need control of the bus.For example, an I/O module may need to read or write directly to memory, without sending the data to the processor.Because only one unit at a time can successfully transmit over the bus, some method of arbitration is needed.Bus arbitration can be done either Statically.Dynamically. Bus ArbitrationDone in a predetermined way.For example , we might use round-robin allocation that rotates the bus among the masters.Easy to implement.A master may be given a bus even it does not need it.This kind of allocation leads to inefficient use of the bus.Static Bus Arbitration DMR with I/O devices.27Bus allocated only in response to a request.Each master is equipped with; Bus request line. Bus grant line. A master uses the bus request line to let others know that it needs the bus. Before a master can use the bus, it must receive permission to use the bus via the bus grant line.Dynamic Bus Arbitration28Distributed arbitration Arbitration hardware is distributed among the masters. A distributed arbitration algorithm is used to determine who should get the bus.Dynamic Bus Arbitration contd

Fixed priority Each master is assigned a fixed priority. Highest priority master always gets the bus. Priorities can be assigned based on the importance of service. Rotating priorityPriority is not fixedSeveral ways of changing priorityIncrease the priority as a function of waiting timeLowest priority for the master that just received the busBus Allocation PoliciesGoverns the conditions under which the current master releases the busTwo typesNon-preemptive.Current master voluntarily releases the bus. DisadvantageMay hold bus for long time.PreemptiveForces the current master to release the bus without completing its bus transaction.Bus Release Policies Transaction-based release Releases bus after completing the current transaction. Requests bus again if it has more transactions. Easy to implement. Unnecessary overhead if only one master needs the bus. Demand-driven release Avoids unnecessary bus requests of the previous policy. Releases the bus only if another master requests the bus. More efficient.Non-Preemptive Bus Release PoliciesDaisy-chainingUses a single, shared bus request signal Central arbiter sends the grant signal to the first master in the chainEach master passes the grant signal to its neighbor if it does need the busGrabs the grant signal if it wants the busEasy to implementCentralized bus arbitration

Independent requestsArbiter is connected to each master Variety of bus allocation policies can be implemented. Disadvantages Complex to implement.PCI uses this implementation technique.Centralized bus arbitration contd