computer architecture lecture 2: processor, program cycle, interrupts, system bus piotr bilski
TRANSCRIPT
Computer Architecture
Lecture 2: Processor, program cycle, interrupts, system bus
Piotr Bilski
von Neumann Machine
Main memory
I/O devices
CPU
MBR
AC
MAR
PC IR CU
ALU
Internal bus
I/O AR
I/O BR
Program
• Program is a set of instructions which, executed is a predefined order, assures processing of the information in a desired way.
• Instruction is a machine word, containing information about the executed instruction and memory location, where arguments, results and the next instruction are stored.
Requirements for the computer system executing program (von
Neumann)Computer system should:• Have finite and functionally coherent instruction list;• Be able to insert program into the computer system using
external devices and store instructions in the memory in the identical way as data;
• Store data and instructions in the memory in a way that they were equally accessible for the processor (by the addresses in the memory);
• Be able to process the information by sequential reading of the instructions from the memory and executing them by the processor .
Program vs hardware „program”
X1
X2
X3
X4
Y1
Y2
X1
X2
X3
X4
Y1
Y2
0000: move 4
0001: add 5
0010: store 6
0011: stop
control
Hard-wired program
Computer operation
STARTInstruction fetching
Instruction execution
STOP
Interrupt execution
Fetch cycle Execution cycle
Interrupt cycle
Interrupts valid?
NO
YES
Register transfer language• Symbols of capital letters stand for the content • M – memory• A, MAR etc. – register• writing• ( ) – address• 0:7 – range of bits of the memory word or
registry, used in the operation
For instance: MAR PC
MBR M(MAR)
Instruction fetching cycle
• Program counter (PC) stores address of the next instruction to acquire (at the beginning it is so called entry point)
• Processor fetches instruction from the address pointed by PC
• Value of the PC is increased by 1 (unless something else is required - jump)
• Instruction is loaded into the instruction register (IR)• Processor decodes instruction and executes
operation pointed by it
Illustration of the instruction fetching cycle
MBRAC
MAR
PC IR CU
ALU
ADDRESS BUS
Entry point
MAR PC
Address Content
100 Move 104
101 Add 105
102 Store 106
103 Stop
104 3
105 5
106 100
MBRAC
MAR
PC IR CU
ALU
CONTROL BUS
READ
101
DATA BUS
ADDRESS BUS
MBR M(MAR)Move 104
Illustration of the instruction fetching cycle (cont.)
Address Content
100 Move 104
101 Add 105
102 Store 106
103 Stop
104 3
105 5
106
MBRAC
MAR
PC IR CU
ALU
CONTROL BUS
PC PC + 1READ
100
DATA BUS
ADDRESS BUS
Move 104
101
Illustration of the instruction fetching cycle (cont.)
Address Content
100 Move 104
101 Add 105
102 Store 106
103 Stop
104 3
105 5
106
MBRAC
MAR
PC IR CU
ALU
CONTROL BUS
READ
100
ADDRESS BUS
Move 104
101
Move 104
IR MBR
Illustration of the instruction fetching cycle (cont.)
DATA BUS
Address Content
100 Move 104
101 Add 105
102 Store 106
103 Stop
104 3
105 5
106
MBRAC
MAR
PC IR CU
ALU
CONTROL BUS
READ
100
DATA BUS
ADDRESS BUS
Move 104
101
Move 104CU IR
Illustration of the instruction fetching cycle (cont.)
Address Content
100 Move 104
101 Add 105
102 Store 106
103 Stop
104 3
105 5
106
Instruction execution cycle
• Processor-memory– data transfer between CPU and memory
• Processor – input/output– data transfer between CPU and input/output module
• Data processing– Arithmetic or logical operations on the data – Change of the instruction execution order (for
example, jump)
• Control• Combination of the above
MBRAC
MAR
PC IR CU
ALU
CONTROL BUS
104
Data BUS
ADDRESS BUS
3
101
Move 104
READ
MAR IR(104)
104
MBR M(104)
AC MBR
Illustration of the instruction execution cycle (cont.)
Address Content
100 Move 104
101 Add 105
102 Store 106
103 Stop
104 3
105 5
106
Next instruction fetching cycle
MBRAC
MAR
PC IR CU
ALU
CONTROL BUS
101
DATA BUS
ADDRESS BUS
101
READ
Add 105
MAR PC
MBR M(101)
Address Content
100 Move 104
101 Add 105
102 Store 106
103 Stop
104 3
105 5
106
MBRAC
MAR
PC IR CU
ALU
CONTROL BUS
101
DATA BUS
ADDRESS BUS
101
READ
Add 105
IR MBR
CU IRAdd 105
Next instruction fetching cycle (cont.)
Address Content
100 Move 104
101 Add 105
102 Store 106
103 Stop
104 3
105 5
106
Instruction format
0 3 4 15
0 1 15
Operation code Address
Size
Sign
For example Move 104 - 0101000001101000
instruction argument
State graph of the instruction cycle
Fetch instr.
Calculate instr.
address
Instr. decode
Calculate argument addr.
Fetching argument
Data operation
Check for
interrupts
Interrupt execution
Calculate argument addr.
Saving argument
Instruction executed, fetch the next one
Many arguments
Many results
No interrupts Return to data
Interrupts
• Mechanism allowing to disturb the original execution order by the other system components
• Programmed– For example, overflow, divide by zero
• Clock-generated– Generated by the internal processor clock– Used for process scheduling
• Input/Output– From the I/O controller
• Hardware failure– Memory parity error
Application of the interruptsUser program
1
2
3
WRITE
WRITE
I/O program
4
5
I/O instruction
User program
1
2a@2b
3a@3b
WRITE
WRITE
I/O Program
4
5
I/O instruction
Interrupt execution program
Stop
Stop
Interrupt cycle
• Processor checks periodically, if the interrupt ocurred– It is shown by the interrupt signal
• If no interrupt occured, the next instruction is fetched
• If the interrupt occured:– The executed program is suspended– Its context is saved– Program counter is set to the address of the first
instruction of the interrupt execution program– Interrupt is processed– After that, the previous context is loaded to the CPU
and the user program is executed from the point it was suspended
Multiple interrupts
Two ways of the multiple interrupts execution exist• Blocked interrupts
– Processor ignores other interrupts while the current interrupt is processed
– Interrupts are queued and after the current interrupt is processed, the next one (if exists) is processed
– Interrupts are executed in the sequence they occured
• Priorities– Execution of the low priority interrupt can be suspended
by the higher priority interrupt– After execution of the higher priority interrupt the
execution of the low priority interrupt is continued
Multiple interrupts execution
User program Interrupt nr 1
Interrupt nr 2
User program Interrupt nr 1
Interrupt nr 2
Sequential execution Priority execution
Example of the interrupts assignment
Data flow in the computer modules
MEMORY
N words
INPUT / OUTPUT MODULE
M ports
PROCESSOR
ADRESS
DATA
DATA
DATA DATA
ADRESS
ADRESSINSTR.
readwrite
writeread
Internal data
External data
Internal data
External data
INT. INT.
INT.
BUS
• The highway to allow communication between the devices
• Includes multiple trails of the three types: data, address and control
• Breadth of the bus is the maximum number of bits, which can be transferred between the modules
The main buses
• ISA (1985)• PCI (1993)• AGP 1x/2x (1997-1998)• AGP 4x (1999)• AGP 8x (2002)• PCI Express (2004)• SCSI (1979)• Industrial busses (PROFIBUS, IEC-625)
Buses bandwidth
How does it work?
Communication between the two modules
Sending data:
1. Accessing the bus
2. transferring the data
Receiving data:
3. Accessing the bus
4. Informing about the need to acquire data (using control lines)
5. Awaiting the incoming data
„Flat” bus structure (ISA)
Hierarchical bus structure
Buses categories
Application• Specialized• MultiplexedArbitration method• Centralized• DistributedTime synchronization• Synchronous• Asynchronous
Synchronous coordination
Asynchronous coordination
Read
Asynchronous coordination
Write
PCI bus
• Proposed by Intel in 1990 • Work frequency: 66 MHz• Works in 32 or 64-bit configuration• Communication between the processor and the
memory using bridges• Valid signal lines:
– system (np. clock, reset)– Address and data (32)– Interface control– Arbitration (individual!)– Error information
PCI bus read
PCI bus arbitrage
PCI Express bus
• Parallel bus architecture
• Introducing switches
• Backward compatibility with PCI
• Scaleable bandwidth of the bus – from 1x to 32x (depending on the used channels/slots)
• Speed of 250 MB/s for the single slot (for the graphic card 16x PCIe it is 4 GB/s)
PCI Express computer architecture