cmos
TRANSCRIPT
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CMOS
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INTRODUCTIONINTRODUCTION
Integrated circuits: many transistors on single chip.
Metal Oxide Semiconductor (MOS) transistor
Fast, cheap, low-power transistors
Complementary: mixture of n- and p-type leads to less power
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INTRODUCTIONINTRODUCTION
MOSFET
CMOSPMOSNMOS
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SourceDrain
Gate
Metal Oxide Semiconductor Field Effect Transistor
Source ( Phosphorous, Boron)
Drain ( Phosphorous, Boron)
Gate (Aluminum, Polysilicon)
MOSFET
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NMOS
P-type substrate
N-type dopant for Source & Drain
Inversion layer is formed to conduct electricity
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PMOS
N-type substrate
P-type dopant for Source & Drain
Inversion layer is formed to conduct electricity
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CMOS
A combination of both NMOS & PMOS technology
Most basic example: inverter
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WELL FORMATIONWELL FORMATION
ISOLATION FORMATIONISOLATION FORMATION
TRANSISTOR MAKINGTRANSISTOR MAKING
INTERCONNECTIONINTERCONNECTION
PROCESS FLOWPROCESS FLOW
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CMOS FABRICATION PROCESSCMOS FABRICATION PROCESSwell formationwell formation
Start with clean p-type substrate (p-type wafer)
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CMOS FABRICATION PROCESSCMOS FABRICATION PROCESSwell formationwell formation
Grow epitaxy layer (made from SiO2) as mask layer for well formation
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CMOS FABRICATION PROCESSCMOS FABRICATION PROCESSwell formationwell formation
By photolithography and etching process, well opening are made
photolithography and etch processes are shown in next slides
Well will be formed here
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PHOTOLITHOGRAPHY (CED)PHOTOLITHOGRAPHY (CED)
Photoresist coating (C)
Masking and exposure under UV light(E)
Resist dissolved after developed (D)◦Pre-shape the well pattern at
resist layer
P-substrateSi02
photoresist
P-substrate
mask
UV light
Opaque area
Transparent area
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ETCHINGETCHING
Removing the unwanted pattern by wet etching
Resist cleanDesired pattern formed
P-substrate
P-substrate
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CMOS FABRICATION PROCESSCMOS FABRICATION PROCESSwell formationwell formation
Ion bombardment by ion implantationSiO2 as mask, uncovered area will exposed
to dopant ion
Phosphorus ion
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CMOS FABRICATION PROCESSCMOS FABRICATION PROCESSIsolation formationIsolation formation
Increase SiO2 thickness by oxidation at high temperature
Oxide will electrically isolates nmos and pmos devices
Thick oxide
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CMOS FABRICATION PROCESSCMOS FABRICATION PROCESStransistor makingtransistor making
By photolithography and etching process, pmos and nmos areas are defined
pmos will be formed
here
nmos will be formed
here
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CMOS FABRICATION PROCESSCMOS FABRICATION PROCESStransistor makingtransistor making
Grow very thin gate oxide at elevated temperature in very short time
Gate oxide
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CMOS FABRICATION CMOS FABRICATION PROCESSPROCESStransistor makingtransistor making
Deposit polisilicon layer
polisilicon
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CMOS FABRICATION CMOS FABRICATION PROCESSPROCESStransistor makingtransistor making
Photolithography (photo) and etching to form gate pattern
gate
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CMOS FABRICATION CMOS FABRICATION PROCESSPROCESStransistor makingtransistor making
Photo process to define the nmos active (source and drain) area and VDD contact
Ion implantation with Arsenic ion for n+ dopant.
Photoresist and polysilicon gate act as mask
photoresist
Arsenic ion
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CMOS FABRICATION PROCESSCMOS FABRICATION PROCESStransistor makingtransistor making
Nmos’s Source and drain with VDD contact formation
Resist removal
source drainVDD
contact
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CMOS FABRICATION CMOS FABRICATION PROCESSPROCESStransistor makingtransistor making
Photo process to define the GND contact and pmos active area (source and drain)
Ion implantation with boron for p+ dopantPhotoresist and gate act as mask
Boron ion
photoresist
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CMOS FABRICATION CMOS FABRICATION PROCESSPROCESStransistor makingtransistor making
Pmos’s source and drain formation with GND contact
Resist removal
GND contact Pmos’
source
Pmos’s drain
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CMOS FABRICATION CMOS FABRICATION PROCESSPROCESSinterconnectioninterconnection
Deposit CVD Oxide layer through out wafer surface
CVD
Oxide
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Photo and etching process to make contact
CMOS FABRICATION PROCESSInterconnection
contact
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CMOS FABRICATION PROCESSCMOS FABRICATION PROCESSinterconnectioninterconnection
Metal 1 deposition throughout wafer surface
Metal 1
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CMOS FABRICATION CMOS FABRICATION PROCESSPROCESSinterconnectioninterconnection
Photo and etching processes to pattern interconnection
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ADVANTAGESADVANTAGES
High operating speed
Low cost
Very low static power consumption
High degree of noise immunity.
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Optical lithography is limited by the light frequency.
Material limitations
Space limitations
DISADVANTAGESDISADVANTAGES
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APPLICATIONSAPPLICATIONS
Integrated Circuits
Data converters
Integrated transceivers
Image sensors
Logic circuits
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CONCLUSION
CMOS Transistors are stack of gate, oxide, silicon
Build logic gates out of switches
Draw masks to specify layout of transistors