cmos thesis

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NUR ERSHADIAH BINTI ABDUL HADI

12th

DECEMBER 1988

DESIGN AND CHARACTERIZATION OF

BIAXIAL STRAINED SILICON CMOS

2010/2011

PROF. DR. RAZALI ISMAIL 881212-01-6032

20TH

MAY 2011 20TH

MAY 2011

Authors Full Name :

Date of Birth :

Title :

Academic Session :

I declare that this thesis is classified as:

Certified by:

SIGNATURE OF SUPERVISOR SIGNATURE

(NEW IC NO. / PASSPORT NO.) NAME OF SUPERVISOR

NOTES : *

DESIGN AND CHARACTERIZATION OF BIAXIAL

STRAINED SILICON CMOS

NUR ERSHADIAH BINTI ABDUL HADI

A thesis submitted in partial fulfillment of

the requirements for the award of the degree of

Bachelor of Engineering (Electrical-Microelectronics)

Faculty of Electrical Engineering

Universiti Teknologi Malaysia

MAY 2011

i

I hereby declare that I have read this thesis and in my opinion this thesis is

sufficient in terms of scope and quality for the award of the degree of Bachelor of

Engineering (Electrical - Microelectronics).

Signature :

Supervisor : Prof. Dr. Razali Ismail

Date : 20th

MAY 2011

ii

I declare that this thesis entitled Design and Characterization of Biaxial Strained

Silicon CMOS is the result of my own research except as cited in the references.

The thesis has not been accepted for any degree and is not concurrently submitted in

candidature of any other degree.

Signature :

Name of Candidate : NUR ERSHADIAH

Date : 20th

MAY 2011

iii

Specially dedicated to

my beloved mother, father, and sisters

and someone who inspired me all of these years.

iv

ACKNOWLEDGEMENT

Alhamdulillah, the author would like to express her utmost gratitude to the

project supervisor, Prof. Dr. Razali Bin Ismail for his ultimate dedication of supervision,

guidance, and motivation to the author to complete the project. His advices and

motivations have kept the author in the track and achieve the aim of the project.

Appreciation should also be extended to doctoral candidate, Miss Kang Eng

Siew becoming the authors mentor besides her selfless help and guidance throughout

this project. Not to forget, Mr. Yeap Kim Ho from Universiti Tuanku Abdul Rahman for

his guidance and help to the author.

Next, the gratitude should be expressed to the authors beloved parents, family

and sisters. The support and love given by them has inspired the author to finish the

project on the estimated time.

Lastly, to the authors friends, Akmal Hayati Rusli, Nurulsyahida Ishak, Sabariah

Mohamad Ali, Aimie Amalina Azman, Siti Zubaidah Tumari, Norsaradatul Akmar

Zulkifli, Nabilah Yusoff, Nadiah Abdul Razak, Nurul Nadia Ramli, Wan Haszerila Wan

Hassan, Nursyifa Zainal Abidin, Noraliah Aziziah Md.Amin, Hafiz Izzuddin Julaihi,

Muhd. Firdaus Yusof, and lots more, the author would like to thank them for their

support, love and trust besides sharing the knowledge and motivated her all of this

while. Thank you to all, very much.

v

ABSTRACT

The challenging improvement of semiconductor devices from conventional

type is the result of the high demand for smaller and faster electronics devices

nowadays. A lot of effort has been made to overcome the scaling problem, which

seems to obey Moores Law. Since scaling has reached its limit, strained silicon is

the latest alternative to achieve the same result as scaling down, without the need to

alter the size of the electronic devices. The device performance can be improved by

introducing strained Silicon layer on MOSFET. The aim of introducing nano regime

strained silicon MOSFET is to increase the carrier mobility and improving the speed

of the device. However, researchers are also facing certain limitation such as short

channel effects that is unavoidable. The objective of the study is to conduct a

research on biaxial strained silicon Complementary MOSFET (CMOS). The project

will be aided by SILVACOs International Technology Computer Aided Design

(TCAD) tools. The process is divided into two parts, that are design and fabrication

by using SILVACOs ATHENA software, and the last process will be the

characteristics analysis, aided by SILVACOs ATLAS software. The result analysis

of electrical properties such as subthreshold swing, drain induced barrier lowering

(DIBL) are compared to the conventional CMOS. Conclusions with some further

suggestions are presented in this project.

vi

ABSTRAK

Bagi memenuhi permintaan yang tinggi terhadap peranti elektronik yang kecil

dan laju telah menghasilkan era penambahbaikan peranti semikoduktor konvensional.

Semakin banyak usaha telah dijalankan bagi mengatasi masalah pengskalaan, dimana ia

mematuhi Moores Law. Kebelakangan ini, pengskalaan dilihat semakin mencapai tahap

limitasi, maka, silicon tegang merupakan kaedah terkini untuk mencapai hasil yang sama

seperti pengskalaan, tanpa perlu mengubahsuai saiz peranti elektronik. Prestasi peranti

elektronik bolek diperbaiki dengan menambah lapisan silicon tegang didalam MOSFET.

Tujuan menambah lapisan nano silicon tegang didalam MOSFET adalah untuk

menambah pergerakan pembawa dan menambahbaik kelajuan peranti. Walau

bagaimanapun, penyelidik menghadapi beberapa limitasi seperti kesan saluran pendek

yang tidak dapat dielakkan. Objektif projek ini adalah untuk menjalankan kajian

terhadap dwipaksi silicon tegang CMOS. Projek ini dibantu oleh SILVACOs

International Technology Computer Aided Design (TCAD) tools. Proses telah

dibahagikan kepada dua bahagian, iaitu rekabentuk dan simulasi menggunakan perisian

SILVACOs ATHENA, dan proses terakhir adalah analisis cirri-ciri peranti, dibantu oleh

perisian SILVACOs ATLAS. Analisis terhadap hasil dapatan dalam sifat-sifat elektrik

seperti subthreshold swing, drain induced barrier lowering (DIBL) dibandingkan

dengan CMOS konvensional. Kesimpulan beserta cadangan untuk penambahbaikan turut

disertakan didalam projek ini.

vii

TABLE OF CONTENT

CHAPTER TITLE

PAGE

DECLARATION

DEDICATION

ACKNOWLEDGEMENT

ABSTRACT

ABSTRAK

TABLE OF CONTENT

LIST OF TABLES

LIST OF FIGURES

LIST OF ABBREVIATIONS

LIST OF SYMBOLS

LIST OF APPENDICES

i

iii

iv

v

vi

vii

xii

xiii

xvii

xix

xx

1 INTRODUCTION

1.1 Background of Study

1.2 Problem Statement

1.3 Objectives

1.4 Scope

1.5 Summary of Previous work

1

3

4

4

5

viii

2 THEORY AND LITERATURE REVIEW

2.1 Overview of MOSFET

2.1.1 NMOSFET

2.1.1.1 NMOS Structure

2.1.1.2 NMOS Operation

2.1.2 PMOSFET

2.1.2.1 PMOS Structure

2.1.2.2 PMOS Operation

2.1.3 CMOS

2.2 Short Channel Effect

2.2.1 Drain Induced Barrier Lowering (DIBL) &

Punchthrough

2.2.2 Surface Scattering

2.2.3 Velocity Saturation

2.2.4 Impact Ionization

2.2.5 Hot Electrons

2.3 Strained Silicon

2.3.1 Theory and Concept

2.3.2 Strained Silicon MOSFET

2.3.3 Types of Strained Silicon MOSFET

2.3.3.1 Uniaxial Strained Silicon MOSFET

2.3.3.1 Biaxial Strained Silicon MOSFET

2.4 Advantages of Strained Silicon MOSFET

7

8

8

9

12

12

13

13

15

16

17

18

19

20

20

21

22

23

23

23

24

ix

2.4.1 Carrier Mobility Enhancement

2.4.2 Lower the Resistance and Power Consumption

2.4.3 New Gate Stack Material Needs Delay

25

25

25

3 METHODOLOGY AND APPROACH

3.1 Methodology

3.2 Flowchart

3.3 TCAD Tools

3.3.1 Simulation Tools

3.3.1.1 TCAD Software

3.3.1.1.1 DECKBUILD: Interactive Deck

Development and Runtime Environment

3.3.1.1.2 TONYPLOT: 1D/2D Interactive

Visualization Tools

3.3.1.1.3 MASKVIEWS

26

26

28

30

30

31

31

32

33

4 DESIGN OF CONVENTIONAL AND STRAINED

SILICON MOSFETS

4.1 Design of MOSFET

4.1.1 ATHENA Design of Biaxial Strained Silicon MOSFETs

4.1.1.1 Mesh Definition and Substrate Initialization

4.1.1.2 Epitaxial Layer

4.1.1.3 Deposition of Silicon and SiGe Layers

4.1.1.4 Formation of Gate Oxide

4.1.1.5 Threshold Voltage Adjustment

35

36

39

40

41

42

44

x

4.1.1.6 Deposition and Patterning of Polysilicon

4.1.1.7 Polysilicon Oxidation and Doping

4.1.1.8 Spacer Oxide

4.1.1.9 Source and Drain Annealing

4.1.1.10 Metallization and Contact Patterning

4.1.1.11 Structure Reflection and Electrode Labeling

4.1.1.12 TONYPLOT Concentration View and Measurement

4.1.2 MASKVIEWS Design of Conventional and Biaxial Strained Silicon Complementary MOSFET

44

46

48

48

50

50

52

54

5 CHARACTERIZATION OF BIAXIAL STRAINED

SILICON MOSFETS

5.1 ATLAS Device Simulation Framework

5.2 Device Characterization using ATLAS Simulator

5.3 Drain Current versus Gate Voltage (ID vs.VGS)

5.4 Drain Current versus Drain Voltage (ID vs. VDS)

5.5 Drain Induced Barrier Lowering

5.6 Subthreshold Swing

5.7 Result Comparison

62

62

64

65

68

70

72

76

6 CONCLUSION

6.1 Project Summary

6.2 Suggestion for Future Work

6.2.1 Reducing Channel Length

6.2.2 Capacitance-Voltage Characteristics

77

77

79

79

79

xi

6.2.3 Strained Silicon in Silicon-On-Insulator (SOI)

6.2.4 MOSFET with Side Gates

6.2.5 Twin Well with Field Oxide Technology (FOX)

80

80

81

REFERENCES

APPENDICES

83

86

xii

LIST OF TABLES

TABLE NO. TITLE

PAGE

1.1

2.1

4.1

5.1

5.2

5.3

5.4

6.1

Summary of previous researches

Type of Stress Needed for NMOS and PMOS

Specification of simulated devices

Comparison of DIBL with different channel length

Comparison of Subthreshold swing with various channel

length

Comparison between conventional and biaxial strained

silicon MOSFETs

Comparison between different channel lengths of

strained silicon MOSFETs

Summary of device characteristics

6

22

54

72

75

76

76

78

xiii

LIST OF FIGURES

FIGURE NO. TITLE PAGE

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

2.14

2.15

2.16

Basic MOSFET structure

NMOS structure

Induced NMOS

Cutoff region of NMOS operation

Linear/Triode region of NMOS operation

Saturation region of NMOS operation

PMOS structure

CMOS structure

Channels formation in CMOS

a) NMOS part b) PMOS part

Several ways to reduce punchthrough effects (a) delta

doping (b) halo (c) pocket implants

Inversion layer, depletion region and the surface

scattering effect

Hot electron effects

(Left) Pure Silicon and Silicon Germanium (Right)

Strained Silicon after being matched with Silicon

Germanium

The direction of strain

Uniaxial Strained Silicon MOSFET

7

9

10

11

11

11

12

13

14

15

17

18

20

21

21

23

xiv

2.17

3.1

3.2

3.3

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

4.11

4.12

4.13

4.14

4.15

4.16

4.17

4.18

Biaxial Strained Silicon MOSFET

Flowchart of the project

Segmentation of project

SILVACO TOOLS used in this project

The flow of designing a conventional MOSFET

The flow of designing biaxial strained Silicon MOSFET

The view of DECKBUILD

Codes for generating mesh

Codes for generating substrate material

Codes for depositing epitaxial layer

View of Epitaxial Layer and Substrate with Grid

Definition

Codes for depositing Silicon and SiGe layer

Silicon and SiGe layer

Codes for diffusing gate oxide

The formation of Oxide layer for Gate Oxide

Codes for extracting the thickness of gate oxide

Codes for implanting the doping for threshold

adjustment

Codes for depositing Polysilicon

Layer of Polysilicon

Codes for patterning Polysilicon

Etched Polysilicon

Codes for Polysilicon oxidation

24

28

29

29

37

37

38

39

40

41

41

42

42

43

43

43

44

45

45

45

46

46

xv

4.19

4.20

4.21

4.22

4.23

4.24

4.25

4.26

4.27

4.28

4.29

4.30

4.31

4.32

4.33

4.34

4.35

4.36

4.37

4.38

5.1

5.2

5.3

Oxidized Polysilicon

Codes for Polysilicon doping

Codes for depositing spacer oxide

Codes for implanting and annealing source and drain

The view of source and drain region/junction

Codes for depositing and patterning Aluminium

Codes for reflecting structure

Reflected structure

Codes for labeling structure and creating output file

Codes for viewing the structure

Concentration view and channel length measurement

The first trial of creating a bulk CMOS

Flowchart of creating a conventional CMOS

Steps of processes of fabricating conventional CMOS

MASKVIEWS Base Window

A 0.35 um conventional CMOS GDS layout

Top view and side view of 0.35um CMOS using

MASKVIEWS

Structure obtained from GDSII layout

Concentration view of 0.35um CMOS

Flowchart of creating biaxial strained silicon CMOS

ATLAS inputs and outputs

Order of Statement in ATLAS Simulation

ID-VGS of NMOS and strained Silicon NMOS at VDS =

0.1V

47

47

48

49

49

50

51

51

52

53

53

55

56

57

58

58

59

59

60

61

63

64

66

xvi

5.4

5.5

5.6

5.7

5.8

5.9

5.10

5.11

5.12

6.1

6.2

6.3

ID-VGS of PMOS and strained Silicon PMOS at VDS =

0.1V

ID-VDS Graph of NMOS

ID-VDS Graph of PMOS

Determining DIBL from graph (a) NMOS (b) PMOS

DIBL effect of conventional MOSFETs

Comparison of DIBL effect between conventional and

strained Silicon MOSFETs

Log ID vs. VGS at VDS = 0.1V

Comparison of subthreshold swing between

conventional and biaxial strained Silicon MOSFETs

Comparison of subthreshold swing with various channel

length

Strained Silicon implemented on Silicon-on-Insulator

(SSOI)

Formation of MOSFET with Side Gates

MOSFET with twin well and FOX technology

67

68

69

70

71

71

73

74

75

80

81

82

xvii

LIST OF ABBREVIATIONS

MOSFET

CMOS

RAM

TCAD

DIBL

UTM

NMOS

PMOS

SiGe

DOS

GaAs

FYP

PBL

sSi

EDA

IC

GUI

SOI

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Metal Oxide Semiconductor Field Effect Transistor

Complementary Metal Oxide Semiconductor Field Effect Transistor

Random Access Memory

Technology Computer Aided Design

Drain Induced Barrier Lowering

Universiti Teknologi Malaysia

N-channel Metal Oxide Semiconductor Field Effect Transistor

P-channel Metal Oxide Semiconductor Field Effect Transistor

Silicon Germanium

Density of States

Gallium Arsenide

Final Year Project

Problem-Based Learning

Strained Silicon

Electronic Design Automation

Integrated Circuit

Graphical User Interface

Silicon On Insulator

xviii

VLSI

STI

DC

AC

HEMT

LED

LASER

CCD

NVM

-

-

-

-

-

-

-

-

-

Very Large Scale Integrated Circuit

Shallow Trench Isolation

Direct Current

Alternating Current

High Electron Mobility Transistor

Light Emitting Diode

Light Amplification by Stimulated Emission of Radiation

Charge Coupled Device

Non-volatile Memory

xix

LIST OF SYMBOLS

ID

VDS

VGS

VT

VSB

VDB

Leff

S

W

L

-

-

-

-

-

-

-

-

-

-

-

Drain current

Drain-to-source voltage

Gate-to-source voltage

Threshold Voltage

Effective carrier mobility / microns

Source-to-body voltage

Drain-to-body voltage

Effective channel length

Subthreshold Swing

Width

Length

xx

LIST OF APPENDICES

APPENDIX

TITLE PAGE

A

B

C

D

E

F

G

H

I

J

K

L

ATHENA INPUT FILE: 45nm BIAXIAL STAINED

SILICON NMOS

ATLAS INPUT FILE: DIBL CHARACTERISTICS

OF BIAXIAL STRAINED SILICON NMOS

ATLAS INPUT FILE: Id-Vgs CHARACTERISTICS


ATLAS INPUT FILE: Id-Vds CHARACTERISTICS


ATHENA INPUT FILE: 45nm CONVENTIONAL

NMOS


OF CONVENTIONAL NMOS





ATHENA INPUT FILE: 45nm BIAXIAL STRAINED

SILICON PMOS


OF BIAXIAL STRAINED SILICON PMOS





85

87

89

92

94

96

98

101

103

105

107

110

xxi

M

N

O

P

ATHENA INPUT FILE: 45nm CONVENTIONAL

PMOS


OF CONVENTIONAL PMOS





112

114

116

119

1

CHAPTER 1

INTRODUCTION

1.1 Background of Study

Widely used as electronics signals amplifier and switches, Metal Oxide

Semiconductor Field Effect Transistor MOSFET is a voltage controlled device. Its

physical includes the presence of n-type and p-type material, which is known as NMOS

if the source and drain are made of n-material and PMOS if the source and drain are

made of p-material. In advanced integrated circuit (IC) design, MOSFET is one of the

most common transistors used in both analog and mixed-signal circuits. MOSFET has

the advantages which the switching time is about 10times faster than a bipolar transistor.

MOSFET has a very much smaller switching current; it is less affected by temperature

when compared to bipolar transistor1.

MOSFET family is divided into three most common types, NMOS, PMOS and

CMOS, which consists of both NMOS and PMOS. CMOS the abbreviation of

Complementary Metal Oxide Semiconductor Field Effect Transistor technology is

widely used in microcontrollers, microprocessors, static RAM, and also in other digital

2

logic circuits. For its variety usage, it is also been used in analog circuits, such as data

converters, image sensors, and highly integrated transceivers in the communication field.

The most important characteristics of CMOS are its high noise immunity and low static

power consumption.

Silicon is one of natures compounds that have been used widely in the

semiconductor technology for years. It is a tetravalent metalloid or semimetal chemical

element that is less reactive than its chemical analog carbon. Silicon comes in atomic

number of 14. The most natural-famous form of silicon found in nature in dusts and

sands is silicon dioxide or silicates. Because of its native oxide that is easily grown in a

furnace and it forms a better dielectric and semiconductor interface compared to the

other material, silicon remains as the most popular material used in semiconductor

technology. Strained silicon MOSFET has been known for increasing the speed,

mobility and reducing power consumption of conventional MOSFET2.

Strained silicon is formed by matching a pure layer of silicon over a substrate of

silicon germanium, SiGe. The silicon atoms inside the pure silicon will be stretched out

and aligned according to the atomic structure of the silicon germanium. The atoms will

be arranged to be far apart, thus will reduce the atomic forces. The atomic forces

influence the movements of electrons through the silicon, thus, when strained silicon is

used in a transistor, the transistors performance will be increased. The electrons can

move almost 70% faster in the strained silicon compared to the pure one, which allowing

the transistor to operate 35% faster than usual. The mobility enhancement obtained by

applying appropriate strain provides higher carrier velocity in MOS channels. Under a

fixed supply voltage and gate oxide thickness, this will result in a higher drive current3.

A general term for Si1-xGex is SiGe, which is widely used in the semiconductor

technology to be matched with silicon and produced strained silicon. Since the

3

fundamental scaling has its own limitation caused by the short channel effect, SiGe

extends the chance of improving the performance of MOSFETs. The 4.2% lattice

mismatch between Si and SiGe layer is used to create strained layer to enhance the

carrier transport in the MOSFETs channel4. Theoretical calculations5-9 predict electrons

and holes mobility enhancements in strained Si MOSFETs.

In this project, biaxial strained silicon CMOS has been chosen to be studied to obtain

the characteristics of biaxial strained silicon CMOS and to compare it with the

performance of the conventional CMOS. Recent studies in semiconductor technology

specialized in strained silicon has proven that the performance of strained silicon CMOS

is much better than the conventional CMOS.

1.2 Problem of Statement

The advancement of semiconductor technology demands for faster and smaller

electronic devices. The scaling of MOSFET has approaching nanoscale, and limitations

arose as short channel effect becomes the main obstacle in producing smaller devices.

Thus, strained silicon has been introduced to improve the performance of CMOS,

without altering or reducing the length of the channel.

It is very costly to fabricate the device and to perform experimental analysis.

After the first fabrication, it takes some time to obtain the characteristics, and when the

desired result could not be obtained, another fabrication of the device will be needed.

Instead of a real life fabrication, virtual fabrication is the alternative way to reduce the

cost and to obtain the accurate result of electrical properties. TCAD tools are one of the

alternatives as the software can be used to fabricate and to analyze the electrical

properties of the virtual design.

4

1.3 Objectives

1. To conduct a study on biaxial strained silicon CMOS.

2. To design and simulate biaxial strained silicon CMOS by using SILVACOs

ATHENA software.

3. To conduct an investigation on the electrical characteristics of biaxial

strained silicon CMOS by using SILVACOs ATLAS software.

4. To compare the characteristics between the conventional and strained silicon

CMOS.

1.4 Scope

Biaxial strained silicon CMOS is modified from the conventional CMOS and the

characteristics of the device is studied. The design and the fabrication process of biaxial

strained silicon CMOS is done by using SILVACOs ATHENA software. The

SILVACOs ATLAS software is used to simulate and to obtain the devices

characteristics. Lastly, analysis is done to the result to investigate the electrical

properties of the biaxial strained silicon CMOS, and compared it to the conventional

one, and the project is concluded.

Some electrical characteristics that are studied in the project including the

threshold voltage, subthreshold swing, and drain induced barrier lowering (DIBL). For

every step in simulation process, caution has been taken to ensure the accurate CMOS

that has been designed is simulated.

5

1.5 Summary of Previous Work

Previous research held by UTM students and researchers focused on PMOS and

NMOS. In the year of 2007, some researches were done on uniaxial strained silicon

PMOS 10-11

. In 2010, Biaxial strained silicon NMOS has been designed virtually, using

TCAD tool (Silvaco International) 12

. In fact, a few research has been conducted to

explore the enhancement of performance of MOSFET devices worldwide, thus

conducting a study on biaxial strained silicon CMOS is relevant for undergraduates

project.

The study focused on 45nm biaxial strained silicon MOSFET, since the technology

now has reach 32nm nano regime. Former research proved that the study is still valid

and can be done extensively. The results of the researches are summarized in Table 1.1

to compare with the result in this project.

6

Table 1.1: Summary of previous researches

Characteristics Strained silicon PMOS

(uniaxial)

Strained silicon NMOS

(biaxial)

Threshold Voltage

(Vd=0.1V)

-0. 596894V (100nm)10

-0.511299V (71nm) 11

0.571733(90nm)12

0.581068(150nm)12

Subthreshold Swing

(mV/dec)

186.153 10

112.8 12

DIBL (mV/V)

693.564 10

/ 303.411

354 12

Mobility enhancement

at Vgs=3V (%)

25.65% 10

-Hole mobility enhancement

35.7% 12

-Electron mobility

enhancement

7

CHAPTER 2

THEORY AND LITERATURE REVIEW

2.1 Overview of MOSFET

Metal Oxide Semiconductor Field Effect Transistor is commonly known as

MOSFET, is capable of voltage gain and signal-power gain. MOSFET is used

extensively in digital circuit applications. Since it is relatively small in its sizes,

thousands of devices can be fabricated in a single integrated circuit. All MOSFET are

actually transistors, which consist of metal, Silicon Oxide, silicon, n+ material or p

+

material. The heart of the MOSFET is a metal-oxide-semiconductor structure known as

a MOS capacitor1.

Figure 2.1: Basic MOSFET structure

8

MOSFET is divided into three main types, PMOS, NMOS and CMOS. MOSFET

operates when a voltage is applied across it. Let us review an example of a p-type

semiconductor. When a positive voltage is supplied at the gate, it creates a depletion

layer by forcing the positive charged majority carrier (in this case hole for p-type)

away from the gate insulator interface, and leave an exposed carrier-free region of

negative charged acceptor. When the voltage supplied at the gate is high enough, high

concentration of negative charge carrier will form an inversion layer a very thin layer

next to the interface between the insulator and semiconductor.

2.1.1 NMOSFET

NMOSFET N-channel Metal Oxide Semiconductor Field Effect Transistor or

simply NMOS is a type of MOSFET that will have an inversion layer of n type material,

or simply said n-channel. It is one of MOSFET family member that is used extensively

as switches and in digital logic design.

2.1.1.1 NMOS Structure

NMOS is built with p-type material as the substrate. The plus (+) notation on n+

indicates the n-type material/region are heavily doped material. An insulator which is

made of a thin layer of silicon oxide (SiO2) is grown on the substrates surface, and

covering the area between the source and drain. Metal is deposited at four different

terminals, which are labeled as Source (S), Gate (G), Drain (D), and Body (B).

9

Figure 2.2: NMOS structure

2.1.1.2 NMOS Operation

When a positive voltage is applied at the gate terminal, it causes the free holes

(positive charges) to be repelled from the region of the substrate, under the gate. Then,

these holes are push downwards into the substrate, creating a carrier depletion region.

The depletion region is made from the negative charges, due to the neutralizing holes

that have been pushed down. The gate voltage, which is positive, will attract electrons

from the n-wells, forming an n channel that connects the source and the drain. Thus,

current will flow through the induced region. The current flow from drain to source,

since the current, iD is carried by free electrons from source to drain. The current

magnitude depends on the electrons density in the channel, which depends on VGS >

VT.

If VGS > VT, the channel will increases, and the resistance across the channel is

reduced or the conductance is increased. The conductance of the channel is proportional

to the excess gate voltage, which is known as effective voltage.

10

Figure 2.3: Induced NMOS

For summary, NMOS operates at:

I. Cutoff region When VGS < VT, there is no inversion layer present under

the surface. At VDS = 0, the source and drain depletion regions are

symmetrical. A positive VDS reverse biases the drain substrate junction,

hence the depletion region around the drain widens, and since the drain is

adjacent to the gate edge, the depletion region widens in the channel.

However, there is no current flows even for VDS > 0, since no conductive

channel is present and ID = 017

.

II. Linear/Triode region when VDS < VGS VT

III. Saturation region when VDS > VGS VT

11

Figure 2.4: Cutoff region of NMOS operation

Figure 2.5: Linear/Triode region of NMOS operation

Figure 2.6: Saturation region of NMOS operation

12

2.1.2 PMOSFET

PMOSFET P-channel Metal Oxide Semiconductor Field Effect Transistor or

simply PMOS is a type of MOSFET that will have an inversion layer of p type material,

or simply said p-channel. It is one of MOSFET family member that is used extensively

as switches and in digital logic design.

2.1.2.1 PMOS Structure

PMOS is built with n-type material as the substrate. The plus (+) notation on p+

indicates the p-type material/region are heavily doped material. An insulator which is

made of a thin layer of silicon oxide (SiO2) is grown on the substrates surface, and

covering the area between the source and drain. Metal is deposited at four different

terminals, which are labeled as Source (S), Gate (G), Drain (D), and Body (B).

Figure 2.7: PMOS structure

13

2.1.2.2 PMOS Operation

A PMOS operates in a similar way as the NMOS, except that VGS, VDS and the

threshold voltage VT are negative values. The current flow through the channel, iD enters

the source terminal, and leaves through the drain (opposite to the NMOS)

For summary, the PMOS device operates at:

I. Cutoff region the device is turned off when VGS > VT, and turned on

VGS < VT.

II. Linear/Triode region when VDS < VGS + VT

III. Saturation region when VDS VGS + VT

2.1.3 CMOS

CMOSFET Complementary Metal Oxide Semiconductor Field Effect

Transistor or simply CMOS is a device that consists of both PMOS and NMOS in its

structure.

Figure 2.8: CMOS structure

14

The PMOS part has been designed so that the PMOS can only receive an input,

either from the source (voltage source) or from the other PMOS transistor. The NMOS

part works similarly. It can only receive an input either from the ground, or from the

other NMOS transistor.

In the PMOS part, the composition of its structure has created a low resistance

every time a low voltage is applied through it, and similarly, when a high voltage is

applied, it creates a high resistance in it. Contrary, in the NMOS part, when a low

voltage is applied, it creates a high resistance and when a high voltage is applied on it, it

creates a low resistance.

Figure 2.9: Channels formation in CMOS

There are two cases of the operation of CMOS device, when a low voltage is

applied, and when a high voltage is applied. Both cases have a similar flow of operation.

15

Figure 2.10: a) NMOS part b) PMOS part

a) When low voltage is inserted: At NMOS part, if the input is a low voltage

supply, the NMOS creates a high resistance, and it prevents the voltage from

leaking into the ground. At the PMOS part, if the input is low voltage, it allows

the input to go through the PMOS transistor straight to the output. The output

will be a high voltage.

b) When high voltage is inserted: When a high voltage is inserted, PMOS transistor

will produce a high resistance and it will automatically block the voltage source

from the output. At the NMOS part, it will be a low resistance, and allows the

output to move from the drain to the ground. The output will eventually register

as a low voltage.

2.2 Short Channel Effect

If the channel length of a MOSFET is the same order of magnitude as the depletion-

layer widths (xdD, xdS) of the source and drain junction, the MOSFET is considered as

short MOSFET. To improve the operational speed of a device and to increase the

number of components per chip, the channel length should be altered. Unfortunately, the

short channel effect will arise when the channel length, Leff is reduced. Two phenomena

are attributed by the short channel effects, which are the limitation imposed on electron

16

drift characteristic in the channel, and the modification of the threshold voltage due to

the shortening channel length3. Basically, there are five significant short channel effects

that can be observed, which are the drain induced barrier lowering (DIBL) and

Punchthrough, surface scattering, velocity saturation, impact ionization and hot

electrons.

2.2.1 Drain induced barrier lowering (DIBL) & Punchthrough

Or

Based on the equations, when the depletion regions surrounding the drain

extends to the source, until the two depletion layer can merge (xdS + xdD = L),

punchthrough will eventually occurs. Thinner gate oxides, larger substrate doping,

shallower junctions, and obviously with longer channels can minimized the effects of

punchthrough3. Creating and sustaining the inversion layer on the surface of a MOSFET

will influence the current flows in the channel. When the gate bias voltage is not

sufficient to invert the surface (i.e. VGS

17

and drain when the potential barrier is reduced, even if the VGS is lower than VTO

(threshold voltage). The current that flows under the condition of VGS

18

interface. This will results the average surface mobility to become about half as much as

that of the bulk mobility, even for small values of x. Surface scattering is the collisions

suffered by the electrons that are accelerated toward the interface by x3.

Figure 2.12: Inversion layer, depletion region and the surface scattering effect

2.2.3 Velocity Saturation

Short channel devices performance is also affected by velocity saturation.

Velocity saturation reduces the transconductance of the device, when it operates in the

saturation mode. At a very low longitudinal electric field, x, the electrons drift velocity

varies linearly with the electric field intensity. As the longitudinal electric field increase

and exceeds above 104

V/cm, the drift velocity will increase slowly and approaches a

value of saturation of vDE (sat) = 107 cm/s around x of 10

5 V/cm, at the temperature of

300K. Instead of the pinch off, the drain current is actually limited by velocity

saturation. It occurs when the dimensions of the short channel device is scaled, without

19

lowering the voltage bias. The maximum gain that is possible for a MOSFET, by using

VDE (sat), can be defined as

2.2.4 Impact Ionization

With the presence of high longitudinal fields that generate electron-hole pairs,

impact ionization occurs when the high velocity of electrons exist. By impacting on

silicon atoms and ionizing the atoms, impact ionization occurs, especially in NMOS.

Most of the electrons are attracted by the drain, while the holes will enter the substrate to

form an art of the parasitic substrate current3.

The source region plays the role of the emitter, the drain region plays the role as

the collector, and the region between the source and the drain plays the role as the base

of an npn. When the source is collecting the holes, the corresponding hole current will

create a voltage drop, right in the substrate material. The normal reverse biased

substrate-source pn junction of 6V will conduct appreciably. Only then electrons can be

injected from the source to the substrate3, most likely to be similar as electrons that have

been injected from the emitter to the base. As the electrons travel towards the drain, it

gained enough energy to create new electron-hole pairs. If some electrons generated due

to high fields escape from the drain field to travel into the substrate, it will affect the

other devices on the chip and worsen the situation.

.................. (3)

20

2.2.5 Hot Electrons

Hot electrons refer to high energy electrons, which enter the oxide layer and trapped,

that will affecting the oxide, to rise to oxide charging. It accumulates with time, and

degraded the performance of the device by increasing the threshold voltage, VT, affects

its conveyed conductance, and affects adversely the gates control on the drain current 3.

Figure 2.13: Hot electron effects

2.3 Strained Silicon

Strained silicon is widely used nowadays in semiconductor manufacturing

technology to design Integrated Circuits (IC). It has captured the researchers attention

and vendors heart since it can be found easily anywhere in natural substance.

21

2.3.1 Theory and Concept

Strained silicon is a semiconductor technology that involving the process of

stretching ad compressing physically, the silicon crystal lattice via various means.

Figure 2.14: (Left) Pure silicon and Silicon Germanium (Right) Strained silicon after

being matched with Silicon Germanium

Figure 2.15: The direction of strain

The technique involves the deposition of pure silicon (Si) on the top of a Silicon

Germanium layer (SiGe) with SiGe ratio as Si1-xGex. The atoms in pure silicon will

22

eventually stretched /strained to match the SiGe atoms as SiGe atoms molecular

structure is much wider. The strained silicon obtained after the process have less

resistance compared to the pure one, which leads to the improvement in the device

performance. It will increases the carrier mobility and improves the electrical

performance of the device without the need of altering them to make it smaller.

2.3.2 Strained Silicon MOSFET

Strained Si (SS) MOSFETs are device structures that take advantage of strain-

induced enhancement of carrier transport in silicon. When a thin layer of Si is

pseudomorphically grown on a thick, relaxed SiGe layer, the lattice constant of the Si

film conforms to that of the SiGe layer, and the lattice mismatch between Si and SiGe

leads to biaxial tensile strained in the Si layer. If the SiGe layer is fully relaxed and the

Si layer fully strained, the amount of strain in Si is approximately 4.2 x x% where x is

the Ge mole fraction in the SiGe layer13

. The type of stress needed for MOSFET is

sectioned in Table 2.1.

Table 2.1: Type of Stress Needed for NMOS and PMOS

Direction NMOS PMOS

Longitudinal (along length of channel) Tension Compression

Transverse (along width of channel) Tension Tension

Out of Plane Compression Tension

23

2.3.3 Types of Strained Silicon MOSFET

2.3.3.1 Uniaxial Strained Silicon MOSFET (Substrate Strain)

All 90, 65, and 45nm high performance logic technologies adopted uniaxial

process induced strained silicon. Uniaxial stress could provide a low channel direction in

plane conductivity mass, large out-of-plane in confinement mass, and high in-plane

density of states (DOS) to the ground hole subband14

. A tensile capping layer is formed

right on top of the Strained SiGe gate. At the area between source and drain, strained

silicon is introduced.

Figure 2.16: Uniaxial Strained Silicon MOSFET

2.3.3.2 Biaxial Strained Silicon MOSFET (Process-Induced Strain)

Biaxial strain in the lattice structure of a crystalline Silicon is induced when an

epitaxial of a thin Silicon film is grown on top of a relaxed Silicon Germanium (SiGe)

24

substrate15

. Strained silicon is introduced at the region between the source and the drain

region, and a relaxed SiGe layer is placed at the top of the bulk, right under the strained

silicon layer. The bottom part of the device will be the silicon substrate layer.

Figure 2.17: Biaxial Strained Silicon MOSFET

2.4 Advantages of Strained Silicon MOSFET

Several advantages have been found by introducing strained silicon in MOSFET It

includes carrier mobility enhancement, lowers the resistance and power consumption,

and the most important thing is that it will delays the new gate stack material needs. The

advantages of strained silicon is indeed should not be taken lightly, since it is the new

hope of improving MOSFETs for better performance.

25

2.4.1 Carrier Mobility Enhancement

The variation of interatomic distance in silicon layer, either tensile or

compressive, would eventually increase the mobility of the devices. By increasing

mobility, the current and the speed required can be maintained. The carriers can move

almost 70% faster in strained silicon, compared to a pure one, which will result a 35%

faster devices.

2.4.2 Lower the resistance and power consumption

Since the interatomic atoms in the strained silicon have been stretched, it allows

electrons to move faster, which means that it creates a lower resistance region.

Fortunately, the power consumption in the device will be reduced as the resistance is

lowered.

2.4.3 New gate stack material needs delay

Strain silicon improves the MOSFET performances without further scaling of

gate dielectric thickness, junction depth or other dimensions of transistor. The silicon

Germanium (SiGe) material could integrate well with silicon. As strained Silicon

products are much more cheaper, it gives a competitive edge over Gallium Arsenide

(GaAs)16

.

26

CHAPTER 3

METHODOLOGY AND APPROACH

3.1 Methodology

Several stages in the project were done to complete the project in the estimated

time. Stages were carefully planned to fit the schedule and also the submission of the

project, part by part.

Stage 1: The title, problem, objectives and scope is determined

Problem is determined, and relevant title with objectives and scopes to focus is

chosen.

Outcomes are determined.

Stage 2: Literature studies are conducted

Conduct literature studies on CMOS, strained silicon, biaxial and uniaxial strained

silicon.

Materials such as eBooks, journals and websites are compiled.

27

Stage 3: FYP 1 Seminar

The projects proposal is presented in front of the panels.

Suggestions were taken into a serious consideration, to improve the project.

Stage 4: TCAD Tools Learning

PBL Lab of SEW 4722 is reviewed to get familiar with the ATLAS and

ATHENA software.

User manual of ATHENA, ATLAS and MASKVIEWS are used extensively to help

the fabrication and characterization process.

Stage 5: Fabrication and Characteristics Simulation

ATHENA is used to design and fabricate the device virtually.

ATLAS is used to investigate the characterization of the device.

MASKVIEWS is used to design the layout and extract information to ATHENA.

Stage 6: Result Analysis

Results is analyzed to conclude the electrical properties of biaxial strained silicon

CMOS.

Results are concluded.

Stage 7: FYP 2 Seminar

Results are presented in front of the panels to be evaluated.

Stage 8: Thesis Writing

Final thesis is written with binding hard cover and submitted to the faculty.

28

3.2 Flowchart

Figure 3.1: Flowchart of the project

1

Propose a topic, objective/s, and outcomes.

2

Conduct a literature research.

Collect relevant data.

3

Learn TCAD tools - ATHENA

Learn TCAD tools - ATLAS

Learn TCAD tools - MaskViews

4

Design conventional PMOS and NMOS using ATHENA

Analyse the characteristics using ATLAS

5

Design biaxial strained silicon PMOS and NMOS using

ATHENA

Analyse the characteristics using ATLAS

6

Compare the characteristics of conventional MOSFET and

the biaxial strained silicon MOSFET.

Conclude the comparison.

7

Design a bulk CMOS using MaskViews

Extract to ATHENA

29

Figure 3.2: Segmentation of project

Figure 3.3: SILVACO TOOLS used in this project

Biaxial sSi

CMOS

Conventional &

sSi PMOS

Analyze

Characteristics

Conventional &

sSi NMOS

Analyze

Characteristics

CMOS (Layout)

CMOS

Structure

PRODUCT

SILVACO

ATHENA

SILVACO

ATLAS

SILVACO

MASKVIEWS

30

3.3 TCAD Tools

The software used in the project is originally from SILVACOs International. It is

divided into three parts, which are the ATHENA software, used for fabrication and

simulation of the device, and ATLAS software, used for investigation of the

characterization of the device, and MASKVIEWS to design a complicated MOSFET by

drawing the layout. TCAD tools are chosen to aid the project since the cost to fabricate

the real design is very expensive. Thus, virtual fabrication is needed, especially when the

design does not meet the right specification and you have to do it all over again. If a real

fabrication is done, the cost to fabricate two to three times would be so much expensive.

Thus, virtual fabrication is the most suitable method to investigate the characterization of

the device, without any costs. Any improvement in the design can be made without hassle

with the aid from the software.

3.3.1 Simulation Tools

Nowadays, simulation tools are very popular in the design section to aid the

designers to obtain the optimized desirable result. In electrical engineering field itself,

stages from digital design to circuit level design, are using simulation tools in every

aspect to obtain the accurate characteristics and results. In this project, ATHENA and

ATLAS have been chosen to aid the author throughout the project.

31

3.3.1.1 TCAD Software

SILVACO International is owned privately and provides a comprehensive set of

electronic design automation (EDA) software, which allows companies to design both

analog and mixed-signal integrated circuit (IC). SILVACO delivers products like TCAD

tools for process and device simulation. It provides analog semiconductor process, device

and design automation solution in CMOS, bipolar transistors, SiGe and any other

compound technologies. The main process and the device simulation project are using the

SILVACOs ATHENA and ATLAS software, for device simulation and characterization

respectively.

3.3.1.1.1 DECKBUILD: Interactive Deck Development and Runtime Environment

DECKBUILD is an interactive runtime and input file development environment

within which all Silvacos TCAD and several other SIMUCAD products can run.

DECKBUILD has numerous simulator specific and general debugger style tools. This

includes powerful extract statements, GUI based process file input, line by line runtime

execution and intuitive input file syntactical error messages. DECKBUILD contains an

extensive library of hundreds of pre-run examples decks which cover many technologies

and materials, and also allow the user to rapidly become highly productive18

.

Key features of DECKBUILD are:

Provide an interactive runtime and input file development environment for

running several core simulators

Input deck creation and editing

32

View simulator output and controls

Set popups that provide full language and run-time support for each simulator

Automatic interface among simulators

Many input file creation and debug assist features, such as run, kill, pause, stop at,

and re-start

Extracted quantities can be used as targets in DECKBUILDs internal optimizer, allowing

automatic cyclical optimization of any parameter19

.

3.3.1.1.2 TONYPLOT: 1D/2D Interactive Visualization Tools

TONYPLOT is a powerful tool designed to visualize TCAD 1D and 2D structures

produced by SILVACO TCAD simulators. TONYPLOT provides visualization and

graphic features such as pan, zoom, views, labels and multiple plot support. TONYPLOT

also provides many TCAD specific visualization functions, 1D cut lines from 2D

structures, animation of markers to show vector flow, integration of log or 1D data files

and fully customizable TCAD specific colors and styles.

Some of the key features of TONYPLOT are:

Flexible graphical analysis tool specifically developed for TCAD visualization

assists in rapid prototyping and developing of process and device designs

Common visualization tool across all SILVACO TCAD products

Plotting engine supports all common 1D and 2D data views including: 1D x-y

data, 2D contour data, 2D meshed data, smith charts and polar charts

Exports data in many common formats for use in reports or by third party tools.

Supported formats include; jpg, png, bmp, Spice Raw File and CSV

33

Flexible Labels allow plots to be annotated to create meaningful figures for

reports and presentations

Integrated suite of probes, rulers, and other measurement tools allows detailed

analysis of 1D and 2D structures

Overlays allow multiple plots to be easily compared

Overlaying 1D log files enables visualization of how process conditions effect

electrical results

Cutline tool allows 1D slices to be generated from 2D structures. Slicing can be

automated to generate several slices through a structure

Function and Macro editor allows complex functions and macros to be defined

that can be visualized as normal 1D quantity. This feature allows calculation of

M-Plots for OLED devices

Quasi 3D mode allows visualization of multi dimensional data

Fully customizable including; colors, materials, legends, toolbars and shortcuts 20.

3.3.1.1.3 MASKVIEWS

Another interesting part in SILVACO TCAD tools is MASKVIEWS. MASKVIEWS

is an IC layout editor. It is designed to interface IC layout or any complicated structured

device with SILVACOs process simulator. MASKVIEWS can be used extensively to

draw and edit any complicated device and IC layout, store and then load the complete

layout, and import or export the layout details by using the industry standard GDSII and

CIF layout format.

34

Any part of the layout can be simulated the most interesting process, and

without the hassle of structuring the codes in ATHENA; you can obtain the accurate

design based on the layout that has been accurately designed. MASKVIEWS also provides

features to allow layout experimentation such as misalignment, polygon over sizing or

under sizing, global rescales and region definition depending on combinations of

present mask elements21

.

35

CHAPTER 4

DESIGN OF CONVENTIONAL AND STRAINED SILICON MOSFET

4.1 Design of MOSFET

In this chapter, we will be discussing the important part of this project, which is

designing MOSFETs PMOS, NMOS and CMOS. Basically, the design of NMOS and

PMOS are the same, except the source/drain doping and the VTH adjustment for NMOS.

That means the material is either Arsenic or Phosphorus. The substrate for NMOS is a

p+ material, so it will be Boron. As for PMOS - the doping at the source and drain, and

also the threshold voltage adjustment is p+ material; which means it is Boron.

Next, the distinct difference between the conventional MOSFET and the strained

silicon MOSFET is minor that is the strained silicon will have two additional layers

Silicon Germanium layer on top of the substrate and Silicon layer on top of the Silicon

Germanium layer. The author would like to declare that only strained silicon NMOS will

be discussed as the flow of conventional and biaxial strained silicon is quite similar

except that conventional MOSFET does not have a silicon and SiGe layers. A bulk

CMOS design will be discussed in the subsequent subtopic.

36

4.1.1 ATHENA Design of Biaxial Strained Silicon NMOS

ATHENA enables process and integration engineers to develop and optimize

semiconductor manufacturing processes. ATHENA provides a useful and convenient

platform for simulating ion implantation, diffusion, etching, deposition, lithography,

oxidation, and silicidation of semiconductor materials. It replaces costly wafer

experiments with simulations in software to shorten the development cycles and gives

higher yields. The key features of ATHENA provided fast and accurate simulation of all

critical fabrication steps used in CMOS, bipolar, SiGe/SiGeC, SiC, SOI, III-V,

optoelectronic, MEMS, and power device technologies, apart from accurately predicts

multi-layer topology, dopant distributions, and stresses in various device structures 18

.

This advanced simulation environment allows easy creation and modification of

process flow input decks including automatic control of layout mask sequences, run-

time extraction of important process and device parameters optimization of process flow

and calibration of model parameters. Besides, this platform also enables IDMs,

foundries and fables companies to optimize semiconductor processes for the right

combination of speed, yield, breakdown, leakage current and reliability to upgrade the

equipment or the devices used. ATHENA can also be used to interface with ATLAS for

device simulation18

. The design of biaxial strained Silicon MOSFET is quite similar for

PMOS and NMOS as mentioned earlier, referring to the figure below.

37

Figure 4.1: The flow of designing a conventional MOSFET

Figure 4.2: The flow of designing biaxial strained silicon MOSFET

Define mesh,

initialize

substrate

Add epitaxial

layer

Gate Oxidation

formation

Threshold

Voltage

Adjustment

Polysilicon

patterning

Polysilicon

Oxidation

Source Drain

Annealing

Metallization

and Contact

Patterning

Reflect

Structure

Electrode

labeling

Tonyplot

Concentration

view and

Measurement

Define mesh,

initialize

substrate

Add epitaxial

layer

Deposition of

Silicon and SiGe

layer

Gate Oxidation

formation

Threshold

Voltage

Adjustment

Polysilicon

patterning

Polysilicon

Oxidation

Source Drain

Annealing

Metallization

and Contact

Patterning

Reflect

Structure

Electrode

labeling

Tonyplot

Concentration

view and

Measurement

38

Note that the only difference between the conventional MOSFET and the biaxial

strained silicon MOSFET is only the deposition of Silicon and Silicon Germanium

layers. This is a simplified version of designing a MOSFET and of course, a much more

detail process do exists. Lets discuss each part of the process starting from the first one,

thoroughly.

The very basic step is to know how to use DECKBUILD of SILVACO TCAD

Tools. DECKBUILD can only be ran in UNIX prompt which means that the next

important thing is to have a computer with UNIX and a SILVACO licensed software.

Open terminal and create a folder to specify the location of the design that will be

created. Since DECKBUILD is a very convenient and user-friendly tool, it is easy to

familiarize with it.

Figure 4.3: The view of DECKBUILD

39

4.1.1.1 Mesh Definition and Substrate Initialization

After invoking ATHENA with the command of go athena, mesh definition is

the essential part in designing a device. At the x-line, setting the mesh with too few lines

can cause the calculation to be inaccurate, while setting the grid with too dense mesh can

consume more time for ATLAS to calculate in the characterization part. At the vertical

line or y-line, the bigger the size of the lines could contribute to the increment of the

weight of the actual fabricated device. Basically, mesh definition is the part where we

can control the size of our device.

Figure 4.4: Codes for generating mesh

At the horizontal or x-line, the line has been set up to be denser at the right of the

structure with the space of 0.025 microns. This region will be the critical region of the

device, where the flow of current and channel formation will occur here. At the vertical

or y-line, almost an even mesh is created. The dimension of the device structured is

0.5 microns x 0.3 microns. Note here that the dimension specified here is only the

dimension that will be generated straight away from the codes. After reflecting it, the

dimension will be 1 microns x 0.3 microns.

# Establishing Initial Non-uniform Grid

line x loc=0.00 spac=0.075




#

line y loc=-2.50 spac=0.008



40

The structure then is initialized by defining the wafer or the substrate of the

device. This is the step where the dopants of the device is determined whether it is a

PMOS or NMOS device. In this case, since it is a NMOS device, the dopant is Boron

which is a p+ material. The concentration is set to be 2 x 1018

cm-3

, and a

orientation with two-dimensional substrate is chosen.

Figure 4.5: Codes for generating substrate material

Note that this is the code for generating a NMOS structure. For a PMOS

structure, the substrate should be doped with an n+ material, which is either Phosphorus

or Arsenic.

4.1.1.2 Epitaxial Layer

Adding epitaxial layer is a process of depositing a thin single layer crystal over a

single crystal substrate. This process is mandatory to minimize the latch-up occurrence

in VLSI (Very Large Scale Integrated Circuit) design, thus allowing a better

controllability in doping concentration and improves the device performance. Normally

the material used in epitaxial layer is the same material with used in its substrate, which

means that, for NMOS, the substrate is Silicon doped with Boron, and for PMOS is

Silicon doped with Phosphorus.

# Initializing Substrate Material

init silicon c.boron=2.0e18 orientation=100 two.d

41

Figure 4.6: Codes for depositing epitaxial layer

Figure 4.7: View of Epitaxial Layer and Substrate with Grid Definition

4.1.1.3 Deposition of Silicon and SiGe layers

As mentioned earlier, the only significant difference between a conventional

MOSFET and a biaxial strained Silicon MOSFET is the additional of two main layers

which are Silicon layer and SiGe layer on top of the silicon substrate. The layers

deposition process is executed line by line, which means that it will deposit Silicon layer

Substrate

Epitaxial layer

# Depositing Epitaxial Layer

epitaxy time=25 temp=800 thickness=0.02 c.boron=4.0e16

42

first, and then SiGe with germanium mole fraction of 0.35, and on top of it is a thin

single layer of Silicon.

Figure 4.8: Codes for depositing Silicon and SiGe layer

Figure 4.9: Silicon and SiGe layer

4.1.1.4 Formation of Gate Oxide

To obtain the gate oxide layer, an oxide layer is diffused after the deposition of

Silicon and SiGe layers. Since a very thin oxide layer needed, diffuse time is minimized

and Dry O2 process is preferred since oxide tends to grown faster in Wet O2 condition.

# Deposit Si & SiGe layer

deposit silicon thick=0.02 c.boron=1.0e16 divisions=10

deposit sige thick=0.015 c.boron=1.0e16 divisions=5 c.fraction=0.35

deposit silicon thick=0.009 c.boron=1.0e16 divisions=4

Silicon Layer SiGe Layer

43

Here, a thin layer of gate oxide of thickness less than 6nm is desired. The temperature

used normally is higher than 800c since Silicon can only be oxidized in temperature

higher than 800c.

Figure 4.10: Codes for diffusing gate oxide

Figure 4.11: The formation of Oxide layer for Gate Oxide

To obtain the accurate thickness, the thickness of gate oxide is the extracted to a

log file that can be open via Microsoft Excel.

Figure 4.12: Codes for extracting the thickness of gate oxide

# Gate Oxidation

diffus time=7 temp=900 dryo2 press=1.00 hcl.pc=3

Oxide Layer

# Extract Gate Oxide Thickness

extract name=GateOxide thickness material=SiO~2 \

mat.occno=1 x.val=0.3 datafile=gateOxide.final

44

4.1.1.5 Threshold Voltage Adjustment

The next step is to implant material for threshold voltage adjustment. This

process is needed to determine the threshold voltage. The lower the concentration of the

dopant, the lower the threshold voltage will be. The material used should be the same as

the material used in the MOSFET device. For NMOS, Boron is used, and for PMOS,

Phosphorus is used. Moderate energy is used as it does not need big junction. The

determination of threshold voltage concentration is highly related to the formation of

gate oxide. Reducing the thickness of gate oxide requires a reduction in threshold

voltage. In other words, thin gate oxide needs a small voltage to turn it on.

Figure 4.13: Codes for implanting the doping for threshold adjustment

4.1.1.6 Deposition and Patterning of Polysilicon

In this project, Polysilicon is used instead of metal as the contact. Polysilicon is a

type of material that consists of small silicon crystals. Also called Polycrystalline

Silicon, Polysilicon has been the ultimate choice as a conducting gate material for the

new generation of MOSFETs. This is due to its flexibility to become a conductor, or a

resistor, by simply changing the doping material of the Polysilicon. Eventually, the

conductivity of the Polysilicon may be increased by simply depositing a layer of metal

such as Tungsten on top of it. Virtually, a layer of Polysilicon is deposited in this step.

To pattern the Polysilicon, it is then etched from left, since it will be mirrored later. Note

that the channel length desired also depends on the length of the Polysilicon. So altering

# Vth Adjust Implant

implant boron dose=1.0e10 energy tilt=0 rotation=0 crystal

45

the length of etched Polysilicon in this process is needed to obtain the accurate desirable

result.

Figure 4.14: Codes for depositing Polysilicon

Figure 4.15: Layer of Polysilicon

Figure 4.16: Codes for patterning polysilicon

# Deposit Poly of Gate

deposit polysilicon thick=0.2 divisions=8

Polysilicon

Layer

# Etch Poly

etch polysilicon left p1.x=0.408093

46

Figure 4.17: Etched Polysilicon

4.1.1.7 Polysilicon Oxidation and Doping

The Polysilicon is then oxidized to create the effect of insulation on top of the

Polysilicon. In this project Polysilicon is diffused in a temperature of 900c since Silicon

can only be oxidized in a temperature above 800c. Wet O2 is preferred so that the oxide

layer can be grown faster.

Figure 4.18: Codes for Polysilicon oxidation

Etched

Polysilicon

Layer

# Poly Oxidation

method Fermi

diffus time=3 temp=900 weto2 press=1.00

47

Figure 4.19: Oxidized Polysilicon

The next crucial step is the Polysilicon doping. This step is needed to alter the

junction of source drain and to ensure the conductibility of the Polysilicon gate. For

NMOS, Polysilicon is doped with an n+ material; while for PMOS, Ploysilicon is doped

with a p+ material. Since TCAD tools has its own limitation, which is etching the

Polysilicon might not affect the channel length when the channel length is too short, you

may found out that altering the doping concentration of Polysilicon is somehow useful to

obtain the accurate desirable channel length. In this process, Polysilicon is implanted

with 5x1014

cm-3 Phosphorus with a small amount of energy.

Figure 4.20: Codes for Polysilicon doping

# Poly Doping

implant phosphor dose=5.0e14 energy=13 crystal

48

4.1.1.8 Spacer Oxide

To prevent ions from being implanted to the gate, a layer of spacer oxide with

thickness of 0.12microns is deposited and then etched. Normally the thickness of the

spacer oxide is only about 10% of the Polysilicon thickness. Since the thickness of

Polysilicon is 0.2 microns, the thickness of spacer oxide can be 0.02 microns. However,

this condition is not mandatory.

Figure 4.21: Codes for depositing spacer oxide

4.1.1.9 Source and Drain Annealing

Right after spacer oxide process, the source and drain formation is done. The

device is implanted with a dopant of 1 x 1016

cm-3. For NMOS, the dopant is an n+

material such as Phosphorus or Arsenic, and for PMOS, the dopant is a p+ material,

which is Boron. This process is also called ion implantation, where a chemical species

directly bombarded into a substrate with a high energy ions of the chemical for

deposition.

# Deposit Spacer Oxide

deposit oxide thick=0.12 divisions=10

#Etch Spacer Oxide

etch oxide thick=0.12

49

Thermal diffusion process has been replaced by ion implantation process for

doping a material in wafer fabrication since it the control of the process of depositing

dopants atoms into the substrate, is much more precise as compared to the thermal

diffusion process. However, the damage caused by atomic collisions during ion

implantation changes the electrical characteristics of the target. Many target atoms are

displaced, creating deep electron and hole traps which capture mobile carriers and

increase resistivity. To repair the lattice damage and inserting the dopant in

substitutional sites where they can be electrically active again, annealing is therefore

needed in this process 11

.

Figure 4.22: Codes for implanting and annealing source and drain

Figure 4.23: The view of source and drain region/junction

# Source Drain Implantation

implant phosphor dose=1.0e16 energy=20 crystal

# Source Drain Annealing

method fermi

diffus time=1 temp=900 nitro press=1.00

Source/Drain region

50

4.1.1.10 Metallization and Contact Patterning

After the formation of body, gate, source and drain, the structure is the ready for

the next step, which is depositing and patterning the contact. When contact is deposited,

the layer of metal is electrically interconnected the device fabricated on the silicon

substrate. The material used for the contact is Aluminium, since it has a very low

resistivity (high conductivity) and its adhesion compatibility with SiO2. In this step, a

very thin layer of metal which in this case is Aluminium, is deposited, and a portion of

it is etched away, leaving a contact right on top of the source and drain region.

Figure 4.24: Codes for depositing and patterning Aluminium

4.1.1.11 Structure Reflection and Electrode Labeling

Since the structure obtained all the way through these processes is only half of

the device structure, the second final process of structuring a device using ATHENA is

to mirror the structure (if it happens the structure is symmetrical). The process eased the

burden of creating the same step over and over again, thus, minimized the risk of errors

occur in the process of structuring a device.

# Aluminium Deposition

deposit aluminum thick=0.03 divisions=2

# Etch Aluminium

etch aluminium right p1.x=0.18

51

Figure 4.25: Codes for reflecting structure

Figure 4.26: Reflected structure

Finally, the device is then labeled for the ease of analysis and the output file is

created. Labels included source, drain, gate, and backside.

# Mirror structure

struct mirror right

52

Figure 4.27: Codes for labeling structure and creating output file

4.1.1.12 TONYPLOT Concentration View and Measurement

The out file of a biaxial strained Silicon NMOS is now obtained. The next step is

to view the structure and measure the channel length of the device and to ensure that the

channel length is the desirable length. By using another advance feature of TONYPLOT

by SILVACO, the effective channel length can be measured by simply viewing the

concentration view and displaying the junction, and zooming right beneath the gate.

Note that the length measured is in microns.

The out file obtained later is exported into ATLAS right after invoking ATLAS

with the command of go atlas. As mentioned earlier, the process of structuring a

conventional NMOS and PMOS is similar to the process of creating biaxial strained

Silicon NMOS and PMOS.

# Label structure

electrode name=source left

electrode name=gate x=0.5

electrode name=drain right

electrode name=backside backside

# Struct Outfile

struct outfile=ssin.str

53

Figure 4.28: Codes for viewing the structure

Figure 4.29: Concentration view and channel length measurement

Overall, the specification of MOSFETs that have been designed is illustrated in

Table 4.1. Effective channel length, gate oxide thickness, threshold voltage and

germanium fraction are the important specification the author has observed.

# Tonyplot structure

tonyplot ssin.str

54

Table 4.1: Specification of simulated devices

Specification NMOS sSi NMOS PMOS sSi PMOS

Effective

Channel

Length (nm)

45 45 45 45

Gate Oxide

thickness (nm)

5.7 5.7 5.7 5.7

Vth at vd=0.1v 1.50 0.2625 -1.30 -0.80

Germanium

fraction

- 0.35 - 0.35

4.1.2 MASKVIEWS Design of Conventional and Biaxial Strained Silicon

Complementary MOSFET

As mentioned above in Chapter 3 Methodology, the design of conventional

bulk CMOS and biaxial strained silicon CMOS can be accomplished by using another

powerful tools provided by SILVACO. If you have any experience creating or designing

a layout, let say in TSPICE L-edit layout, you may have a clue on the topic we are about

to discuss.

MASKVIEWS by SILVACO provided a very handy help which can ease the

burden of creating a complicated device. As you may find typing or even generating the

codes with GUI (Graphical User Interface) is somehow a tedious process for a

complicated device such as Complementary MOSFET, MASKVIEWS is the sole, easiest

solution to this problem.

Some researchers and student tried to construct a CMOS and any other

complicated device using solely ATHENA and ATLAS, including the author. Basically,

55

the structure obtained will have the resemblance of a Complementary MOSFET, and the

STI (Shallow Trench Isolation to isolate between NMOS and PMOS) is simply the

etched Silicon that has been oxidized. But the significance problem arose is that how to

get the accurate effective channel length desired? ATHENA can design and using

TONYPLOT the cross-section of the simulated device can be observed. By using,

MASKVIEWS, layout is designed using top-view of the device, and the characteristics

will be exported to ATHENA to generate the cross-section view.

Figure 4.30: The first trial of creating a bulk CMOS

The only solution is to use MASKVIEWS to produce a GDS layout, and extract it

to ATHENA to produce the structure. Since MASKVIEWS license is not available, the

author could not proceed with this step to create a bulk CMOS and a bulk biaxial

strained silicon CMOS. The author will discuss MASKVIEWS processes by referring to

SILVACO MASKVIEWS manual and journal from SILVACO 21

. The recipe of

simulation should be observed and done carefully, since even with MASKVIEWS aid, if

the simulation recipe is incorrect, the desirable result could not be obtained. Figure 4.31

56

shows the flowchart to design a CMOS and Figure 4.32 shows the recipe and steps to

design a CMOS.

Figure 4.31: Flowchart of creating a conventional CMOS

57

The process recipes and fabrication flows are referred from University of

California, Berkeley Micro lab open source 21

.

Figure 4.32: Steps of processes of fabricating conventional CMOS

The only significant difference between designing a conventional CMOS and

biaxial strained silicon CMOS is that, biaxial strained silicon CMOS includes the

process of depositing a thin silicon layer and SiGe layer on top of the substrate.

MASKVIEWS Base Window can be invoked within DECKBUILD. Examples can be

loaded, similar with loading the examples of ATHENA and ATLAS.

58

Figure 4.33: MASKVIEWS Base Window

After creating the layout and converting it to GDS II format (industry format),

the parameters generated is sent to ATHENA to construct the structure of a complicated

device.

Figure 4.34: A 0.35 um conventional CMOS GDS layout

59

Figure 4.35: Top view and side view of 0.35um CMOS using MASKVIEWS

The structure of a complicated device in this case CMOS is then straight

away generated from the out file of GDSII format.

Figure 4.36: Structure obtained from GDSII layout

60

Figure 4.37: Concentration view of 0.35um CMOS

Comparing a conventional CMOS and biaxial strained silicon CMOS structure,

the only distinct difference between both devices is that the absence of a thin silicon

layer and a SiGe layer on top of the conventional CMOS substrate. Thus, in the design

steps of biaxial strained silicon CMOS, there will be extra step of depositing a very thin

silicon layer and SiGe layer on top of its substrate.

61

Figure 4.38: Flowchart of creating biaxial strained silicon CMOS

62

CHAPTER 5

CHARACTERIZATION OF BIAXIAL STRAINED SILICON MOSFETS

The design of conventional and strained Silicon MOSFETs has been discussed

thoroughly in the last chapter. The next step conducted in this project is to characterize

the electrical properties of the devices that have been simulated previously, before

comparison and conclusion is made. In this chapter, ATLAS as a device simulator is

discussed as well as the electrical properties of the devices.

5.1 ATLAS Device Simulation Framework

ATLAS enables device technology engineers to simulate the electrical, optical,

and thermal behavior of semiconductor devices. ATLAS provides a physics-based, easy

to use, modular, and extensible platform to analyze DC, AC, and time domain responses

for all semiconductor based technologies in two and three dimensions12

.

The key features of ATLAS are that ATLAS can accurately characterize physics-

based devices in 2D or 3D for electrical, optical, and thermal performance. This means

63

that ATLAS can characterize without costly split-lot experiments, solve yield and

process variation problems for optimal combination of speed, power, density,

breakdown, leakage, luminosity, or reliability. ATLAS also is fully integrated with

ATHENA process simulation software, comprehensive visualization package, extensive

database of examples, and simple device entry, that can be chosen from the largest

selection of silicon, III-V, II-VI, IV-IV, or polymer/organic technologies including

CMOS, bipolar, high voltage power device, VCSEL, TFT, optoelectronic, LASER,

LED, CCD, sensor, fuse, NVM, ferro-electric, SOI, Fin-FET, HEMT, and HBT, as well

as connect TCAD to Tape-out with direct import of ATLAS results into UTMOST for

SPICE parameter extraction. ATLAS is also worldwide support software 28

.

Figure 5.1: ATLAS inputs and outputs

64

5.2 Device Characterization using ATLAS Simulator

The most commonly used inputs of ATLAS are text file (.txt file) and structure

file (.str file). Commands written in text file can be executed by running the coding

while the structure defined in structure file can also be exported for the device

simulation12

.

Besides, ATLAS produces three outputs: run-time output, log files (.log) and

solution files. Run-time output will display the progress of simulations running,

warning or error messages if any. Log file (.log file) stores all the terminal current and

voltage values from the device simulation. These values are then extracted and used for

data analysis in Microsoft Excel. Solution file will stores two or three dimension data

that related to the values of solution variables within the device for a bias point12

.

Figure 5.2: Order of Statement in ATLAS Simulation

Mesh

Region

Electrode

Doping

Structure

Specification

Material

Models

Contact

Interface

Material

model

Specification

Method

Numerical

Models

Specification

Log

Solve

Load

Save

Solution

Specification

Extract

Tonyplot

Result

Analysis

65

To start the device simulation, the input file of structure specification can be read

from another existing file. The input file of ATLAS in this project is taken from the

structure file (.str file) created in ATHENA. The result analysis is done to obtain the

characterizations of biaxial strained Silicon MOSFET and conventional MOSFET in the

following sub chapters12

.

5.3 Drain Current versus Gate Voltage (ID vs. VGS)

Characterization of biaxial strained silicon MOSFETs is done using ATLAS.

Both MOSFETs were characterized in a similar way, except that a negative voltage is

supplied to biaxial strained silicon PMOS, and positive voltage is supplied to biaxial

strained silicon NMOS. To plot drain current versus gate voltage (ID vs. VGS) graph,

each of the nodes of gate, source and drain is biased at different value of voltage. At the

gate of NMOS, the voltage is ramped from zero volts (0V) to three volts (3V) with steps

value of +0.1V. Drain voltage is biased with two different values that have a big

difference, which is 0.1V and 1V. The source is biased with zero voltage. The same

values have been applied to the conventional NMOS.

As for PMOS, gate voltage has been ramped from 0V to -3V. A negative voltage

must be applied to the gate in order to make the inversion layer charge equal to zero,

whereas a positive gate voltage will induce a larger inversion1. Drain voltage is biased

with -0.1V and -1V, and the same value is supplied to the conventional PMOS.

66

Figure 5.3: ID-VGS of NMOS and strained Silicon NMOS at VDS = 0.1V

From Figure 5.3, graph of ID-VGS of NMOS and strained Silicon NMOS at VDS

= 0.1V, it can be observed that strained silicon NMOS has a threshold voltage around

0.26V. Comparing with conventional NMOS, the same threshold adjustment results a

different threshold voltage. This is one of short channel effects that occur when the

channel length is too small.

The concentration at threshold voltage adjustment is the same, which is 1.01010

cm-3

. Unfortunately, the conventional NMOS suffers hot electrons effect. Hot electron

effect has increased the actual value of threshold voltage, thus, degraded the device

performance. This effect is not something that can be reduced by simply reducing the

concentration of the threshold implant, even the purpose of altering threshold implant

concentration is suppose to adjust the threshold voltage.

-2.00E-05

0.00E+00

2.00E-05

4.00E-05

6.00E-05

8.00E-05

1.00E-04

1.20E-04

1.40E-04

1.60E-04

1.80E-04

0.0

0E+

00

2.0

0E-

01

4.0

0E-

01

6.0

0E-

01

8.0

0E-

01

1.0

0E+

00

1.2

0E+

00

1.4

0E+

00

1.6

0E+

00

1.8

0E+

00

2.0

0E+

00

2.2

0E+

00

2.4

0E+

00

2.6

0E+

00

2.8

0E+

00

3.0

0E+

00

ID - VGS of NMOS at VDS=0.1V

NMOS

sSi NMOS

67

Figure 5.4: ID-VGS of PMOS and strained Silicon PMOS at VDS = 0.1V

From Figure 5.4, graph of ID-VGS of PMOS and strained Silicon PMOS at VDS =

0.1V, it can be observed that strained Silicon PMOS has a threshold voltage around

0.80V. Comparing with conventional PMOS, the same threshold adjustment or threshold

implant concentration results a different threshold voltage. This is one of short channel

effects that occur when the channel length is too small.

The concentration

cmos thesis

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