cmos linear mixer design for high performance receiver applications
DESCRIPTION
CMOS Linear Mixer Design for High Performance Receiver Applications. Jiming Jiang22 Sept 2005 Department of Engineering, University of Cambridge. Design Issue. Non-linearity Bandwidth Power Consumption Conversion Gain Noise. Process. 0.35um. 0.18um. 0.13um. 0.09um. IIP3. - PowerPoint PPT PresentationTRANSCRIPT
CMOS Linear Mixer Designfor
High Performance Receiver Applications
Jiming Jiang 22 Sept 2005
Department of Engineering, University of Cambridge
Design Issue
• Non-linearity
• Bandwidth
• Power Consumption
• Conversion Gain
• Noise
Target Specification
150MHz
300MHz
1.5GHz
0dB
10-15dB
5-10dBm
0.35um
5dB 0-5dB
5-10dB 10dB
5dBm 0-5dBm
1.2GHz600MHz400MHzBandwidth
2.5GHz1.2 GHz600MHzIntermediate Frequency
10GHz 5GHz2.5GHzRadio Frequency
0-5dBConversion Gain
10dBNoise Figure
5dBmIIP3
0.09um 0.13um0.18umProcess
1 2
212 122
Fundamental
IMD3IMD3
Non-linearity: Third Order Inter-modulation Distortion
Analysis Methods for Prediction of Non-linearity
• Taylor series– Simple approach but not adequate for high frequency analysis
• Harmonic balance– Accurate but only suitable for numerical work, eg computer simulation
• Volterra series– Accurate but complicated procedure demanded
XTTzzsCT
sA
ssA
sssAIM sggs 234
1
3
1
211
2,1,133 2)(1
)(
4
3
)2(
)(
4
3
IMD3 using Volterra Series
)2(
),,(
4
3
211
21133 SSA
SSSAIM
)]()()()(2][1))(
)([(2
4
31
213212
2
SDSDTSDSDTSCg
gSCggSCZZ
T gdds
mgddsmgssg
Common Source:
Differential Pair:
)]2()2(3
1)()(
3
2[ 11
1
2 szsAszsAT
TX ss
Inductance Negative real number Decrease
Capacitance Positive real number Increase
)(1 sggs zzsC sgsZsC
Discussions:Linearity improvement methods
Discussion 1: Linearity Enhancement based on degeneration component
Discussion 2:Linearity based on A1(s) and T1
Increasing A1(s) -> Linearity decrease
Increasing T1 -> Linearity increase
Linearity Enhancement With Capacitance and Degeneration Inductance
gZ
I
inV
sZ
inV
I
External C
sL
With source and degeneration impedance With external capacitance and degeneration inductance
1I
inV inV
R R
1I
inV inVL L
inV inVC
Resistive CapacitiveInductive
Good Linearity
Noisy resistance
Good Linearity
No noise Added
Bad Linearity
Noisy Source
Conclusion
IIP3 With Swept Inductance and Capacitance Value
NB: Simulation is based on AMS 0.35um BSIM3 Model
1I
inVL L
inV
Inductance degeneration Capacitance degeneration
Simulation Circuit Setup
CinV inV
Without Improvement (IIP3=10dbm)
With Improvement (IIP3=23.5dBm)
inPP outPP inAP outAPInput Output
Transconductance Switching stage
inPP
outPP
inAP
outAP
Input
Output
Proposed Linearity Enhancement method: Pre-Distortion