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ClawZ

—Diagram Translator Test Cases

Version: 10.6Date: 20 June 2003Reference: DAZ/INT517Pages: 54

Prepared by: R.B.JonesTel: +44 1344 642507E-Mail: [email protected]

LEMMA1

Lemma 1 Ltd. DAZ/INT517: ClawZ - Diagram Translator Test Cases 2

0 DOCUMENT CONTROL

0.1 Contents

0 DOCUMENT CONTROL 2

0.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.2 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.3 Document Cross References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.4 Changes History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.5 Changes Forecast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1 GENERAL 4

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.2 Notation and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 OVERVIEW 4

2.1 Testing Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 MODEL FILES 5

4 LIBRARY FILES 6

5 .M FILES 6

6 TESTS 6

7 MODELS - NOTES AND DIAGRAMS 7

7.1 Alf’s Model - RBJ version (int517a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77.2 Digital Addition Model (int517b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97.3 Simulink Demo Models (int517c and int517d) . . . . . . . . . . . . . . . . . . . . . . . 107.4 Alf’s Model (int517e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117.5 The DERA Bedford Control Model (int517f) . . . . . . . . . . . . . . . . . . . . . . . 137.6 Loose Ends Model (int517g) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147.7 Fcn Expression Test Model (int517k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157.8 Library with Masks and Buses (int517l) . . . . . . . . . . . . . . . . . . . . . . . . . . 167.9 Block Reference Test Model (int517m) . . . . . . . . . . . . . . . . . . . . . . . . . . . 207.10 QinetiQ Block Reference Example Library (int517n) . . . . . . . . . . . . . . . . . . . 227.11 QinetiQ Block Reference Example Model (int517o) . . . . . . . . . . . . . . . . . . . . 227.12 Diagnostic Model (int517p) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227.13 Name Translation Model (int517q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237.14 Signal block synthesis and virtualization (int517r) . . . . . . . . . . . . . . . . . . . . 267.15 Name Translation Model (int517s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287.16 QuintetiQ Mux Virtualization Model (int517t) . . . . . . . . . . . . . . . . . . . . . . 297.17 QuintetiQ Action Subsystem eg5 (int517u) . . . . . . . . . . . . . . . . . . . . . . . . 307.18 Action Subsystem Error Checks (int517v) . . . . . . . . . . . . . . . . . . . . . . . . . 337.19 QuinetiQ Action Subsystems (eg1,eg3) (int517w) . . . . . . . . . . . . . . . . . . . . . 527.20 Digital Clock Example (digclock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547.21 Fcn Example Model (fcn eg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54


0.2 List of Figures

0.3 Document Cross References

[1] LEMMA1/DAZ/ZED504. ClawZ - Model Translator Specification. R.B. Jones, Lemma 1 Ltd.,[email protected].

[2] LEMMA1/DAZ/ZED507. ClawZ - Extending the Z Library. R.B. Jones, Lemma 1 Ltd.,[email protected].

0.4 Changes History

Issue 2.1 First issue.

Issue 5.1 (Phase 3) Final issue to DERA. The integration tests are enhanced to provide testingof the new features in the translator introduced in Phase 3. The DERA Bedford “control”model has been added as a supplementary integration test (it is expected to translate but notto type-check). Tests of the .M file translator have been added.

Issue 6.1 (Real Clawz first delivery) Tests enhanced to cover translation of Matlab .M files.

Issue 7.1 (Real Clawz final delivery) Tests enhanced to cover expression translation and otherenhancements.

Issue 7.3 (Clawz extensions final delivery) The document has been simplified and more diagramshave been added.

Issue 7.4 (Clawz extensions II first delivery) Rework of tests to use Mux/Demux synthesis withinjected port type information where necessary. Additional tests for improvements to signalinference and synthesis.

Issue 10.2 (Clawz extensions II final delivery) Addition of tests for virtualization simplificationsand for virtual loop handling to int517r. Addition of test int517t, which is a Mux/Demuxvirtualization test from QuinetiQ.

Issue 10.4 JANUARY 2003 - Support for action subsystems. Addition of tests int517u (actionsubsystems) and int517v (action subsystem errors). Insertion of action subsystems into int517l,int517m, including covering QuinetiQ eg6.

Issue 10.5 MAY 2003 - Support for action subsystems merge synthesis. Updates to tests int517l.mdl,int517m.mdl, int517u.mdl, int517v.mdl.

Issue 10.6 JUNE 2003 - Support for block references to artificial subsystems of libraries. Updatesto run scripts for tests int517l.mdl and int517m.mdl. Change to int517v.mdl.

0.5 Changes Forecast

None.


1 GENERAL

1.1 Introduction

This document is one of the deliverables from the Control Law project, placed by DERA Malvernwith Lemma1 Ltd. and various subsequent contracts enhancing and extending the resulting ClawZtool.

1.2 Notation and Conventions

The integration tests in this document consist of Simulink models to be translated by the ControlLaw diagram translator.

The main purpose of the document is to provide access to the diagrams for the models independentof access the capability to run Simulink, and to describe the purpose and scope of the various tests.Though originally the simulink models were contained in this document and extracted from it, thisarrangement proved practically cumbersome and the models are now held as separate ascii files.

2 OVERVIEW

2.1 Testing Methods

The integration testing of the translator is undertaken in the following manner:

Preparation of Models First a small number of Simulink models are prepared or selected for usein the integration tests. For each of the models diagrams are saves as encapsulated postscriptfrom Simulink. The models are also saved in simulink model file format (.mdl). Some of thediagrams are presented in this document. All diagrams and models are available in the projectRCS repository.

Translation of Models The integration test makefile feeds the various matlab .m files and simulink.mdl files, together with appropriate library metadata files into the translator. ClawZ is thenused to process the files and produce ProofPower-Z specifications suitable for processing byProofPower.

Automatic Checking of the Translations Two automatic checks are performed on the outputof the translator.

Firstly there is a facility in the makefile to perform diffs comparing the output with that ofprevious runs. This is particularly useful to check that a small change has not had unintendedconsquences.

Secondly, the output of ClawZ can be automatically type-checked by ProofPower, in the contextof appropriate libraries. Some of the tests now involve loading one or more translated .m fileor libraries to provide the context for checking the actual model.


Further Assessment of the Translations Once the output from the tool has been shown to betype correct, a further stage of assessment is undertaken, firstly to ensure that the output ofthe translator conforms to the specification of the translator in [1], and then to assess it in themore general way required for the final report.

Production of Report The assessments are documented in a report which describes the resultsof the system tests and also includes an assessment of the capabilities and limitations of thetranslator.

3 MODEL FILES

The following model files are used in the tests:

alfs3v2.mdl A second version of Alf’s model as built using Simulink by Alf.

digclock.mdl An example used in the User Guide.

fcn eg.mdl An example involving an Fcn block used in the User Guide.

int517a.mdl Our own first transcription of Alf’s model from a paper copy into Simulink.

int517b.mdl The digital adder. This is a primarily oriented to testing nested subsystems. It has beenadapted to test the output direction facility.

int517c.mdl The F14 model.

int517d.mdl The Abs Brakes example.

int517e.mdl A version of Alf’s model edited to test scalar literals.

int517f.mdl This is a large model previously known as the DERA Bedford control model.

int517g.mdl A small model introduced for testing vector parameters, and tolerance of one-ended lines.

int517k.mdl Special model primarily for testing Fcn parameter expressions and matlab expressions as blockparameters.

int517m.mdl A model testing library reference.

int517o.mdl A model supplied by QinetiQ primarily for illustrating their use of libraries and block reference.

int517p.mdl A small model used to isolate problems during early testing, this is edited as needed and notintended as a stable test.

int517q.mdl A small model intended to test the name/path translation facilities and the use of matlabvariable types in signal inference.

int517r.mdl A QuinetiQ example concerning propagation of signal names, subsequently augmented forvirtaulization.

int517s.mdl A QuinetiQ example concerning effects of angled brackets in signal names on bus selection.


int517t.mdl A QuinetiQ example (clawz112 issue 1) concerned with ordering of inputs to virtualized Muxblocks.

int517u.mdl A QuinetiQ example (eg5) used to agree details of implementing support for action subsystems.

int517v.mdl A model for testing the error checks associated with action subsystems, also for errors onartificial subsystems and block references.

int517w.mdl A model combining two QuinetiQ action subsystem examples (eg1 and eg3).

unitdelay.mdl An example involving a unitdelay used in the User Guide.

4 LIBRARY FILES

The following library files are used in the tests:

int517l.mdl A library file which constructed for testing library translation and block reference, and also fortesting masked subsystems and artificial subsystems of libraries.

int517n.mdl A library file supplied by QuinetiQ and referred to by int517o.mdl.

5 .M FILES

The following .m files are used in the tests:

int517i.m This .m file serves primarily to define the external variables required by the Abs Brakes model(int517d.mdl), but also exercises various features of matlab expressions.

int517j.m This .m file tests matlab expressions in .m files and defines certain variables which are used inthe model int517k.mdl (which exercises some of the special cases identified by DERA as usedin their applications).

int517z.m The is adapted from an example provided by DERA.

mfile eg.m To illustrate the use of a translated .M file in conjunction with a Simulink model, a very simplemodel (fcn eg.mdl) has been constructed which uses a variable defined in this .M file.

The .M file defines the variable factor that is used in the parameter expression of the Fcn block.Custom schemas implementing this block and the Display block are given in [2].

6 TESTS

Tests are run with composite metadata files obtained by extracting metadata from one or more filesand concatenating the results.


Each test corresponds to one run of ClawZ and hence processes one .mdl file. Each .m file is alsotranslated in a separate run of ClawZ.

When type checking the results it is sometimes necessary to load more than one file, for examplewhen a model depends upon definitions supplied in a .m file, or when it referrs to blocks in a library.

Details of which metadata is used for each test and which combination of files is used for typechecking should be sought in the make file.

7 MODELS - NOTES AND DIAGRAMS

7.1 Alf’s Model - RBJ version (int517a)

There are now several versions of Alf’s model in use.

This version was constructed by Roger Jones before Alf did his own Simulink model, and is intendedmore as a sensible test of the translator than as an accurate Simlink rendition of the original.

The main respects in which it differs from Alf’s model are:

1. The discrete integrator in the Simulink library is used. This is less complex than that definedby Alf and also takes some values (e.g. limit values) as parameters rather than inputs.

2. The continuous differentiator from the Simulink library has been used, because no discretedifferentiator is provided. It is proposed to translate this as if it were a discrete integrator.

3. I originally designed a subsystem to do the scale function and then realised that a block wasavailable. Since this was the only subsystem I decided to leave it as a trivial subsystem, justto make it a slightly better test of the translator.

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1

OUTPUT

subtract

add2

add1

Divisor

Mult

Input

Out1

Scale5

Divisor

Mult

Input

Out1

Scale4

Divisor

Mult

Input

Out1

Scale3

Divisor

Mult

Input

Out1

Scale2

Divisor

Mult

Input

Out1

Scale1 Saturation

2

SMPIDO

1

SDPIDO

500

SCFPRP

1200

SCFPRF

1250

SCFINT

25

SCFDIF

T

z−1xo

Discrete−TimeIntegrator

du/dt

Derivative

1

DFMVGP

1

DFMVGD

5

DFMVG1

4

DFMVGF

3

FMVPV

2

FMVPE

1

IntInir

SCALEINPUT

FMVER2

FMVDTM

FMVPTM

FMVER1

INTINPUT

SCDIF

FMVFTM

UPPER_LINRES

Varian

tof

Alf’s

Model

(int517a1.ep

)


1

Out1

Product

3

Input

2

Mult

1

Divisor

Scale subsystem (int517a2.eps)

7.2 Digital Addition Model (int517b)

This example is mainly for testing depth and complexity of the diagrams. The library blocks usedare straightforward.

2

C

1

S

AND

LogicalOperator1

XOR

LogicalOperator

2

B

1

A

Half Adder (int517b4.eps)

2

CO

1

SOR

LogicalOperator

A

B

S

C

Half Adder1

A

B

S

C

Half Adder

3

CI

2

B

1

A

Full Adder (int517b3.eps)


2

CO

1

S

Mux

Mux

ABCI

S

CO

Full Adder4

ABCI

S

CO

Full Adder3

ABCI

S

CO

Full Adder2

ABCI

S

CO

Full Adder1Demux

Demux2

Demux

Demux1

3

CI

2

B

1

A

4-bit Adder (int517b2.eps)

1

S

z

1

UnitDelay4bit

A

B

CI

S

CO

4−bit Adder

2

B

1

A

Nibble-serial Adder (int517b1.eps)

7.3 Simulink Demo Models (int517c and int517d)

Two of the demonstration models provided with the Simulink software are used in the system tests.They are the F14 flight controller and the ABS brakes simulation. It was not originally expected thatthe tool would be able to produce good translations of these models, but it was required that the toolbehave reasonably and helpfully when asked to translate a model which is beyond its capabilities.

The reader is referred to the Simulink system for the details of these model, which we are not ableto supply since the copyright belongs to The MathWorks Inc.

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Alf’s

Model(in

t517e)

1

FMTMCD

upper

Upper

z

1

UnitDelay2

z

1

UnitDelay1

sub

Sub

scale

Scale5

scale

Scale4

scale

Scale3

scale

Scale2

scale

Scale1

2

SMPIDO

1

SDPIDO

500

SCFPRP

500

SCFPRF

1250

SCFINT

25

SCFDIF

limit2

Limit2

limit1

Limit1

integrator

Integrator

2048

ITGAIN

differentiator

Differentiator

1

DFMVGP

1

DFMVGD 25

DFGAINadd

Add4add

Add3

add

Add2

add

Add1

65536

65536

8

CFMCMN

7

CFMCMX

6

DFM2MX

5

DFM2MN

4

DFMVGF

3

FMVPV

2

DFMVGI

1

FMVPE

FMVER2

SINPUT

LIMINP

SCDIFFMVDTM

LINRES

FMVFTM

INTRESINTINPUT

FM1MN

FM1MX

ULINRES

(int517e1.ep

s)


1

Out1Saturation

Mux u[1] + u[2]

Fcn

2

In2

1

In1

(int517e2.eps)

1

Out1Saturation

Mux f(u)

Fcn

3

In3

2

In2

1

In1

(int517e6.eps)

1

Out1

Mux

Mux

max

MinMax1

min

MinMax

3

In3

2

In2

1

In1

(int517e8.eps)


1

Out1Saturation

Mux u[1]*u[2]/u[3]

Fcn

3

In3

2

In2

1

In1

(int517e10.eps)

1

Out1Saturation

Mux u[1] − u[2]

Fcn

2

In2

1

In1

(int517e15.eps)

1

Out1

u / 65536

Fcn

1

In1

(int517e16.eps)

7.5 The DERA Bedford Control Model (int517f)

This is the largest model to which we have access, and the one which is probably most representativeof the applications for the ClawZ tool in DERA. Because of its size the diagrams are omitted.


7.6 Loose Ends Model (int517g)

This model is intended to check the following features of the ClawZ translator:

1. Tolerance of one-ended lines

2. Scalar, Vector and Matrix parameter types and their use with overlapping generic specifications.

z

1

Unit Delay3

z

1

Unit Delay2

z

1

Unit Delay1

z

1

Unit Delay

Terminator

Selector

MuxMux

y(n)=Cx(n)+Du(n)x(n+1)=Ax(n)+Bu(n)

Discrete State−Space

Demux3

Constant2

2

Constant1

1

Constant

(int517g.eps)


7.7 Fcn Expression Test Model (int517k)

1

Out1

In1 Out1

ss1

signal1

signal2

signal3

signal4

signal5

signal6

Look−UpTable (2−D)1

Look−UpTable (2−D)

5

Fcn6

5

Fcn5

f(u)

Fcn4

f(u)

Fcn3

u*u

Fcn2

u(4)

Fcn1

u(u(1)+1)

Fcn

num(z)

den(z)

Discrete/transfer

VEC([1 3 5 7])

Constant6

VEC(1:3)

Constant5

−C−

Constant4

(−N N)

Constant3

VEC(N)

Constant2

VEC(N+1:2*N)

Constant1

VEC(1:N+3)

Constant

1

In1

(int517k1.eps)

1

Out1

In1 Out1

SubSystem

1

In1

(int517k2.eps)

1

Out1

u*u−u/8

Fcn

−C−

Constant

1

In1

(int517k3.eps)


7.8 Library with Masks and Buses (int517l)

Out1

Subsystem1

In1

Out1

Out2

Subsystem0

Display2

0

Display1

(int517l1.eps)

2

Out2

1

Out1

0

Display8

0

Display7

0

Display6

0

Display5

0

Display4

0

Display3

0

Display2

0

Display1

0

Display

Demux

Demux

Demux

1

In1

<alpha>

<middle>

<signal3> <signal1>

<signal1, middle, signal3><signal3>

<signal1>

(int517l2.eps)


1

Out1

Out1

Subsystem1

Out1

Subsystem

4

Constant4

6

Constant3

5

Constant1

mux2

middle

(int517l3.eps)


1

Out1u1

case [ 1 ]:

case [ 2 3 ]:

default:Switch Case

default: { }In1 Out1

SCAS2

case: { }In1 Out1

SCAS1

case: { }In1 Out1

SCAS

Merge

Merge

editvar

Constant5

checkvar

Constant2

popupvar

Constant

alpha

(int517l4.eps)

1

Out1z

1

Unit DelaySwitch

editvar

Constant5

checkboxvariable

Constant2

case: { }

Action Port

1

In1

(int517l5.eps)


1

Out1z

1

Unit DelaySwitch

editvar

Constant5

popupvar

Constant2

case: { }

Action Port

1

In1

(int517l6.eps)

1

Out1

In1

In2

In3

Out1

Subsystem

editvar

Constant5

popupvar

Constant2

default: { }

Action Port

1

In1

(int517l7.eps)

1

Out1z

1

Unit DelaySwitch3

In3

2

In2

1

In1


(int517l8.eps)

7.9 Block Reference Test Model (int517m)

Out1

Subsystem2

In1

Out1

Out2

Subsystem

Out1

Sub system

ActionIn1 Out1

SCAS2

ActionIn1 Out1

SCASMerge

Merge

else { }In1 Out1

If ActionSubsystem

u1

u2

u3

if(u1)

elseif(u2)

elseif( u3)If

In1 Out1

Enabled andTriggered Subsystem

In1 Out1

EnabledSubsystem

0

Display32

Constant3

45

Constant2

32

Constant1

(int517m1.eps)

1

Out1

Enable

1

In1


(int517m2.eps)

1

Out1

In1 Out1

Enabled andTriggered Subsystem

Trigger Enable

1

In1

(int517m3.eps)

1

Out1

Trigger Enable

1

In1

(int517m4.eps)

1

Out1

In1

In2

In3

Out1

Subsystem

1

Constant1

constantvar

Constant

else { }

Action Port1

In1

(int517m5.eps)


7.10 QinetiQ Block Reference Example Library (int517n)

VARIABLE

Variable

Z−1

Delay

On Off

On−Off Delay Timer

S

Differentiation with gain input

ABS

Absolute Value

(int517n.eps)

7.11 QinetiQ Block Reference Example Model (int517o)

2

Out2

1

Out1

VARIABLE

Variable

Z−1

Delay

On Off

On−Off Delay Timer

S

Differentiation with gain input

1

Constant4

0

Constant3

1

Constant2

1

Constant1

1

Constant

ABS

Absolute Value1

In1

(int517o.eps)

7.12 Diagnostic Model (int517p)

In1

In2

Out1

Subsystem 0

Display7

0

Display6

1

Constant1

1

Constant


(int517p1.eps)

1

Out12

In2

1

In1

(int517p2.eps)

7.13 Name Translation Model (int517q)

This model tests:

• Name translation

• Signal inference

• Selector and Terminator blocks


1

Out1

(N)

the nameof the constant

vec4

a/6*

vec8

_abS5S

vec2

_a_b__c___d

vec3

__S_SS__SSS___

vec7

Sab_

vec6

7__

VEC

VEC

1

In1in1

a

b

c

d

e

f

g

h

j

(int517q1.eps)


1

Out1

N

the nameof the constant

vec4

a/6*

vec8

_abS5S

vec2

_a_b__c___d

vec3

__S_SS__SSS___

vec7

Sab_

vec6

7__

VEC

VEC

1

In1g

(int517q2.eps)


Terminator1

Terminator

In1 Out1

Subsystem1

In1 Out1

Subsystem

U U(E)

Selector

0

Display

1

Constant

<c>

<g>

<g>

<signal6>

(int517q3.eps)

7.14 Signal block synthesis and virtualization (int517r)

This model tests:

• Signal inference

• Synthesis or Virtualization of Mux, Demux, Bus Creator, Bus Selector blocks.

• Virtualization simplifications.

• Virtualization loop handling.

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Switch

U U(E)

Selector

0

Display5

0

Display4

0

Display3

0

Display2

0

Display1

0

Display

Demux

Demux

Demux

5

Constant6

−C−

Constant5

−C−

Constant4

3

Constant3

1

Constant2

3

Constant1

1

Constant

<X>

<YZ>X

YZ

Z

Y

<Y>

<signal1><signal2><signal1>

(int517r.ep

s)


7.15 Name Translation Model (int517s)

A QuinetiQ example addressing signal name propagation.

0

Display9

0

Display8

0

Display7

0

Display6

0

Display5

0

Display4

0

Display3

0

Display2

0

Display13

0

Display12

0

Display11

0

Display10

0

Display1

0

Display

Demux

Demux

10

Constant9

9

Constant8

8

Constant7

7

Constant6

6

Constant5

5

Constant4

4

Constant3

3

Constant2

14

Constant13

13

Constant12

12

Constant11

11

Constant10

2

Constant1

1

Constant

<X>

Y <Y>

<signal1>

A<X>

Y <Y>

<A<X>>

<X>A

Y <Y>

<signal1>

<XA

Y <Y>

<signal1>

<Y>

<X>

Y

X <X>

<Y>

<signal1>

Y

X <X>

<Y>

<P>

Y

X P<X>

(int517s.eps)


7.16 QuintetiQ Mux Virtualization Model (int517t)

A QuinetiQ example originally showing missordering of elements in a vector display in a completelyvitualized Mux/Demux subsystem.

Merge ATMOD common data

1

COMMON

Demux

14

AT_ACQ_SET

13

FCS_DAS_HOLD_ACQD_IND

12

FCS_MACH_HOLD_ACQD_IND

11

FCS_AT_MACH_SET_IND

10

FCS_AT_DAS_SET_IND

9

AT_ENG_DISENG_TIMER

8

DATUM_SET_TIMER_BOUND_FLAG

7

DATUM_SET_TIMER

6

DATUM_ENTRY_TIMER

5

AT_FOLUP_REQUEST

4

FCC_AT_REHEAT_REQ_WRN

3

ITIMST

2

IATSEL

1

COMMON

FCSMAI (FCS_AT_MACH_SET_IND)

FCSDAI (FCS_AT_DAS_SET_IND)

FCSDAQ (FCS_DAS_HOLD_ACQD_IND)

FCSMAQ (FCS_MACH_HOLD_ACQD_IND)

IRRWRN (FCC_AT_REHEAT_REQ_WRN)

AT_ENG_DISENG_TIMER

IFOLUP (AT_FOLUP_REQUEST)

ITIMST

IATSEL


DATUM_SET_TIMER

DATUM_ENTRY_TIMER

AT_ACQ_SET

FCSMAI (FCS_AT_MACH_SET_IND)

FCSDAI (FCS_AT_DAS_SET_IND)

FCSMAP (FCS_AT_MACH_PRESELCD)

FCSDAP (FCS_AT_DAS_PRESELCD)

FCSMAQ (FCS_MACH_HOLD_ACQD_IND)

FCSDAQ (FCS_DAS_HOLD_ACQD_IND)

FCSATE (FCS_AT_ENGAGE)

IDCFLG (AT_DISCON_FLAG)

ITOWRN (AT_OUT_WRN)

IRRWRN (FCC_AT_REHEAT_REQ_WRN)

IATWRN (FCC_AUTOTHROTTLE_WRN)

IFOLUP (AT_FOLUP_REQUEST)

ITIMST

IATSEL

AREFTH

THROTTLE_LEVER_ASYMMETRY

ATHRIG_OLD

ATHLEF_OLD

AT_ENG_DISENG_OLD

ATHRIG_REHEAT_REF

ATHLEF_REHEAT_REF

AT_ENG_DISENG_TIMER


DATUM_SET_TIMER

DATUM_ENTRY_TIMER

AT_WRN_TIMER

AT_REHEAT_TIMER

REHEAT_FINISHED_TIMER

AT_ACQ_SET

AT_MACH_DATUM_SET

AT_DAS_DATUM_SET

AT_DAS_MACH_PRESELCD

THROTTLE_OVERRIDE

AT_FAILURE_RESETABLE

AT_SYSTEM_FAILURE

IMMED_AT_DISENG_SIGNAL

ATMOD

(int517t.eps)


7.17 QuintetiQ Action Subsystem eg5 (int517u)

A QuinetiQ example used during the requirements negotiations for support of action subsystems.

1

Out1

<=

RelationalOperator1

<=

RelationalOperator

Merge

Merge

elseif { }In1 Out1

Medium

if { }In1 Out1

Low

u1

u2

if(u1)

elseif(u2)

else

If

else { }In1 Out1

High

4

Constant1

1

Constant

1

In1

(int517u1.eps)

1

Out1z

1

Unit DelayProduct

else { }

Action Port

1

In1

(int517u2.eps)


1

Out1

z

1

Unit Delay

if { }

Action Port

1

In1

(int517u3.eps)

1

Out1

<=

RelationalOperator

Merge

Merge

if { }In1 Out1

Low

u1

u2

if(u1)

elseif(u2)

If

elseif { }In1 Out1

High

T

z−1

Discrete−TimeIntegrator

2.5

Constant

elseif { }

Action Port

1

In1

(int517u4.eps)


1

Out1z

1

Unit DelayProduct

elseif { }

Action Port

1

In1

(int517u5.eps)

1

Out1

z

1

Unit Delay

if { }

Action Port

1

In1

(int517u6.eps)


7.18 Action Subsystem Error Checks (int517v)

u1case [ 1 ]:

case [ 2 3 ]:

switch−err4,7

u1 if(u1)

if−err4,6

In1

In2Out1

err1−5

case: { }In1 Out1

as−err3

case: { }In1 Out1

as−err2

if { }In1 Out1

as−err1

Out1

Subsystem1

Merge

Merge1

Merge

Merge

1

Constant1

1

Constant

/home/clawz/v1.1.4.rbj.030619/src/int517v.mdl

int517v

page 1/19printed 20−Jun−2003 07:17


1

Out1

if { }

Action Port

1

In1


int517v/as−err1



1

Out1

case: { }

Action Port

1

In1


int517v/as−err2



1

Out1

case: { }

Action Port

1

In1


int517v/as−err3



1

Out1

case: { }

In1 Out1

noerrrors

case: { }In2

In3Out2

err3−5

default: { }In1

In2Out1

err1,2,4

u1

case [ 1 ]:

case [ 2 3 ]:

default:

Switch Case

Merge

Merge

2

In2

1

In1


int517v/err1−5



1

Out1

else { }In1 Out1

as−err2

if { }In1

Out1

Out2

as−err1/2

Terminator1

Terminator

Merge

Merge

u1if(u1)

else

If−err4

default: { }

Action Port

2

In2

1

In1


int517v/err1−5/err1,2,4



2

Out2

1

Out1

if { }

Action Port

1

In1


int517v/err1−5/err1,2,4/as−err1//2


(int517u7.eps)


1

Out1

else { }

Action Port

1

In1


int517v/err1−5/err1,2,4/as−err2



1

Out2ActionIn2

In3Out2

err5

ActionIn2

In3Out2

err4

Merge

Merge−err3

u1if(u1)

else

If−err41

Constant

case: { }

Action Port

2

In3

1

In2


int517v/err1−5/err3−5



1

Out2

else { }In1 Out1

ias3

elseif { }In1 Out1

ias2

ActionIn1 Out1

ias1

Terminator

Merge

Merge1

Merge

Merge

u1

u2

if(u1)

elseif(u2)

elseIf−err4

Action

Action Port

2

In3

1

In2


int517v/err1−5/err3−5/err4



1

Out1

Action

Action Port

1

In1


int517v/err1−5/err3−5/err4/ias1



1

Out1

elseif { }

Action Port

1

In1





1

Out1

else { }

Action Port

1

In1





1

Out2

else { }

In1 Out1

ias4

if { }

In1 Out1

ias3

else { }

In1 Out1

ias2

Action

In1 Out1

ias1Merge

Merge−err5

u1if(u1)

else

If1

u1if(u1)

else

If

Action

Action Port

2

In3

1

In2


int517v/err1−5/err3−5/err5



1

Out1

Action

Action Port

1

In1





1

Out1

else { }

Action Port

1

In1





1

Out1

if { }

Action Port

1

In1





1

Out1

else { }

Action Port

1

In1





1

Out1

case: { }

Action Port

1

In1


int517v/err1−5/noerrrors



7.19 QuinetiQ Action Subsystems (eg1,eg3) (int517w)

Put together from QuinetiQ eg1 and eg3 examples, also illustrates what happens with enabledsubsystems.

3

Out4

2

Out3

1

Out1

Switch

Merge

Merge

NOT LogicalOperator

In1 Out1

Increment1

if { }

In1 Out1

Increment

u1

if(u1)

else

If

In1 Out1

Decrement1

else { }

In1 Out1

Decrement

4

In4

3

In3

2

In2

1

In1

(int517w1.eps)


1

Out1

1

Constant

else { }

Action Port

1

In1

(int517w2.eps)

1

Out1

1

Constant

Enable

1

In1

(int517w3.eps)

1

Out1

1

Constant

if { }

Action Port

1

In1

Y

(int517w4.eps)


1

Out1

1

Constant

Enable

1

In1

(int517w5.eps)

7.20 Digital Clock Example (digclock)

Scope

12:34

Digital ClockClock Output

Digital Clock Example (digclock.eps)

7.21 Fcn Example Model (fcn eg)

u*factor

Fcn

0

Display

3.14159

Constant

Fcn Example (fcn eg.eps)

clawz diagram translator test cases · l e m m a1 c lemma 1 ltd. lemma 1 ltd. c/o interglossa 2nd...

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