cisc 662 graduate computer architecture lecture 12 ......cisc 662 graduate computer architecture...
TRANSCRIPT
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CISC 662 Graduate ComputerArchitecture Lecture 12 -
Hardware Speculation
Michela Tauferhttp://www.cis.udel.edu/~taufer/teaching/CIS662F07
Powerpoint Lecture Notes from John Hennessy and David Patterson’s: ComputerArchitecture, 4th edition
----Additional teaching material from:
Jelena Mirkovic (U Del), John Kubiatowicz (UC Berkeley), andSoner Oender (Michigan Technological University)
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• Exploiting more ILP requires that we overcome the limitation ofcontrol dependence:– With branch prediction we allowed the processor
continue issuing instructions past a branch based on aprediction:
• Those fetched instructions do not modify the processor state.• These instructions are squashed if prediction is incorrect.
– We now allow the processor to execute theseinstructions before we know if it is ok to execute them:
• We need to correctly restore the processor state if such aninstruction should not have been executed.
• We need to pass the results from these instructions to futureinstructions as if the program is just following that path.
Hardware Based Speculation
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• Assume the processorpredicts B1 to be taken (T)and executes.
• What will happen if theprediction was wrong?
• What value of each variableshould be used if theprocessor predicts B1 and B2taken (T) and executesinstructions along the way?
Hardware Based Speculation
x < y?
A =b+cC=c-1
C=0A=0
B=b+1A=a+1
C=a
D=a+b+c….
Use d
X < z
B1
B2
T
T
N
N
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• In order to execute instructions speculatively, we needto provide means:– To roll back the values of both registers and the memory
to their correct values upon a misprediction.– To communicate speculatively calculated values to the
new uses of those values.• Both can be provided by using a simple structure
called Reorder Buffer (ROB).
Hardware Based Speculation
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• It is a simple circular array with a head and a tailpointer:– New instructions is allocated a position at the tail in
program order.– Each entry provides a location for storing the
instruction’s result.– New instructions look for the values starting from
tail – back.– When the instruction at the head complete and
becomes non-speculative the values are committedand the instruction is removed from the buffer.
Reorder Buffer
Tail Head
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• 3 fields: instr, destination, value• Reorder buffer can be operand source => more
registers like RS• Supplies operands between execution complete &
commit• Use reorder buffer number instead of reservation
station when execution completes• Once operand commits, result is put into register• As a result, its easy to undo speculated instructions
on mispredicted branches or on exceptions
Reorder Buffer
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Steps of Speculative TomasuloAlgorithm
1. Issue [get instruction from FP Op Queue]
1. Check if the reorder buffer is full.2. Check if a reservation station is available.3. Access the register file and the reorder buffer for the
current values of the source operands.4. Send the instruction, its reorder buffer slot number and
the source operands to the reservation station.
Once issued, the instruction stays in the reservationstation until it gets both operands.
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Steps of Speculative TomasuloAlgorithm
2. Execute [operate on operands (EX) ]• When both operands ready and a functional unit is
available, the instruction executes.• This step checks RAW hazards and as long as
operands are not ready, watches CDB for results.
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Steps of Speculative TomasuloAlgorithm
3. Write result [ finish execution (WB) ]– Write on Common Data Bus to all awaiting FUs
and the reorder buffer.– Mark reservation station available.
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Steps of Speculative TomasuloAlgorithm
4. Commit [ update register file with reorder result ]• When instruction reaches the head of reorder buffer• The result is present• No exceptions associated with the instruction
The instruction becomes non-speculative:• Update register file with result (or store to memory)• Remove the instruction from the reorder buffer.
A mispredicted branch flushes the reorder buffer.
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MIPS FP Unit
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Recall: Four Steps of SpeculativeTomasulo Algorithm
1. Issue — get instruction from FP Op Queue If reservation station and reorder buffer slot free, issue instr &
send operands & reorder buffer no. for destination (this stagesometimes called “dispatch”)
2. Execution — operate on operands (EX) When both operands ready then execute; if not ready, watch CDB
for result; when both in reservation station, execute; checks RAW(sometimes called “issue”)
3. Write result — finish execution (WB) Write on Common Data Bus to all awaiting FUs
& reorder buffer; mark reservation station available.4. Commit —update register with reorder result
When instr. at head of reorder buffer & result present, updateregister with result (or store to memory) and remove instr fromreorder buffer. Mispredicted branch flushes reorder buffer(sometimes called “graduation”)
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Tomasulo With Reorder Buffer
ToMemory
FP adders FP multipliers
Reservation Stations
FP OpQueue
ROB7ROB6
ROB5
ROB4
ROB3
ROB2
ROB1
Done?
Dest Dest
Oldest
Newest
from Memory
1 10+R2Dest
Reorder Buffer
Registers
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Tomasulo With Reorder Buffer
ToMemory
FP OpQueue
ROB7ROB6
ROB5
ROB4
ROB3
ROB2
ROB1
Done?
Oldest
Newest
Reorder Buffer
Registers
COB
Dest.Value
Instruction type
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Example 1
LD F6, 34(R2)LD F2, 45(R3)MULTD F0, F2, F4SUBD F8, F6, F2DIVD F10, F0, F6ADDD F6, F8, F2
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Issue Execute Write result Commit L.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6DIV.D F10, F0, F6ADD.D F6, F8, F2
Instruction status
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
Reservation stations
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
Register result status
Time =
Mult1Mult2
Busy
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Entry Busy Instruction State Destination ValueReorder buffer
Time =
123456
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Issue Execute Write result Commit L.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6DIV.D F10, F0, F6ADD.D F6, F8, F2
Instruction status
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
Reservation stations
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
Register result status
√
Time =1First load is issued
Mult1Mult2
yes Load
#1
Regs[R2] 34
Busy yes
#1
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Entry Busy Instruction State Destination ValueL.D F6, 34(R2)
Reorder buffer
Time =1First load is issued
123456
yes Issue F6
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Issue Execute Write result Commit L.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6DIV.D F10, F0, F6ADD.D F6, F8, F2
Instruction status
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
Reservation stations
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
Register result status
√
Time =2First load executesSecond load is issued
Mult1Mult2
yesyes
Load
#1
34+ Regs[R2]
Busy yes
#1
yes
√√
Load Regs[R3] #2 45
#2
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Entry Busy Instruction State Destination ValueL.D F6, 34(R2)L.D F2, 45(R3)
Reorder buffer
123456
yesyes
Execute F6Issue F2
Time =2First load executesSecond load is issued
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Issue Execute Write result Commit L.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6DIV.D F10, F0, F6ADD.D F6, F8, F2
Instruction status
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
Reservation stations
F0 … F2 … F4 … F6 … F8 … F10 … F12Reorder #
Register result status
√
Time =3First load executesSecond load executesMul is issued
Mult1Mult2
yesyes
yes
Load
#1
34+ Regs[R2]
Busy yes
#1
yes yes
√√
Load #2
#2
√
Mult Regs[F4] #2
#3
#3
45+ Regs[R3]
√
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Entry Busy Instruction State Destination ValueL.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4
Reorder buffer
123456
yesyesyes
Execute F6Execute F2
Time =3First load executesSecond load executesMul is issued
Issue F0
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Issue Execute Write result Commit L.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6DIV.D F10, F0, F6ADD.D F6, F8, F2
Instruction status
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
Reservation stations
F0 … F2 … F4 … F6 … F8 … F10 … F12Reorder #
Register result status
√
Time =4First load writes resultSecond load executesSub is issued
Mult1Mult2
yesyes
yes
#1Busy yesyes yes yes
√√
Load #2
#2
√
Mult Regs[F4] #2
#3
#3
45+ Regs[R3]
√
√
√
Sub Mem[34+ Regs[R2]]#2 #4
#4
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Entry Busy Instruction State Destination ValueL.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6
Reorder buffer
123456
yesyesyesyes
Write result F6Execute F2Stalled in issue F0
Mem[34+ Regs[R2]]
Issue F8
Time =4First load writes resultSecond load executesSub is issued
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Issue Execute Write result Commit L.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6DIV.D F10, F0, F6ADD.D F6, F8, F2
Instruction status
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
Reservation stations
F0 … F2 … F4 … F6 … F8 … F10 … F12Reorder #
Register result status
√
Time =5First load commitsSecond load writes resultDiv is issued
Mult1Mult2
yes
yesyes
Busy yes yes yes yes
√√
#2
√
Mult Regs[F4]
#3
#3
√
√
√
Sub #4
#4
√√
Mem[34+ Regs[R2]]Mem[45+ Regs[R3]]
Mem[45+ Regs[R3]]Div Mem[34+ Regs[R2]] #3 #5
√
#5
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Entry Busy Instruction State Destination ValueL.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6
Reorder buffer
123456
noyesyesyesyes
Commit F6Write result F2Stalled in issue F0
Mem[34+ Regs[R2]]
Stalled in issue F8
Time =5First load commitsSecond load writes resultDiv is issued
DIV.D F10, F0, F6 Issue F10
Mem[45+ Regs[R3]]
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Issue Execute Write result Commit L.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6DIV.D F10, F0, F6ADD.D F6, F8, F2
Instruction status
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
Reservation stations
F0 … F2 … F4 … F6 … F8 … F10 … F12Reorder #
Register result status
√
Time =6Second load commitsMul (1/10) and sub(1/2) executeAdd is issued
Mult1Mult2
yesyes
yesyes
Busy yesyes yes yes
√√ √
Mult Regs[F4]
#3
#3
√
√
√
Sub #4
#4
√√
Mem[34+ Regs[R2]]Mem[45+ Regs[R3]]
Mem[45+ Regs[R3]]Div Mem[34+ Regs[R2]] #3 #5
√
#5
√√√
√
Add Mem[45+ Regs[R3]] #4
#6
#6
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Entry Busy Instruction State Destination ValueL.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6
Reorder buffer
123456
nonoyesyesyesyes
Commit F6Commit F2Execute F0
Mem[34+ Regs[R2]]
Execute F8DIV.D F10, F0, F6 Stalled in issue F10
Time =6Second load commitsMul (1/10) and sub(1/2) executeAdd is issued
Mem[45+ Regs[R3]]
ADD.D F6, F8, F2 Issue F6
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Issue Execute Write result Commit L.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6DIV.D F10, F0, F6ADD.D F6, F8, F2
Instruction status
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
Reservation stations
F0 … F2 … F4 … F6 … F8 … F10 … F12Reorder #
Register result status
√
Time =7Second load commitsMul (2/10) and sub(2/2) execute
Mult1Mult2
yesyes
yesyes
Busy yesyes yes yes
√√ √
Mult Regs[F4]
#3
#3
√
√
√
Sub #4
#4
√√
Mem[34+ Regs[R2]]Mem[45+ Regs[R3]]
Mem[45+ Regs[R3]]Div Mem[34+ Regs[R2]] #3 #5
√
#5
√√√
√
Add Mem[45+ Regs[R3]] #4
#6
#6
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Entry Busy Instruction State Destination ValueL.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6
Reorder buffer
123456
nonoyesyesyesyes
Commit F6Commit F2Execute F0Execute F8
DIV.D F10, F0, F6 Stalled in issue F10
Time =7Second load commitsMul (2/10) and sub(2/2) executeAdd is issued
ADD.D F6, F8, F2 Issue F6
Mem[34+ Regs[R2]]Mem[45+ Regs[R3]]
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Issue Execute Write result Commit L.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6DIV.D F10, F0, F6ADD.D F6, F8, F2
Instruction status
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
Reservation stations
F0 … F2 … F4 … F6 … F8 … F10 … F12Reorder #
Register result status
√
Time =8Mul executes (3/10)Sub writes result (X)
Mult1Mult2
yes
yesyes
Busy yesyes yes yes
√√ √
Mult Regs[F4]
#3
#3
√
√
√
√√
Mem[45+ Regs[R3]]Div Mem[34+ Regs[R2]] #3 #5
√
#5
√√√
√
Add Mem[45+ Regs[R3]]X
#6
#6
√
#4
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Entry Busy Instruction State Destination ValueL.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6
Reorder buffer
123456
nonoyesyesyesyes
Commit F6Commit F2Execute F0Write result F8
DIV.D F10, F0, F6 Stalled in issue F10ADD.D F6, F8, F2 Stalled in issue F6
Time =8Mul executes (3/10)Sub writes result (X)
X
Mem[34+ Regs[R2]]Mem[45+ Regs[R3]]
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Issue Execute Write result Commit L.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6DIV.D F10, F0, F6ADD.D F6, F8, F2
Instruction status
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
Reservation stations
F0 … F2 … F4 … F6 … F8 … F10 … F12Reorder #
Register result status
√
Time =9Mul executes (4/10)Add executes(1/2)
Mult1Mult2
yes
yesyes
Busy yesyes yes yes
√√ √
Mult Regs[F4]
#3
#3
√
√
√
√√
Mem[45+ Regs[R3]]Div Mem[34+ Regs[R2]] #3 #5
√
#5
√√√
√
Add Mem[45+ Regs[R3]]X
#6
#6
√
√
#4
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Entry Busy Instruction State Destination ValueL.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6
Reorder buffer
123456
nonoyesyesyesyes
Commit F6Commit F2Execute F0Waiting to commit F8
DIV.D F10, F0, F6 Stalled in issue F10ADD.D F6, F8, F2 Execute F6
X
Time =9Mul executes (4/10)Add executes(1/2)
Mem[34+ Regs[R2]]Mem[45+ Regs[R3]]
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Issue Execute Write result Commit L.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6DIV.D F10, F0, F6ADD.D F6, F8, F2
Instruction status
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
Reservation stations
F0 … F2 … F4 … F6 … F8 … F10 … F12Reorder #
Register result status
√
Time =10Mul executes (5/10)Add executes(2/2)
Mult1Mult2
yes
yesyes
Busy yesyes yes yes
√√ √
Mult Regs[F4]
#3
#3
√
√
√
√√
Mem[45+ Regs[R3]]Div Mem[34+ Regs[R2]] #3 #5
√
#5
√√√
√
Add Mem[45+ Regs[R3]]X
#6
#6
√
√
#4
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Entry Busy Instruction State Destination ValueL.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6
Reorder buffer
123456
nonoyesyesyesyes
Commit F6Commit F2Execute F0Waiting to commit F8
DIV.D F10, F0, F6 Stalled in issue F10ADD.D F6, F8, F2 Execute F6
X
Time =10Mul executes (5/10)Add executes(2/2)
Mem[34+ Regs[R2]]Mem[45+ Regs[R3]]
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Issue Execute Write result Commit L.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6DIV.D F10, F0, F6ADD.D F6, F8, F2
Instruction status
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
Reservation stations
F0 … F2 … F4 … F6 … F8 … F10 … F12Reorder #
Register result status
√
Time =11Mul executes (6/10)Add writes result (Y)
Mult1Mult2
yesyes
Busy yesyes yes yes
√√ √
Mult Regs[F4]
#3
#3
√
√
√
√√
Mem[45+ Regs[R3]]Div Mem[34+ Regs[R2]] #3 #5
√
#5
√√√
√
√
√ √
#4#6
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Entry Busy Instruction State Destination ValueL.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6
Reorder buffer
123456
nonoyesyesyesyes
Commit F6Commit F2Execute F0Waiting to commit F8
DIV.D F10, F0, F6 Stalled in issue F10ADD.D F6, F8, F2 Write result F6
X
Time =11Mul executes (6/10)Add writes result (Y)
Y
Mem[34+ Regs[R2]]Mem[45+ Regs[R3]]
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Faster than light computation(skip a couple of cycles)
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Faster than light computation(skip a couple of cycles)
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Issue Execute Write result Commit L.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6DIV.D F10, F0, F6ADD.D F6, F8, F2
Instruction status
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
Reservation stations
F0 … F2 … F4 … F6 … F8 … F10 … F12Reorder #
Register result status
√
Time =16Mul writes result (Z)
Mult1Mult2 yes
Busy yesyes yes yes
√√ √√
√
√
√√
Div Mem[34+ Regs[R2]]Z #5
√
#5
√√√
√
√
√ √
√
#3 #4#6
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Entry Busy Instruction State Destination ValueL.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6
Reorder buffer
123456
nonoyesyesyesyes
Commit F6Commit F2Write result F0Waiting to commit F8
DIV.D F10, F0, F6 Stalled in issue F10ADD.D F6, F8, F2 Waiting to commit F6
X
Y
Time =16Mul writes result (Z)
Z
Mem[34+ Regs[R2]]Mem[45+ Regs[R3]]
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Issue Execute Write result Commit L.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6DIV.D F10, F0, F6ADD.D F6, F8, F2
Instruction status
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
Reservation stations
F0 … F2 … F4 … F6 … F8 … F10 … F12Reorder #
Register result status
√
Time =17Mul commitsDiv is executed (1/40)
Mult1Mult2 yes
Busy yes yes yes
√√ √√
√
√
√√
Div Mem[34+ Regs[R2]]Z #5
√
#5
√√√
√
√
√ √
√
√
√
#4#6
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Entry Busy Instruction State Destination ValueL.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6
Reorder buffer
123456
nononoyesyesyes
Commit F6Commit F2Commit F0Waiting to commit F8
DIV.D F10, F0, F6 Execute F10ADD.D F6, F8, F2 Waiting to commit F6
X
Y
Z
Time =17Mul commitsDiv is executed (1/40)
Mem[34+ Regs[R2]]Mem[45+ Regs[R3]]
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Issue Execute Write result Commit L.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6DIV.D F10, F0, F6ADD.D F6, F8, F2
Instruction status
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
Reservation stations
F0 … F2 … F4 … F6 … F8 … F10 … F12Reorder #
Register result status
√
Time =18Sub commitsDiv is executed (2/40)
Mult1Mult2 yes
Busy yes yes
√√ √√
√
√
√√
Div Mem[34+ Regs[R2]]Z #5
√
#5
√√√
√
√
√ √
√
√
√
#6
√
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Entry Busy Instruction State Destination ValueL.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6
Reorder buffer
123456
nonononoyesyes
Commit F6Commit F2Commit F0Commit F8
DIV.D F10, F0, F6 Execute F10ADD.D F6, F8, F2 Waiting to commit F6
X
Y
Z
Time =18Sub commitsDiv is executed (2/40)
Mem[34+ Regs[R2]]Mem[45+ Regs[R3]]
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Faster than light computation(skip a couple of cycles)
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Faster than light computation(skip a couple of cycles)
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Issue Execute Write result Commit L.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6DIV.D F10, F0, F6ADD.D F6, F8, F2
Instruction status
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
Reservation stations
F0 … F2 … F4 … F6 … F8 … F10 … F12Reorder #
Register result status
√
Time =57Div writes result (W)
Mult1Mult2
Busy yes yes
√√ √√
√
√
√√
√
#5
√√√
√
√
√ √
√
√
√
#6
√√
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Entry Busy Instruction State Destination ValueL.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6
Reorder buffer
123456
nonononoyesyes
Commit F6Commit F2Commit F0Commit F8
DIV.D F10, F0, F6 Write result F10ADD.D F6, F8, F2 Waiting to commit F6
X
Y
Z
Time =57Div writes result (W)
W
Mem[34+ Regs[R2]]Mem[45+ Regs[R3]]
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Issue Execute Write result Commit L.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6DIV.D F10, F0, F6ADD.D F6, F8, F2
Instruction status
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
Reservation stations
F0 … F2 … F4 … F6 … F8 … F10 … F12Reorder #
Register result status
√
Time =58Div commits
Mult1Mult2
Busy yes
√√ √√
√
√
√√
√
√√√
√
√
√ √
√
√
√
#6
√√ √
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Entry Busy Instruction State Destination ValueL.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6
Reorder buffer
123456
nononononoyes
Commit F6Commit F2Commit F0Commit F8
DIV.D F10, F0, F6 Commit F10ADD.D F6, F8, F2 Waiting to commit F6
X
Y
Z
W
Time =58Div commits
Mem[34+ Regs[R2]]Mem[45+ Regs[R3]]
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Issue Execute Write result Commit L.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6DIV.D F10, F0, F6ADD.D F6, F8, F2
Instruction status
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
Reservation stations
F0 … F2 … F4 … F6 … F8 … F10 … F12Reorder #
Register result status
√
Time =59Add commits
Mult1Mult2
Busy
√√ √√
√
√
√√
√
√√√
√
√
√ √
√
√
√√
√ √√
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Entry Busy Instruction State Destination ValueL.D F6, 34(R2)L.D F2, 45(R3)MUL.D F0, F2, F4SUB.D F8, F2, F6
Reorder buffer
123456
nononononono
Commit F6Commit F2Commit F0Commit F8
DIV.D F10, F0, F6 Commit F10ADD.D F6, F8, F2 Commit F6
X
Y
Z
W
Time =59Add commits
Mem[34+ Regs[R2]]Mem[45+ Regs[R3]]
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Example 2
Loop: LD F0, 0(R1)MULTD F4, F0, F2SD F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
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Issue Execute Write result Commit
Load1Load2Add1Add2Add3
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
√
Time =1Load is issued
Mult1Mult2
yes
Busy yes
L.D F0, 0(R1)MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
L.D F0, 0(R1)
Load Regs[R1] 0#1
#1
Store1Store2
Busy Op Vj Vk Qj Qk Dest A
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Entry Busy Instruction State Destination ValueReorder buffer
123456
yes Issue F0
Time =1Load is issued
8910
7
L.D F0, 0(R1)
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Issue Execute Write result Commit
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
√
Time =2Load executes, MUL is issued
Mult1Mult2
yes
yes
Busy yes
L.D F0, 0(R1)MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
L.D F0, 0(R1)
0+Regs[R1]#1
#1
Store1Store2
√√
Load
Mul #2#1Regs[R2]
#2yes
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Entry Busy Instruction State Destination ValueReorder buffer
123456
yesyes Issue
F0
8910
7
L.D F0, 0(R1)
Time =2Load executes, MUL is issued
MUL.D F4, F0, F2Execute
F4
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Issue Execute Write result Commit
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
√
Time =3Load executes, MUL is stalledStore is issued
Mult1Mult2
yes
yes
Busy yes
L.D F0, 0(R1)MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
L.D F0, 0(R1)
0+Regs[R1]#1
#1
Store1 yesStore2
√√
Load
Mul #2#1Regs[R2]
#2yes
√
Store Regs[R1] 0#3#2
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Entry Busy Instruction State Destination ValueReorder buffer
123456
yesyesyes
Stalled in issueF0
8910
7
L.D F0, 0(R1)MUL.D F4, F0, F2
ExecuteF4
Time =3Load executes, MUL is stalledStore is issued
S.D F4, 0(R1) Issue
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Issue Execute Write result Commit
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
√
Time =4Load writes result (X), store executes (addr.calc)DADDIU is issued
Mult1Mult2
yes
yes
Busy
L.D F0, 0(R1)MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
L.D F0, 0(R1)
Store1 yesStore2
√√
Mul #2X Regs[R2]
#2yes
√
Store #3#2
√
√√
Add Regs[R1] -8
0+Regs[R1]
yes#1
#4
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Entry Busy Instruction State Destination ValueReorder buffer
123456
yesyesyesyes
Stalled in issueF0
8910
7
L.D F0, 0(R1)MUL.D F4, F0, F2
Write resultF4
S.D F4, 0(R1) Execute
Time =4Load writes result (X), store executes (addr.calc)DADDIU is issued
X
DADDIU R1, R1, #-8 Issue R1Mem[0+Regs[R1]]
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Issue Execute Write result Commit
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
√
Time =5Load commits, store is stalled, MUL executes(1/10)DADDIU executes, BNE is issued
Mult1Mult2
yesyes
yes
Busy
L.D F0, 0(R1)MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
L.D F0, 0(R1)
Store1 yesStore2
√√
Mul #2X Regs[R2]
#2yes
√
Store #3#2
√
√√
Add Regs[R1] -8
0+Regs[R1]
√
√
√
√
#4Branch Loop#5Regs[R2] #4
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Entry Busy Instruction State Destination ValueReorder buffer
123456
noyesyesyesyes
ExecuteF0
8910
7
L.D F0, 0(R1)MUL.D F4, F0, F2
CommitF4
S.D F4, 0(R1) Stalled in execute
X
DADDIU R1, R1, #-8 Execute R1
Time =5Load commits, store is stalled, MUL executes(1/10)DADDIU executes, BNE is issued
BNE R1, R2, Loop
Mem[0+Regs[R1]]
Issue
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Issue Execute Write result Commit
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
√
Time =6Store and BNE are stalled, MUL executes(2/10)DADDIU writes result (Y) Load is issued
Mult1Mult2
yes
yes
yes
Busy
L.D F0, 0(R1)MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
L.D F0, 0(R1)
Store1 yesStore2
√√
Mul #2X Regs[R2]
#2yes
√
Store #3#2
√
√√
0+Regs[R1]
√
√
√
√
Branch Loop#5Regs[R2]
√
√
Load Y 0
Y
#6
#6yes
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Entry Busy Instruction State Destination ValueReorder buffer
123456
noyesyesyesyesyes
ExecuteF0
8910
7
L.D F0, 0(R1)MUL.D F4, F0, F2
CommitF4
S.D F4, 0(R1) Stalled in execute
X
DADDIU R1, R1, #-8 Write result R1BNE R1, R2, Loop
Mem[0+Regs[R1]]
Stalled in issue
Time =6Store and BNE are stalled, MUL executes(2/10)DADDIU writes result (Y) Load is issued
F0L.D F0, 0(R1) Issue
Y
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Issue Execute Write result Commit
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
√
Time =7Store is stalled, MUL executes(3/10), BNE and load executeMUL is issued
Mult1Mult2
yes
yes
yesyes
Busy
L.D F0, 0(R1)MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
L.D F0, 0(R1)
Store1 yesStore2
√√
Mul #2X Regs[R2]
#7yes
√
Store #3#2
√
√√
0+Regs[R1]
√
√
√
√
Branch Loop#5Regs[R2]
√
√
Load 0+Y
Y
#6
#6yes
√√
√
Mul Regs[R2] #6 #7
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Entry Busy Instruction State Destination ValueReorder buffer
123456
noyesyesyesyesyes
ExecuteF0
8910
7 yes
L.D F0, 0(R1)MUL.D F4, F0, F2
CommitF4
S.D F4, 0(R1) Stalled in execute
X
DADDIU R1, R1, #-8 Waiting to commit R1BNE R1, R2, Loop
Mem[0+Regs[R1]]
ExecuteF0L.D F0, 0(R1) Execute
Y
Time =7Store is stalled, MUL executes(3/10), BNE and load executeMUL is issued
IssueMUL.D F4, F0, F2 F4
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Issue Execute Write result Commit
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
√
Time = 8Store is stalled, MUL executes(4/10), BNE writes result, load executesMUL is stalled, store is issued
Mult1Mult2
yes
yesyes
Busy
L.D F0, 0(R1)MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
L.D F0, 0(R1)
Store1 yesStore2 yes
√√
Mul #2X Regs[R2]
#7yes
√
Store #3#2
√
√√
0+Regs[R1]
√
√
√
√
√
√
Load 0+Y#6
#6yes
√√
√
Mul Regs[R2] #6 #7
√
√
Store Regs[R1] 0#8#7
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Entry Busy Instruction State Destination ValueReorder buffer
123456
noyesyesyesyesyes
ExecuteF0
8910
yes7 yes
L.D F0, 0(R1)MUL.D F4, F0, F2
CommitF4
S.D F4, 0(R1) Stalled in execute
X
DADDIU R1, R1, #-8 Waiting to commit R1BNE R1, R2, Loop
Mem[0+Regs[R1]]
Write resultF0L.D F0, 0(R1) Execute
Y
Stalled in issueMUL.D F4, F0, F2 F4
Time = 8Store is stalled, MUL executes(4/10), BNE writes result, load executesMUL is stalled, store is issued
S.D F4, 0(R1) Issue
Not taken
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Issue Execute Write result Commit
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
√
Time = 9Store is stalled, MUL executes(5/10), Load writes result (Z), Store executes (addr.calc)DADDIU is issued
Mult1Mult2
yes
yesyes
Busy
L.D F0, 0(R1)MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
L.D F0, 0(R1)
Store1 yesStore2 yes
√√
Mul #2X Regs[R2]
#7yes
√
Store #3#2
√
√√
0+Regs[R1]
√
√
√
√
√
√
#6yes
√√
√
Mul Regs[R2]Z #7
√
√
Store Regs[R1] #8#7
√
√√
Add Regs[R1] -8 #9
0+Regs[R1]
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Entry Busy Instruction State Destination ValueReorder buffer
123456
noyesyesyesyesyes
ExecuteF0
8910
yesyes
7 yes
L.D F0, 0(R1)MUL.D F4, F0, F2
CommitF4
S.D F4, 0(R1) Stalled in execute
X
DADDIU R1, R1, #-8 Waiting to commit R1BNE R1, R2, Loop
Mem[0+Regs[R1]]
Waiting to commitF0L.D F0, 0(R1) Write result
Y
Stalled in issueMUL.D F4, F0, F2 F4S.D F4, 0(R1) Execute
Not taken
Time = 9Store is stalled, MUL executes(5/10), Load writes result (Z), Store executes (addr.calc)DADDIU is issued
Z
Mem[0+Regs[R1]]DADDIU R1, R1, #-8 Issue R1
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Issue Execute Write result Commit
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
√
Time = 10MUL executes(6/10), Store is stalled, DADDIU executes, BNE issuesMUL executes (1/10)
Mult1Mult2
yesyes
yesyes
Busy
L.D F0, 0(R1)MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
L.D F0, 0(R1)
Store1 yesStore2 yes
√√
Mul #2X Regs[R2]
#7yes
√
Store #3#2
√
√√
0+Regs[R1]
√
√
√
√
√
√
#6yes
√√
√
Mul Regs[R2]Z #7
√
√
Store Regs[R1] #8#7
√
√√
Add Regs[R1] -8 #9
0+Regs[R1]
√√
Branch Loop#10Regs[R2] #9
√
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Entry Busy Instruction State Destination ValueReorder buffer
123456
noyesyesyesyesyes
ExecuteF0
8910
yesyesyes
7 yes
L.D F0, 0(R1)MUL.D F4, F0, F2
CommitF4
S.D F4, 0(R1) Stalled in execute
X
DADDIU R1, R1, #-8 Waiting to commit R1BNE R1, R2, Loop
Mem[0+Regs[R1]]
Waiting to commitF0L.D F0, 0(R1) Waiting to commit
Y
ExecuteMUL.D F4, F0, F2 F4S.D F4, 0(R1) Stalled in execute
Not takenZ
Mem[0+Regs[R1]]DADDIU R1, R1, #-8 Execute R1
Time = 10MUL executes(6/10), Store is stalled, DADDIU executes, BNE issues
BNE R1, R2, Loop Issue
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Issue Execute Write result Commit
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
√
Time = 11MUL executes(7/10), DADDIU writes result (W), BNE stalledMUL executes (2/10)
Mult1Mult2
yes
yesyes
Busy
L.D F0, 0(R1)MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
L.D F0, 0(R1)
Store1 yesStore2 yes
√√
Mul #2X Regs[R2]
#7yes
√
Store #3#2
√
√√
0+Regs[R1]
√
√
√
√
√
√
#6yes
√√
√
Mul Regs[R2]Z #7
√
√
Store Regs[R1] #8#7
√
√√
0+Regs[R1]
√√
Branch Loop#10Regs[R2]W
√
√
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Entry Busy Instruction State Destination ValueReorder buffer
123456
noyesyesyesyesyes
ExecuteF0
8910
yesyesyes
7 yes
L.D F0, 0(R1)MUL.D F4, F0, F2
CommitF4
S.D F4, 0(R1) Stalled in execute
X
DADDIU R1, R1, #-8 Waiting to commit R1BNE R1, R2, Loop
Mem[0+Regs[R1]]
Waiting to commitF0L.D F0, 0(R1) Waiting to commit
Y
ExecuteMUL.D F4, F0, F2 F4S.D F4, 0(R1) Stalled in execute
Not takenZ
Mem[0+Regs[R1]]DADDIU R1, R1, #-8 Write result R1BNE R1, R2, Loop Stalled in issue
Time = 11MUL executes(7/10), DADDIU writes result (W), BNE stalledMUL executes (2/10)
W
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Issue Execute Write result Commit
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
√
Time = 12MUL executes(8/10), BNE executesMUL executes (3/10)
Mult1Mult2
yes
yesyes
Busy
L.D F0, 0(R1)MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
L.D F0, 0(R1)
Store1 yesStore2 yes
√√
Mul #2X Regs[R2]
#7yes
√
Store #3#2
√
√√
0+Regs[R1]
√
√
√
√
√
√
#6yes
√√
√
Mul Regs[R2]Z #7
√
√
Store Regs[R1] #8#7
√
√√
0+Regs[R1]
√√
Branch Loop#10Regs[R2]W
√
√
√
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Entry Busy Instruction State Destination ValueReorder buffer
123456
noyesyesyesyesyes
ExecuteF0
8910
yesyesyes
7 yes
L.D F0, 0(R1)MUL.D F4, F0, F2
CommitF4
S.D F4, 0(R1) Stalled in execute
X
DADDIU R1, R1, #-8 Waiting to commit R1BNE R1, R2, Loop
Mem[0+Regs[R1]]
Waiting to commitF0L.D F0, 0(R1) Waiting to commit
Y
ExecuteMUL.D F4, F0, F2 F4S.D F4, 0(R1) Stalled in execute
Not takenZ
Mem[0+Regs[R1]]DADDIU R1, R1, #-8 Waiting to commit R1BNE R1, R2, Loop Execute
W
Time = 12MUL executes(8/10), BNE executesMUL executes (3/10)
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Issue Execute Write result Commit
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
√
Time = 13MUL executes(9/10), BNE writes result, MUL executes (4/10)
Mult1Mult2
yesyes
Busy
L.D F0, 0(R1)MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
L.D F0, 0(R1)
Store1 yesStore2 yes
√√
Mul #2X Regs[R2]
#7yes
√
Store #3#2
√
√√
0+Regs[R1]
√
√
√
√
√
√
#6yes
√√
√
Mul Regs[R2]Z #7
√
√
Store Regs[R1] #8#7
√
√√
0+Regs[R1]
√√√
√
√√
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Entry Busy Instruction State Destination ValueReorder buffer
123456
noyesyesyesyesyes
ExecuteF0
8910
yesyesyes
7 yes
L.D F0, 0(R1)MUL.D F4, F0, F2
CommitF4
S.D F4, 0(R1) Stalled in execute
X
DADDIU R1, R1, #-8 Waiting to commit R1BNE R1, R2, Loop
Mem[0+Regs[R1]]
Waiting to commitF0L.D F0, 0(R1) Waiting to commit
Y
ExecuteMUL.D F4, F0, F2 F4S.D F4, 0(R1) Stalled in execute
Not takenZ
Mem[0+Regs[R1]]DADDIU R1, R1, #-8 Waiting to commit R1BNE R1, R2, Loop Write result
W
Time = 13MUL executes(9/10), BNE writes result, MUL executes (4/10)
Not taken
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Issue Execute Write result Commit
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
√
Time = 14MUL executes(10/10), MUL executes (5/10)
Mult1Mult2
yesyes
Busy
L.D F0, 0(R1)MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
L.D F0, 0(R1)
Store1 yesStore2 yes
√√
Mul #2X Regs[R2]
#7yes
√
Store #3#2
√
√√
0+Regs[R1]
√
√
√
√
√
√
#6yes
√√
√
Mul Regs[R2]Z #7
√
√
Store Regs[R1] #8#7
√
√√
0+Regs[R1]
√√√
√
√√
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Entry Busy Instruction State Destination ValueReorder buffer
123456
noyesyesyesyesyes
ExecuteF0
8910
yesyesyes
7 yes
L.D F0, 0(R1)MUL.D F4, F0, F2
CommitF4
S.D F4, 0(R1) Stalled in execute
X
DADDIU R1, R1, #-8 Waiting to commit R1BNE R1, R2, Loop
Mem[0+Regs[R1]]
Waiting to commitF0L.D F0, 0(R1) Waiting to commit
Y
ExecuteMUL.D F4, F0, F2 F4S.D F4, 0(R1) Stalled in execute
Not takenZ
Mem[0+Regs[R1]]DADDIU R1, R1, #-8 Waiting to commit R1BNE R1, R2, Loop Waiting to commit
WNot taken
Time = 14MUL executes(10/10), MUL executes (5/10)
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Issue Execute Write result Commit
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
√
Time = 15MUL writes result (A) MUL executes (6/10)
Mult1Mult2 yes
Busy
L.D F0, 0(R1)MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
L.D F0, 0(R1)
Store1 yesStore2 yes
√√
#7yes
√
Store #3A
√
√√
0+Regs[R1]
√
√
√
√
√
√
#6yes
√√
√
Mul Regs[R2]Z #7
√
√
Store Regs[R1] #8#7
√
√√
0+Regs[R1]
√√√
√
√√
√
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Entry Busy Instruction State Destination ValueReorder buffer
123456
noyesyesyesyesyes
Write resultF0
8910
yesyesyes
7 yes
L.D F0, 0(R1)MUL.D F4, F0, F2
CommitF4
S.D F4, 0(R1) Stalled in execute
X
DADDIU R1, R1, #-8 Waiting to commit R1BNE R1, R2, Loop
Mem[0+Regs[R1]]
Waiting to commitF0L.D F0, 0(R1) Waiting to commit
Y
ExecuteMUL.D F4, F0, F2 F4S.D F4, 0(R1) Stalled in execute
Not takenZ
Mem[0+Regs[R1]]DADDIU R1, R1, #-8 Waiting to commit R1BNE R1, R2, Loop Waiting to commit
WNot taken
Time = 15MUL writes result (A) MUL executes (6/10)
A
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Issue Execute Write result Commit
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
√
Time = 16MUL commits, store writes result MUL executes (7/10)
Mult1Mult2 yes
Busy
L.D F0, 0(R1)MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
L.D F0, 0(R1)
Store1Store2 yes
√√
#7yes
√
√
√√
√
√
√
√
√
√
#6yes
√√
√
Mul Regs[R2]Z #7
√
√
Store Regs[R1] #8#7
√
√√
0+Regs[R1]
√√√
√
√√
√ √√
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Entry Busy Instruction State Destination ValueReorder buffer
123456
nonoyesyesyesyes
CommitF0
8910
yesyesyes
7 yes
L.D F0, 0(R1)MUL.D F4, F0, F2
CommitF4
S.D F4, 0(R1) Write result
X
DADDIU R1, R1, #-8 Waiting to commit R1BNE R1, R2, Loop
Mem[0+Regs[R1]]
Waiting to commitF0L.D F0, 0(R1) Waiting to commit
Y
ExecuteMUL.D F4, F0, F2 F4S.D F4, 0(R1) Stalled in execute
Not takenZ
Mem[0+Regs[R1]]DADDIU R1, R1, #-8 Waiting to commit R1BNE R1, R2, Loop Waiting to commit
WNot taken
A
Time = 16MUL commits, store writes result MUL executes (7/10)
A
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Issue Execute Write result Commit
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
√
Time = 17Store commits MUL executes (8/10)
Mult1Mult2 yes
Busy
L.D F0, 0(R1)MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
L.D F0, 0(R1)
Store1Store2 yes
√√
#7yes
√
√
√√
√
√
√
√
√
√
#6yes
√√
√
Mul Regs[R2]Z #7
√
√
Store Regs[R1] #8#7
√
√√
0+Regs[R1]
√√√
√
√√
√ √√ √
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Entry Busy Instruction State Destination ValueReorder buffer
123456
nononoyesyesyes
CommitF0
8910
yesyesyes
7 yes
L.D F0, 0(R1)MUL.D F4, F0, F2
CommitF4
S.D F4, 0(R1) Commit
X
DADDIU R1, R1, #-8 Waiting to commit R1BNE R1, R2, Loop
Mem[0+Regs[R1]]
Waiting to commitF0L.D F0, 0(R1) Waiting to commit
Y
ExecuteMUL.D F4, F0, F2 F4S.D F4, 0(R1) Stalled in execute
Not takenZ
Mem[0+Regs[R1]]DADDIU R1, R1, #-8 Waiting to commit R1BNE R1, R2, Loop Waiting to commit
WNot taken
AA
Time = 17Store commits MUL executes (8/10)
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Issue Execute Write result Commit
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
√
Time = 18DADDIU commitsMUL executes (9/10)
Mult1Mult2 yes
Busy
L.D F0, 0(R1)MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
L.D F0, 0(R1)
Store1Store2 yes
√√
#7yes
√
√
√√
√
√
√
√
√
√
#6yes
√√
√
Mul Regs[R2]Z #7
√
√
Store Regs[R1] #8#7
√
√√
0+Regs[R1]
√√√
√
√√
√ √√ √
√
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Entry Busy Instruction State Destination ValueReorder buffer
123456
nonononoyesyes
CommitF0
8910
yesyesyes
7 yes
L.D F0, 0(R1)MUL.D F4, F0, F2
CommitF4
S.D F4, 0(R1) Commit
X
DADDIU R1, R1, #-8 Commit R1BNE R1, R2, Loop
Mem[0+Regs[R1]]
Waiting to commitF0L.D F0, 0(R1) Waiting to commit
Y
ExecuteMUL.D F4, F0, F2 F4S.D F4, 0(R1) Stalled in execute
Not takenZ
Mem[0+Regs[R1]]DADDIU R1, R1, #-8 Waiting to commit R1BNE R1, R2, Loop Waiting to commit
WNot taken
AA
Time = 18DADDIU commitsMUL executes (9/10)
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Issue Execute Write result Commit
Busy Op Vj Vk Qj Qk Dest ALoad1Load2Add1Add2Add3
F0 … F2 … F4 … F6 … F8 … F10 … F12
Reorder #
√
Time = 19Branch commits, everything is flushed
Mult1Mult2
Busy
L.D F0, 0(R1)MUL.D F4, F0, F2S.D F4, 0(R1)DADDIU R1, R1, #-8BNE R1, R2, Loop
Store1Store2
√√√
√
√√
√
√
√
√
√√ √
√ √√ √
√√
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Entry Busy Instruction State Destination ValueReorder buffer
123456
nonononono
CommitF0
8910
7
L.D F0, 0(R1)MUL.D F4, F0, F2
CommitF4
S.D F4, 0(R1) Commit
X
DADDIU R1, R1, #-8 Commit R1BNE R1, R2, Loop
Mem[0+Regs[R1]]
CommitYNot taken
AA
Time = 19Branch commits, everything is flushed
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Exceptions
• Exceptions are handled by not recognizing theexception until it is ready to commit
• Exceptions raised during e.g., execution are stored inROB
• Exceptions are flushed with the related instruction, ifthe instruction does not need to be executed, e.g.,due to branch misprediction
• Speculation adds significant complication to thecontrol
• Branch mispredictions are more complex
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Memory Hazards
• WAW and WAR hazards are avoided by in-ordercompletion– A store is committed at the head of the ROB and
therefore no earlier loads or stores are still pending• RAW hazard is prevent by ensuring that a load that
accesses a memory location written to by an earlierstore cannot perform the memory access until thestore has written the data
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Deadlines7 Oct 14 Lec10 - Dynamic Scheduling: Tomasulo
7 Oct 16 Lec11 - Hardware Speculation
Oct 20 Homework 2 due
8 Oct 21 Homework review
8 Oct 23 Midterm exam Chap 3; App C
9 Oct 28 Lec12 - Multiple Issue
9 Oct 30 Lec13 - Study of the Limitations of ILP Q4
10 Nov 4 Election day – no class
10 Nov 6 Lec14 - Review Cache and Review Virtual
Memory
Chap 4
11 Nov 10 Homework 3 d u e
11 Nov 11 Lec15 - Multiprocessors and Thread-Level
Parallelism; Symmetric Shared Memory
Q 5
11 Nov 13 Lec16 - Distributed Shared Memory
Nov 17 Homework 4 due
12 Nov 18 Lec18 – Homework 3 review Chap 5
12 Nov 20 Lec19 – Homework 4 review
13 Nov 25 Lec17 - Synchronization Q6
13 Nov 27 Thanksgiving – Holiday
14 Dec 2 Lec20 Cache Performance
14 Nov 4 Lec21 - Memory Technology; Virtual Memory
and Virtual Machine
15 Dec 9 Lec22 - Design of Memory Hierarchy