CISC Scalar ProcessorsA scalar processor executes with scalar data. The simplest scalar processor executes integer instructions using fixed-point operands. More capable scalar processors execute both integer and floating-point operations. A modern scalar processor may possess both an integer unit and a floating-point unit. Based on a complex instruction set, a CISC scalar processor can be built either with a single chip or with multiple chips mounted on a processor board. Three representative CISC scalar processors are listed. The VAX 8600 processor is built on a PC board. The i486 and M68040 are single-chip microprocessors. They are still widely used at present. We use these popular architectures to explain some interesting features built into modern CISC machines. Lets discuss one of its implementations...

THE VAX 8600 CISC PROCESSOR KEY FEATURES Developed by Digital Equipment Corporation (DEC) in 1985 A 32-bit CISC instruction set A commercial pioneer in using virtual address 4 GB Vitrual Memory Space Replaced 16-bit PDP-11 ISA 15 20 year architecture life span Runs on VMS operating system 16 32-bit registers (r0, r1, .., r15) 300+ variable length instructions 22 addressing modes

VAX 8600 CPU ARCHITECTURE [DEC , 1985]

FIGURE 1: VAX 8600 CPU DESIGN

EXECUTION UNIT- In charge of the overall execution of the machine and under exceptional cases explicitly controls the other functional units. It contains most of the micro code of all the complex instructions. There are 256 registers present each of which are of 32 bits , of which one half correspond to GPRS , temporary registers and internal processor registers. The other half relates to storing of constants. INSTRUCTION UNIT In charge of prefetching and decoding instructions , handles branching operations and supplies operands to the fuctional units in pipelined manner . CACHE It is of 16K Bytes , has virtual address space for data as well as instructions . MEMORY & I/O CONTROL UNIT It performs memory accesses as requested by Instruction unit and Execution Unit . It also has the Translation Lookaside Buffer used for fast generation of physical address from virtual memory address .

The CPI ranges from 2 cycles to 20 cycles. For eg. multiply and divide may tie up an execution unit for a large no. of cycles . This occurs due to large no. of microinstuction sequences to control hardware operations .

FIGURE 2 :VAX 8600 BLOCK DIGRAM

The VAX 8600, shown here during assembly, offered up to 4.2 times the performance of the industry standard VAX-11/780 and increased I/O capacity, while maintaining I/O subsystem compatibility with the VAX-11/780 and the 11/785 Synchronous Backplane Interconnect (SBI). The VAX 8600 was the first VAX implementation in ECL technology and the first to include macropipelining.

8600 Microarchitecture:All of the boxes are microprogrammed independently. Most of the microcode, including all instruction specific microcode, is contained in the EBOX. The IBOX and MBOX perform the duties of instruction prefetching, operand prefetching, and memory accesses. The EBOX (EXECUTION UNIT) contains 8K x 92 bits of writeable control store. The horizontal microinstruction format facilitates the implementation of a simple, but flexible data path. This flexibility accounts for much of the power of this machine. The EBOX data path consists of a dual-ported 256 x 32 bit scratchpad register file, an ALU, and a barrel shift network. The scratchpad contains Internal processor registers, temporary registers, constants, and architecturally defined general purpose. The 8600 microcycle is 80 nanoseconds. In one microcycle, the machine can perform an ALU or shifter operation on two scratchpad elements and store the result back in the scratchpad. The barrel shifter works in parallel with the ALU and can select any 32 consecutive bits from a 64 bit value. Two scratchpad registers or one register concatenated with a memory operand supply this 64 bit value. The MBOX contains a 16 Kbyte data cache to speed up memory accesses. A memory read takes two microcycles if the data is found in the cache, and seven cycles in the event of a cache miss.

Microcode FlowBoth EBOX and IBOX microcode share in the execution of an instruction. The IBOX microcode prefetches and decodes the instruction. Decoding is facilitated by the RAM containing opcode specific information. Based on the decode information, a microcode fork address is passed from the IBOX to the EBOX, directing the EBOX to the entry point of a microsequence

which performs the execution phase of the particular instruction. If operands are required, the IBOX delivers a fork address causing the EBOX to loop until the MBOX can fetch the operands from memory. As the operands become available, the IBOX directs the EBOX to microcode which operates on the data. After the EBOX completes the execution phase, it may transfer results back to the IBOX. The IBOX delivers any memory result to the MBOX. Otherwise, the EBOX has already stored the result into a general purpose register, with all copies of the general registers updated via the Write Bus. The fork addresses sent to the EBOX by the IBOX are stored in the decode RAM. The RAM contains up to eight fork entries for each instruction. As a result of each fork, the EBOX reads data, operates on data, or both. An optimization OCCUTS when one operand is in memory and another is in a general purpose register. The IBOX delivers the memory data on the Operand Bus and the register number on the IBGPR bus . The EBOX fork addresses are operand specific. The particular microsequence which is executed depends on the location of the data, its data type, and whether or not it is a special case handled by optimization microcode. The IBOX decodes the operand specifiers and generates the EBOX fork addresses appropriately.

VAX DATA TYPES :

(Rich hardware data types to simplify compiler)

INSTRUCTIONS:

INSTRUCTION VARIANTS:

22 ADDRESSING MODES:

ADDRESSING MODE EXAMPLES:

INSTRUCTION ENCODING: A one to two byte OPCODE specifies the operation, number of operands, and data type After the OPCODE has indicated the number of operands, each operand is represented by an Operand Specifier The Operand Specifier indicates the addressing mode for the operand and the first parameter. Any further parameters must then be read in following their designated Operand Specifier .

ENCODING FOR LOAD INSTRUCTION:

VIRTUAL MEMORY OF VAX 8600:

VIRTUAL ADDRESS EXTENSION DESIGN:

MICROPROGRAMMED PIPELINIG:

MICROPIPELINE

Lastly lets revisit ... CISC Microprocessor Families:In 1971, the Intel 4004 appeared as the first microprocessor based on a 4-bit ALU. Since then, Intel has produced the 8-bit 8008, 8080, and 8085. Intels 16-bit processors appeared in 1978 as the 8086, 8088, 80186 and 80286. In 1985, the 80386 appeared as a 32-bit machine. The 80486 are 80586 are the latest 32-bit microprocessors in the Intel 80x86 family. Motorola produced its first 8-bit microprocessor, the MC6800 in 1974, then moved to the 16 bit 68000 in 1979, and then to the 32 bit 68020 in 1984. The latest are the MC68030 and MC68040 in the Motorola MC680x0 family. National semiconductors latest 32 bit microprocessor is the NS 325 introduced in 1988. These CISC microprocessor families are widely used in thepersonal computer (PC) industry. In recent years, the parallel computer industry has begun to build experimental systems with a large number of open-architecture microprocessors. Both CISC and RISC microprocessors have been employed in these efforts.

REFERENCES: Hennessy, John L., and David A. Patterson. Computer Architecture A Quantitative Approach. 3. San Francisco: Morgan Kaufmann Publishers, 2003. VAX Architecture Handbook. Digital Equipment Corporation, 1981. http://www-inst.eecs.berkeley.edu/~cs266/sp10/readings/melvin86.pdf www.eecs.berkeley.edu/Pubs/TechRpts/1988/CSD-88-399.pdf