chung chihping
TRANSCRIPT
\Setting CMOS Environment for I _
VLSI Design ;
A Thesis Presented to
The Faculty of the College of Engineering and Technology
Ohio University
In Partial Fulfillment
of the Requirements for the Degree
Master of science
BY
Chih-Ping Chung,# 4
November, 19 89
ACKNOWLEDGEMENTS
I would like to especially thank Dr. Janusz A. Starzyk
for his inspiration and encouragement to set up CMOS
environment for VLSI design. I also thank the members of my
committee, Dr. Robert A. Curtis, Dr. Henryk J. Lozykowski
and Dr. John D. Gillam, for their invaluable assistance. My
deepest appreciation goes to Mr. Wu-Kai Lee and Mr. Randy Yu
for their efforts and CAD support. Also, thanks to Mr.
Gerald Blackburw and Miss. Elis for their patient
inspiration.
Finally, my great appreciation and acknowledgement goes
to my wife Hsiao-yen Leen and my parents for their endless
support, devotion and love, without which this job could not
have been done.
~hih-Ping Chung
TABLE OF CONTENTS
CHAPTER 1. I'NTRODUCTION ................................... 1
CHAPTER 2 . TECHNOIXGY UPGRADE FOR VALID WORKSTATION FROM nMOS TO CMOS ............................. 3 2.1 Introduction ............................... 3 2.2 Comparison between NMOS and CMOS
technologies ............................... 4 2.3 CMOS Technology ............................ 8
......................... 2.3.1 Introduction 8
2.3.2 Description of n-well fabrication
.............................. process 9
2.3.3 CMOS colormap and technology files
............... for Valid workstations 12
2.3.4 CMOS layout design rules ............. 17
CHAPTER 3. INSTALLING LVS ON THE SCALD SYSTEM ............ 21 3.1 Introduction .............................. 21 3.2 Layout tools section ...................... 21
3.2.1 The command file structure .......... 22 3.2.2 Geometric operation commands ........ 25 3.2.3 DRC/Extract control commands ........ 32 3.2.4 Hierarchy section commands .......... 33
3.3 Running COMPARE for LVS ................... 34 3.3.1 Need for LVS ........................ 34
......... 3.3.2 Hierarchical design for LVS 35
3.3.3 Running COMPARE procedure ........... 47
CHAPTER 4 . DESIGN EXAMPLE ................................ 52 4.1 New product release procedure ................ 52
......... 4.2 Example of predecoder design (PD512) 57
4.2.1 Introduction ........................... 57 ..... 4.2.2 Process definition and development 59
............. 4.2.3 Functional design of PD512 68
. .................................... CHAPTER 5 CONCUJSION 84
REFERENCES ............................................... 86
APPENDIX-A ............................................... 88
APPENDIX-B .............................................. 116
CHAPTER 1. INTRODUCTION
CMOS(Comp1ementary Metal Oxide Silicon) is the fastest
growing process technology in recent years. This is due to
the two key features of the CMOS technology: higher circuit
density combined with lower power. CMOS has the greatest
impact in low power and medium speed applications such as
industrial control, medical analyzers and most of the
automatic test equipment. CMOS products will continue to be
a popular choice in many designs. The advanced CMOS process
provides higher performance, better noise margin and lower
power consumption than nMOS. Moreover, the feature size of
CMOS has been scaling down continuously. l1 Ten years ago, a
CMOS feature size of 5 to 7.5um was state-of-the-art
technology. By the end of 1986, lum CMOS technology was
available and used increasingly to produce commercial VLSI
chips,It [Masakazu 881. Therefore, it is vital to make this
new technique available to students so that their
qualifications can match the needs of industry.
I1Verification and validation of a design are an even
more difficult challenge, [Mukherjee 861 . The development of powerful circuit design tools and software systems are
the keys to the success of VLSI technology. There are many
kinds of design tools, which are presently used and
developed for integrated-circuit chips, such as Layout
Editors (LED) , Graphics Editors (GED) , circuit extractors and
2
Layout verification System(LVS). All the principle VLSI
design tools at E.C.E. Department are available on Valid
workstations except LVS which is a layout verification tool.
It is an important design tool for VLSI design.
The purpose of this thesis is to set up and test a
complete CMOS VLSI environment on Valid workstations. The
work on this thesis was organized around three major goals:
Goal I: Upgrade old nMOS to advanced CMOS technology
In order to upgrade Valid workstations from nMOS to
CMOS, there were two steps to be done.
1) Setting up CMOS technology and color map files
2) Developing design rules checker program(DRC) for
CMOS technology rules
Goal 11: Installation of LVS in SCALD system
To run Compare 1.3L version on Valid workstations, an
Extract program and special CMOS library was necessary
to be set up.
Goal 111: Designing an example (PD512)
A circuit PD512 was developed as a design example from
functional partitioning through circuit simulation to
LVS . Chapter 2 illustrates how to do an upgrade from nMOS to
CMOS for Valid workstations, and develops CMOS design rules.
How to develop CMOS Extract program and to design a layout
for LVS are described in Chapter 3. Chapter 4 gives a design
example. Finally, further improvements and conclusions are
described in Chapter 5.
C!HAEl%R 2. TECHNOIDGY UPGRADE FOR VALID
WORKSTATION FROM nMOS TO CMOS
2.1 Introduction:
Transistors in nMOS technology with electrons as
majority carriers are called n-channel devices (nM0~) . Holes are majority carriers in p-channel devices (PMOS) . When PMOS and nMOS devices are fabricated on the same substrate, these
devices are called CMOS devices. Since PMOS and nMOS devices
are made on the same substrate, latch-up and die size are of
important concern. At present, there are several approaches
to prevent CMOS from latch-up by making p+ and n+ guard
rings and by using EPI-substrate wafers to achieve smaller
die size for CMOS technology. Furthermore, CMOS circuits
have other advantages over nMOS circuits such as lower power
dissipation and higher noise margin. Therefore, CMOS has
become a very important technology for VLSI.
To upgrade Valid tools from nMOS to CMOS, it is
necessary to change technology and color map files. Since
the CMOS fabrication process is much more complex than nMOS,
CMOS circuits need more layers in these files. The 1.8um
CMOS EPROM process is chosen to produce design rules. For
CMOS EPROM technology 13 layers are typically needed, for
very high speed products, two more layers are required such
as a second metal and via contact.
4
2.2 Comparison between nMOS and CMOS technologies
In nMOS technology p-type high-resistivity silicon
wafers are used as the substrate material. In CMOS
technology special regions must be created for PMOS
transistors. These regions are called wells or tubs. For
this CMOS EPROM process, an n-well is created in a p-type
substrate wafer. comparison between nMOS and CMOS is
described in detail.
1. nMOS technology:
nMOS technology uses enhancement mode transistors with
a positive threshold voltage, and depletion mode transistors
with a negative threshold voltage. These transistors are
used as drivers, loads, and pass transistors to design
functional blocks.
2. CMOS technology:
CMOS technology uses enhancement mode transistors as
drivers, depletion mode transistors as pass transistors, and
complementary transistors as loads.
Since nMOS and CMOS use different mode transistors as
loads, their transfer characteristics are also different.
Fig.2.l shows a transfer characteristic for an inverter when
an nMOS depletion transistor is used as a load. Fig.2.2
shows a transfer characteristic for an invertor with an nMOS
enhancement transistor used as a load. Finally Fig. 2.3
shows a transfer curve with a PMOS transistor used as load.
GND
I I I
I I
I I I I I I I
Non-zero output I I I I I I I
Fig. 2.1 Inverter and its transfer characteristic with nMOS depletion transistor as a load
Fig. 2.2 Inverter and its transfer characteristic with nMOS enhancement transistor as a load
GND I v s s
Fig. 2.3 Inverter and its transfer characteristic with PMOS transistor as a load
8
From Figs.2.1, 2.2 and 2.3, we can summarize the
results of comparisons between nMOS and CMOS inverters as
follows:
a) Noise margin:
There is non-zero output for nMOS and zero output for
CMOS when input is high. Therefore, CMOS has higher noise
margin than nMOS.
b) Power dissipation:
The current of an nMOS inverter flows all the time for
logical 1 inputs, however, current of a CMOS inverter flows
only during logic transition, therefore, CMOS has zero
static power dissipation.
With the new improvements in maskmaking, it is possible
to fabricate devices smaller and smaller in size. The nMOS
circuits become very dense. Maximum power dissipation become
the limiting factor for high density nMOS VLSI chips. In
order to reduce the dc power dissipation, obtain higher
noise margin, and high density of VLSI devices, CMOS is the
obvious choice.
2.3 CMOS technology:
2.3.1 Introduction
An n-well CMOS process, which is currently the most
popular process in CMOS fabrication, will be discussed in
this section. CMOS technology provides both n-channel and p-
channel MOS transistors on the same chip. nMOS transistors
are designed in the p-type substrate, while PMOS transistors
9
are built in the n-well. A simple n-well CMOS fabrication
sequence is shown in Fig.2.4 and a set-up procedure for
layout and design rule checking is discussed in Sections
2.3.3 and 2.3.4.
2.3.2 Description of n-well fabrication process
As an illustration of the fabrication process, a CMOS
inverter example is described. The first step is to define
the n-well regions. To form them, the phosphorus is
implanted into these regions at high-temperature cycle.
After n-well implant, the active regions are defined
for MOS source and drain regions. The formation of active
regions are accomplished through local oxidation of silicon
(Locos process). In this process thick regions of silicon
dioxide are grown on the silicon substrate to provide
isolation between nMOS and PMOS transistors. The thickness
of the field oxide is about 5000 A.
The gate oxides are grown only in the open areas of the
active region. In general, the thickness of the oxide layer
is about 250A. The gate oxides will affect the threshold
voltage of the MOS transistors. When field and gate oxide
growth is finished, the polysilicon deposition will be
made.
Usually the chemical vapor deposition(CVD) process is
used to deposit the polysilicon (poly) layer over the entire
wafer. Poly is used, not only as a gate, but also for
interconnections. We use the dry etching process to remove
1 Formation of n-well regions I *
Formation of the active regions
Field and gate oxide growth
Deposit the polysilicon layer 1 +
N diffusion &
I + P diffusion
I * I CVD deposition of SiO2
Contact cuts I I
Metal l izat ion
I Passivat ion I Packaging
Fig. 2.4 CMOS fabrication sequence
11
the undesired poly which is outside of the gate regions and
the interconnecting patterns. After the thin gate oxide is
etched, we use a n+ mask (n-select mask) to define source
and drain regions of nMOS transistors and implant phosphorus
to obtain low-resistance source and drain regions. In the
same manner, we define the p+ source and drain regions of
PMOS transistors.
The p+ source and drain regions of PMOS transistors are
defined by a negative of the n-select mask. Boron is used as
the dopant in the process step instead of phosphorus, when
completing the implant of p+ and n+ source/drain.
We use a CVD technique to deposit SiOZ over the entire
wafer as an insulating layer.
In order to expose the n+ and p+ areas and connect them
to outside metal, we use a contact mask to define contact
cuts in the insulating layer.
The metallization mask is used to define the
interconnection pattern. Then, the evaporation process is
used to deposit aluminum over the entire wafer, and the
undesired metal is removed by etching.
Passivation is used in the final step of the wafer
fabrication, in order to protect the wafer surface from
contaminants and scratches.
We see from the above discussion that ten layers of
masks are needed for device fabrication in a typical CMOS
process. Layer data is either drawn directly or generated
indirectly from logic operations in Valid CAD systems. The
details are described in 2.3.3.
2.3.3 CMOS colormap and technology files for Valid
workstations
In general, colormap and technology files are needed
only for layout drawing. To create a layout drawing, we need
to specify all the layers. "A technology file defines
various masks and symbolic layers in a cell. This file also
defines the color, fill pattern, and outline pattern used to
display each layer, and references a colormap file that sets
each layer's color^^, (Valid layout EDITOR REFERENCE MANUAL).
Colormap and technology files will be discussed next.
a) Colormap file:
Colormap file determines colors of all layers on the
screen. The red, green and blue colors are the three basic
colors. The color of combination layers is determined by the
intensities of the red, green, and blue color. The intensity
values ranges from 0 (off) to 255 (maximum intensity) . We can change the color of layers by using PED(Pa1ette Editor
Display). The format of the colormap file is:
[red green blue color number]
Color number is associated with technology file, the colors
of different layers are shown below:
The p active layer would be in yellow on a color
graphics.termina1.
The n active layer is in green
The polysilicon layer (poly2) is in red
The metal layer is in blue
The contact cut is cross
The n-well layer is dashed line
An example of CMOS color map file is presented below:
[red, green, blue, color member]
178 94 183 1
0 200 0 2
250 100 0 3
Column 1 is red, column 2 is green and column 3 is
blue, number 178 is intensity value of red, 94 is intensity
value of green, 183 is intensity value of blue, 1 is color
number corresponding to the color number of technology file.
To change the color of a layer, we can call up the PED
display by entering this command:
PED
Then select the EDIT command from the PED display (Fig.2.5)
and select the layer to edit. There are several ways to pick
layers:
1. Pick layers from the layer menu
2. Select one or more layers from the active palette
3. Type layer names at the keyboard
To obtain the desired color, we need to adjust the intensity
values of red, green and blue. When you want to exit from
14
PED, use the QUIT command. A physical CMOS color map file is
shown in Appendix A-1.
b) Technology file:
Different mask symbolic layers and the unit sizes are
described in a technology file. The first line of the file
is the name of the technology such as nMOS, CMOS etc. The
second line is the name of the colormap file to be used with
the technology. The third line contains three numbers
separated by spaces. The first number specifies the number
of centimicrons such as 100 for microns and 254 for mils
(lmil =25.4um) . Most companies use micron instead of mils
in current development. The second number is the grid
spacing and the third number is the grid interval in this
technology. Each layer in the technology file is described
in the following format.
layer-name outline-pattern fill-style color-number
In this format layer-name is the name of the layer. The
outline-pattern describes the style of the outline and is a
hexadecimal number between 0 and FFFF. The value 0
indicates no outline, and value FFFF indicates a solid line.
Values between 0 and FFFF describe patterns of dots or
dashes. There are four reserved words in the fill-style:
empty, solid, stipple, and cross. The color-number specifies
the color for the layer and is associated with color map.
Technology Editor(TED) is able to change the outline-pattern
and fill-style of a layer. To use the Technology ~ditor, we
can enter the following command from LED:
TED
Fig.2.6 shows example TED display. Seven commands are shown
in TED display such as edit, buf, color, save, logop, fill,
and quit. To edit the color or fill pattern for a layer,
select the EDIT command from the TED menu. Color command can
change color number. We can use the fill command to change
fill-style, use the buf command to store the current stipple
and use the logop command to perform logical operations on
the current stipple by using the stipples in the buffers.
In general, most users will never need to change a
technology file. The system manager will change this file
when the process is changed or special layer is added.
However, a user may change to outline pattern or fill style
for a particular layer in the technology file. The CMOS
technology file shown in Appendix A-2 is for a regular 13-
layer EPROM process. Nactive and pactive are drawn layers.
When taped out for reticles, the nactive and pactive layers
should be merged to form an active layer. The p-field layer
is generated from the reverse field of an oversized n-well
layer while the p-plus layer is generated from an oversized
pactive layer. The n-plus layer is just the reverse field
layer of the p-plus layer. A hvim layer is added in the
technology file for 12V or higher while Mhvim is added for
voltages between 6 and 12V for EPROM or EEPROM technology.
The details of the technology file are described in the
following:
Fig.2.5 PED display for a color
Fig.2.6 Example TED display
17
{ This is the typical technology file example for 1.8um CMOS
double-poly, single metal, N-well EPROM process).
{The layers shown below are in the order of mask sequence,
some are layout drawn layers, some are added layers for the
purpose of easier layout drawing and design rule checks).
$
CMOS {specifies specific technology)
CMOS.CMP{specifies color map file)
100 0.1 2 (100 stands for micro meter, grid resolution
0. lum)
$
Nwell c5c5 empty 8 [layer name,outline-pattern, fill-style,
color number]
$
Pfield ffff stipple 1 { ffff indicates a solid line )
c) Discussion:
Valid workstations use a layer name as a layer instead
of using a layer number in the technology file. It is not
convenient to run LVS in a layer name system. When running
LVS for the top cell, we have to remove the signal name of a
subcell.
2.3.4 CMOS layout design rules
The purpose of the design rules are to guarantee the
precise layout according to the rules defined by the
specific process. The rules are the worst process deviation:
mask misalignment, overetching, spreading of the diffusion,
18
and tolerances of other field oxides etc. More layers will
need more layout design rules. These rules are so
complicated that manual checking becomes extremely
difficult. Besides that, the more accurate design rule check
program must report false errors, which become more
difficult when the number of layers increases. The typical
13-layer CMOS 1.8um EPROM design rules and programs are
described below. They can be easily modified for SRAM, DRAM
or other technologies. Some basic layout design rules are
explained below.
1. Minimum width: In order to prevent the line layer from
notching or necking, the minimum width for each specific
layer is defined; such as minimum width for active, polyl,
poly2, or metal layers.
2. H i n h u m spacing: The line to line spacing is defined to
avoid line shorts or bridging for polyl, poly2 and metal
layers. Also, the minimum active spacing is usually
specified to prevent active to active leakage in punch-
through mode. Some larger rules are specified, especially in
1/0 or high voltage areas in EPROM or EEPROM technologies.
In these cases, the HVIM and MHVIM defined in DRC. CMD file
are needed to perform special checks.
3. Overlap: This check is for two overlapped layers.
Normally it is needed to check metal contact, poly contact
or active contacts. For different voltages, different
overlap rules are required.
4 . Misalignment: Misalignment between masking layers
19
determines design rules. There are two kinds of alignments.
1) direct alignment, and 2) indirect alignment. The author
would like to illustrate alignments by using 1.8um CMOS
process. In this process, n-well is a major flat layer,
active and p-field to n-well are direct alignments, active
to p-field is an indirect alignment, polyl, poly2, N+
implant and P+ implant to active are direct alignments. They
are in indirect alignments with each other. Contact to
poly2, metal to contact and pad to metal are direct
alignments. Fig. 2.7 shows an alignment sequence. It is
helpful to us to understand the relation between direct and
indirect alignment. The direct alignment has lower
misalignment errors.
The design rules of 1.8um CMOS process used by Elite
Semiconductor Inc. of San Jose, California are adopted to
upgrade O.U. Valid logic system from nMOS to CMOS.
Organization of these rules is discussed in the Appendix
A-3.
Act ive P - f i e l d
N+ implant P+ implant
Contact '3 Metal
Fig. 2.7 Mask alignment
CHAPTER 3. INSTALLING LVS ON THE SCALD SYSTEM
3.1 Introduction:
It is much more difficult to find layout errors using
the naked eye. Instead, we use a computer to process this
work. The SCALD star IC Layout Verification System (LVS) can
perform the task of verifying IC layout designs. A COMPARE
program is in the system for comparing electrical
connectivity of an IC layout with its corresponding
schematic representation.
The SCALD system Graphics Editor (GED) creates
schematics and the system automatically creates a
connectivity file to describe connections of components. We
also use Layout Editor (LED) to draw the IC layout. However,
an LED layout drawing does not contain electrical
connectivity information, so we use an Extract program to
extract connectivity from the layout data. Extract produces
an electrical connectivity file in the same format as the
GED schematic connectivity file. Comparing schematics and
layout connectivity files is the primary purpose of COMPARE.
~f circuit elements do not match, we can easily correct
layout or schematic errors based on the COMPARE results.
Before running the COMPARE program, we need to set up
command files for circuit extraction.
3.2 Layout tools section
Assuming that we have completed subcell layout, we have
22
to check if it is a correct layout or not. Both circuit
extraction and DRC are performed to eliminate layout hook-up
and design rule errors. Before running Extract and DRC, we
must first set up two command files: drc.cmd and
extract .cmd. A perfect run of DRC and Extract program will
not produce false errors.
3.2.1 The command file structure
The command file is created with a UNIX text editor.
There are five sections in the command file: files, layers,
hierarchy, extract, and checks. Their order is shown as
below:
section
<< files>>
<< layers>>
<< hierarchy>>
<< extract>>
<< checks>>
description
location of files
list of layers
rules for hierarchy
rules for EXTRACT
rules for DRC
"The files and layers sections must be present in every
DRC/Extract command files; the hierarchy, extract, and
checks sections are required only when their associated
operations are to be performed. For example, when performing
a DRC on a cell, the extract section can be omitted.
Typically, a separate command file is created for Design
Rule Checks and circuit Extract. Files that do checks are
23
called DRC files, and files that do extraction are called
DRC EXTRACT files, [Layout Verification DRC/EXTRACT
REFERENCE MANUAL 2-31.
1. The files section:
The files section contains all the information about a
cell. For example, where each cell is located and what
libraries are used.
The files section contains two: a) The Directory and
Use commands, and b) The Library command
a) The directory and use commands
The Directory and Use commands will specify the SCALD
directory that contains the cell design data to be
processed. The legal expressions are:
Use directory-name
Directory-name
b) The library command
The master library directory can be accessed by using a
lib command. The following expression can be used:
Lib library-name
2. The layers section:
There are various types of layers used in the layers
section: input layers, intermediate layers and output
layers.
a) Input layers:
Input layers are defined in a technology file. They are
also called drawing layers such as n-well, pactive,
nactive, polyl, poly2, contact, metal, sae and vapox for
PD512.
b) Intermediate layers:
Intermediate layers are temporary layers, which are
created from combinations of input layers. For example, when
two drawing layers overlap, the overlapped area is defined
as the intermediate layer used to check layout design rules.
c) Output layers:
Output layers can be created by using the keep command,
and can be written back to the layout data files.
Intermediate layers and output layers are created by the
geometric operation commands. DRC and Extract command files
are completed by these operators, which will be described in
the next section.
3. The hierarchy section:
The Hierarchy section is to define the relation between
the topcell and a subcell. It is necessary to give subcell a
pin-name in order that subcells are able to connect to the
topcell.
4 . The extract section:
The extract section is to define transistors from the
layout and determine circuit connectivity among devices.
5 . The checks section:
The checks section checks layout for violation of the
design rules.
3.2.2 Geometric operation commands
Geometric operation commands are needed in order to
create new layers from combinations of drawing layers. These
new layers are used to define transistors or to do DRC
checking. These commands are: and, andnot, or, xor, expand,
include. The following will explain how these operators
create new layers.
1. The And Command
The AND command can create layer3 by intersection of layerl and layer2
layer3 = layerl and layer2
For example:
Drawing layer AND operate Result
l a y e r l
l a y e r 2 l a y e r 3
2. The OR command
The OR command can be expressed by the following form:
layer3 = layer1 or layer2
For example:
Drawing layer OR command Result
l a y e r
l a y e r
3. The XOR command
The XOR command creats layer3 from layerl and layer2. Layer3 contains all regions of layerl and layer2, excluding their common part.
layer3 = layerl XOR layer2
For example:
Drawing layer
l a y e r l
l aye r2
XOR command Result
4. The ANDNOT command
The ANDNOT command has the following form:
Layer3 regions is the layerl with overlap of layerl and layer2 removed.
layer3 = layerl ANDNOT layer2
For example:
Drawing layer ANDNOT command Result
5. The Include command
The Include command will copy layerl to layer3 if there are intersections between layerl and l a y e r 2 ,
layer3= layerl include layer2
For example:
Drawing layer include operate r e s u l t
6. The Expand command
The Expand command will increase or decrease layerl by a distance to produce layer2
expand layerl distance layer2
For example:
Drawing layer Expand operate
l ayer1 l ayer2 l ayer2
3.2.3 DRC/Extract control commands
DRC/Extract control commands control program execution.
These control commands are: analysis-name, donut-size, keep-
updated, ignore-maskout, flat-cell-size, flat-cell-name and
ignore-subcell. They are described below:
1. The wanalysis-namem command
This command specifies DRC/Extract file to be analyzed
and separates the results of DRC/Extract.
For example:
analysis-name "drew
This command lets program execute DRC check instead of
executing Extract.
2. The mdonut-sizen command
The purpose of donut-size is to let the program check
the overlap of the topcell and subcell instead of rechecking
the entire subcell.
A general rule for setting the donut size is:
donut size = overlap-max + largest-design-rule
where overlap-max is the maximum allowable cell
overlap.
3. The mkeep-updatedn command
If the layout and command file have been changed since
the last DRC, the keep-updated command forces the
DRC/Extract program to run the DRC/Extract program again.
4 . The wignore-maskoutm command
The ignore-maskout command causes DRC/Extract not to
check or extract all layers beneath the mask layer.
5. The nflat-cell-size' command
The flat-cell-size command will flatten all cells
smaller than the specified max-size, and flatten all
hierarchies below these cells.
For example:
flat-cell-size 6.0
will flatten all cells below 6.0um.
6. The Nflat-cell-namen command.
This command is expressed by: flat-cell-name ttcell-
namett.
For example
flat-cell-name "*" will flatten all cells.
7. The nignore-subcelln , Hignore-multiplen commands The ignore-subcell command causes DRC and EXTRACT not
to check for errors or extract subcell data. The ignore-
multiple command causes DRC and EXTRACT to ignore multiple
signal names.
Since the O.U. LED system is the 8.07 version, it does
not have flat-cell-name and ignore-multiple commands.
Therefore, this system is not able to extract flat layout
nor to compare the flat netlists.
3.2.4 Hierarchy section commands
Hierarchy section commands are to define the relation
between the parent cell and a subcell. These commands are:
define-pin, overlap-max, ignore-overlaps and get-subcell-
data commands.
1. The ndefine-pinn command
The define-pin command causes DRC/EXTRACT to use the
user-defined pin area, rather than the machine-generated pin
area. Parent cell and subcells make connection through these
pin-areas.
2. The noverlap-maxn command
The overlap-max command defines the maximum allowable
amount of overlap between two cells.
3. The nignore-overlapsn command
The ignore-overlaps command causes DRC/Extract to
ignore overlaps.
4 . The nget-subcell-datan command
This command causes the DRC and Extract to retrieve
data from the subcellsl abstracts.
Above commands will be used by DRC and Extract
programs. Appendix A-4 shows the physical DRC and Extract
programs.
3.3 Running COMPARE for LVS
3.3.1 Need for LVS
The main purpose of running LVS is to determine whether
or not a physical layout matches the schematic. In general,
there are two ways to run LVS; one is to run hierarchically,
and the other is to run flatly. A physical layout includes
several parent cells and subcells. For hierarchical
comparisons, subcells are considered as bodies and only the
35
connectivity among bodies is checked. For flat comparison,
parent cells and subcells will be flattened to transistor
level, then COMPARE will check the connectivity among
transistors.
Before running LVS, all signal names must be placed in
the schematic and the layout for hierarchical and flat
comparison. For hierarchical comparison, the schematic must
be a ".spiceH name, and it can only use nMOS or PMOS parts
from the spice library.
For each nMOS or PMOS, power(VCC) and GND(VSS) signals
must be attached. The symbol(.body) of every hierarchy level
must have power and GND pins and the It. logic and .spiceIf
must have VCC\I and VSS\I, and the wafer substrate signal is
still a global signal, but must be attached to every part.
3.3.2 Hierarchical design for LVS
In general, hierarchical design must be used in VLSI
circuits. There are several benefits for using hierarchical
designs :
a. savings in memory space
b. Easy check for LVS errors
c. Reduction in program execution time
Therefore, most large chips are designed
hierarchically. For hierarchical extraction, every cell must
have signal names, which will become the pin names of a
body. The pins of a cell are defined by donut area and
pin - area layer which is the drawing layer of LED. An
inverter is used to explain a pin name and signal name.
Fig.3.1 shows the signal names of a schematic and layout of
a CMOS inverter. Fig. 3.2 shows the pin names of a body of a
CMOS inverter. A test circuit shown in Fig.3.3 is used to
show the relationship between parent cell (test) and subcell
(inverter). Fig. 3.4 shows the body of parent cell (test).
In hierarchical design, pin and overlay are the two
ways to define the relationship between 1) parent cell and
subcell 2) subcell and subcell 3) primitive and subcell
1) Parent cell and subcell
Parent cell and subcell can only make connections
through these pin - areas. The parent cell will only read the
abstract data (abstract.l.extract) and not the whole subcell
layout data. The abstract data of a subcell is the layout
area defined by "pin - areaw. Pin-area is created through
logical operations or pin-area layer. In other words, the
parent cell can only see the pin areas of the subcell.
2) Subcell and subcell
There are overlaps between subcell and subcell. The
command "OVERLAP-MAX max-numfl in the extract command file is
used to control any extract errors of the overlaps, and
max-num should be set up to twice of the pin - area defined.
For example:
create_pin=boundary andnot (boundary expand -12.0)
pin - area=pin-area or creategin
OVERLAP-MAX 2 4.0
If the overlap of subcell and subcell is smaller than
Schematic
layout INVEIlyout-bin.1 .I
pact ive mact ive contact
P O ~ Y m e t a l . . cell boundary
Fig.3.1 The pin names of a CMOS inverter
Schematic
VCC
OUT
VSS
layout
Fig.3.2 The schematic body and the layout extract of a CMOS inverter.
Schematic
V C C \ I
layout TEST\lyout-bin.1 ..I
Fig.3.3 The relation between parent cell and subcell
Schematic
Tes t
Fig. 3.4 The schematic body and layout extract of test (parent cell)
41
twenty four, the connection can be made between them. If the
overlap is greater than the OVERLAP - MAX and there is no
other way around, use the pin - area layer to create a bigger pin.
3) primitive and subcell
If primitives (hard data) overlap the subcell, the
primitives have to touch the pin of the subcell.
In order to run hierarchical LVS, the body name must be
the same for schematics (GED) and layout, and the pin names
(signal names) must be the same. The several rules for
putting the signal names are as follows:
1. Put names inside the edge of the cell
(so not to enlarge the boundary of the cell)
2. Keep n+ll and signal name text together
(for easy identification)
3. Put signal names on every named net
i.e, if there are two nets that have the same
name put signal name on every one of them.
4. Put signal names as close to the cell edge as
possible (so it will become the pin and at the
cell edge) . 5 . Put signal names on primitives (hard data):
If it is within 12um of the cell edge, it does
not need the pin-area.
6. Put signal names on each subcell:
a. Must be on the pins of the subcell
b. Put pin-area layer to overlap the signal
name
c. Choose the place closest to the parent cell
edge
When running the comparison on hierarchical, the layout
designer has to satisfy the four rules shown in the
following figures, however, the four rules may be ignored if
compare is run on a flat design.
Layout Rule 1:
Do not make device in different cells.
Example : A nMOS device which has nactive
in one cell and polysilicon in
another cell is not allowed.
nat ive
cell B
Not an nMOS
Layout Rule 2:
Do not make contact connection of different layers in different cells
Example : Metal and polysilicon connect through contact.
Can not have polysilicon and contact in a cell,
and metal in another cell.
I polysi l icon I I- - - I ------
cell A
polys i l ico
m e t a l
- - 7 cell B I I I I I I I
contact I I I I I I I
--*
No connection between metal and polysilicon
Layout Rule 3:
Do not make connection of the same layer in different cells.
Example : A metal net was discontinued in a cell A.
If you connect this layer on the top level, the extract program will not extract right.
Cell A
Cell B
Do not fix in cell B Fix in cell A
Layout Rule 4:
Put a proper shape of boundary layer in every cell.
Example : An error in connectivity can not be detected without proper boundary.
pin areak/I/A 1 I L,--,,-,-,-- .,-----.
I 4.1 boundary
A short will not be detected without proper boundary.
3.3.3 ~unning Compare procedure
Fig.3.5 shows the procedure for running a comparison
program. Before running the comparison, a cell layout is
extracted to generate a connectivity file (lyout cn.l.1) and - a spice connectivity file (spice-cn.1.1) is generated when
the schematic is written out. The COMPARE program will
compare spice cn.l.1 and lyout cn.l.1. - -
The two key points for running compare are summarized
below:
1. Put both schematic and layout in the same cell name - directory
For example:
cell name/lyout-bin.l.1 - lyout-cn.l.1
logic - bn.l.1
logic - cn.l.1
logic - dp.l.1
2. To run compare hierarchically
a. drc cell - name extract.cmd
b. compare cell - name spice-cn.l.1 lyout-cn.l.1
It will automatically find spice - cn.l.1 and lyout - cn.l.1
under cell - name directory and compare them. Fig.3.6 and
Fig.3.7 represent the schematic and layout, respectively.
Fig.3.8 is the result of the comparison.
GRAPHICS EDITOR
LAYOUT EDITOR
I CELL DESCRIPTION I
Fig. 3.5 The procedure for running compare
* 7
CONNECTIVITY FILE
DRCI EXTRACT
logic-cn.1 .I - o r
CONNECTIVITY ' FlLE
lyout-cn.1 .I
DRAWING
TITLE=RSDEC
LAS?JE!?W~ ~ c t M 00a 38 39 19~9
Fig 3.6 Schematic of a RSDEC circuit
. . I I?;. 3 7 I . a p o u ~ f i f a HSDEC c i r c u i t
SCALDsystem COMPARE Ver 9.2 SUN3-P1 (Tue Mar 15 01:08:49 PST 1988).
Processing rsdech/logic cn.l.1
Processing rsdech/lyout-cn.l.1
Generating Body Table
BODYTABLE ********* Name Number Name Nuabe r .................................................................... invel inve2 nand3
Num Of Bodies N u m Of Si~nals
1 i nve 1 1 i nve 2 1 nand3
3 Num Of Bodies 3 8 Num Of Signals 8
Comparing rsdech/logic cn.l.1 rsdech/lyout cn.l.1
inve 1 inve2 nand3 vss unSlSinvelS3pSinp unSlSinve2S2pSinp a6s a5s a48 an VCC
The Circuits Match.
inve 1 inve2 nand3 un52 unS 7 un56 unS 3 unt 5 un54 un58 unS 1
Fig.3.8 The result of the compariion
CHAPTER 4. DESIGN EXAMPLE
4.1 New product release procedure
The ability of a semiconductor company to be a main
supplier of its products, depends on release the new
products as quickly as possible. However, the products must
be reliable and complete with published specifications. This
section outlines a typical release procedure for a new
product in semiconductor companies. The procedure describes
the product development process from the design stage to the
full production status.
The following is the list of stages, which a product
will go through from the product design to full production
release status:
1. Engineering proposal
2. Design
3. Development
4. Simulation or prototype development
5 . Pilot production
1. Engineering proposal
The design engineer develops an internal proposal for
the product design based on the marketing definition of the
product and available fabrication processes. This proposal
should be reviewed by marketing and process engineering
departments. The preliminary Design Review should address
the following issues:
a) Product development
b) Product specifications
c) Product development schedules
d) Cost objectives
e) Competitive and manufacturing cost analysis
A full scale design project will be initiated upon
successful completion of the Design Review. That is,
marketing, process engineering and manufacturing engineering
must agree with the product specifications and development
strategies.
2. Design phase
A complete design cycle is initiated to execute the
design. Sufficient analytical work shall be completed. This
will ensure that the final design meets the product
ob j ective specification. The following product design
analysis tasks should be completed prior to a preliminary
design review:
a) Simulation studies(i.e., design models, process models
etc.)
b) Breadboard circuit test results and layout constraints
c) Discussion of the expected areas of difficulty in
meeting the applicable product specifications
d) Special or new (if any) manufacturing requirements
e) Unique material requirements
f) Review of all the current manufacturing factors and
levels
h) Revised development schedule
54
3. Development
Once the design concept is reviewed and approved, full
scale development of the product is authorized. Design for
initial prototyping (i. el prototype wafer) , process
specifications and test specifications, as well as test
methodologies, must be identified during this phase. At this
stage, the new product facilitator must select the team
members from the functional groups. This team includes a
marketing engineer, design engineer, product engineer,
process engineer, test engineer and reliability/quality
assurance engineer. It is important that the quality
assurance engineer and reliability engineer become formally
involved at this stage of the development to review the
actions necessary to fully evaluate the reliability of the
product and identify any special concerns about outgoing
quality levels. Furthermore, the product development team
must consider all the factors and levels of manufacturing
variability to overcome the problems of variability. In
order to overcome the problems of manufacturing variability,
design and product engineering departments must prepare
product characterization plans, which apply to the methods
of experimental design. Exit from the development stage is
through the critical design review, which addresses all
issues regarding the development phase. At a minimum, the
following shall be reviewed:
a) Product development report (i.e., define design rules,
layout and cell simulation)
5 5
b) Process development report (i . e. , process models and process architecture)
c) Define manufacturing factors and levels affecting the
product design
d) Test parameters specifications
e) Cost projection
f) Reliability projections
g) Revised schedule (if applicable)
4. Simulation or Prototype Development
Simulation or prototyping of a new product design is
the responsibility of the design engineering group. At this
stage, the design engineer should work closely with the
process engineer in developing appropriate circuit models,
which will be utilized in the product design. This may
involve building special kit parts and subcells of the
product. Furthermore, the design engineer using simulation,
must include AC and DC performance evaluations of the
product. In summary, the prototype stage is completed when
the following items are done:
a) The design report showing test data from the
prototypes, specifically compare the test data with
both the simulation and breadboard data. Simulation
results might be adequate on projects which require
complex breadboards.
b) The design action report must show the areas of
redesign needed prior to pilot production. The
designer must document all the process model
parameters used during the simulation. These
process model parameters must be reviewed and
approved by process engineering and wafer
fabrication engineering departments.
c) The product quality plan giving requirements for
reliability evaluations and product quality control
requirements.
d) A preliminary product specification developed by a
marketing representative based on the design
engineer's feasibility report. A marketing
representative will be responsible for identifying a
product introduction plan.
e) A test development project must be able to test the
product parameters. This test development will be used
to characterize the product performance and eventually,
it will be transferred to production testing.
5 . Pilot production
The purpose of pilot production is to evaluate the
product performance prior to production release. The
initial production lot will be reviewed by the design
engineer for compliance with the design objective
specifications . Moreover, the product engineer should
assume primary responsibility for the product and support
from design engineering at this time. A statistical sample
plan should be designed to characterize the product
characteristics in a package. Exit from pilot production to
full production status requires completion of the following
57
items :
a) Product and process engineering analyses yields problems
in any pilot production lots. This will include any
design modifications requested from design engineering to
support volume production.
b) Review of the product characterization report.
c) All requirements specified in the quality plan for the
product and reliability report.
d) Release product development document package.
e) Final data sheet limits.
In conclusion, a new product release will take five
steps from engineering proposal to pilot production. The
next section will give an example of a new product design.
4.2 Example of predecoder design (PD512)
4.2.1 Introduction
PD512 is a standard industrial predecoder for memory
chips. The author likes to present a chip design procedure
by using this design example. This design procedure starts
from specification of functional blocks, through simulation,
layout, LVS, DRC to taping out the chip. The author chose
1.8um CMOS technology for this chip. Fig.4.1 shows the IC
design procedure.
The product can be developed by interconnecting several
sub cells. Each subcell presents a functional block of the
PD512 system. The intention of this example is to develop
the key functional blocks for the system.
I CIRCUIT DEFINITION I
I PROCESS DEFINITION I IC
PROCESS DEVELOPMENTISIMULATION A
It I DEVICE CHARACTERIZATION I
+ FUNCTIONAL PARTITIONINGISIMULATION
I
I LOGIC DESlGNlSlMULATlON I
CIRCUIT SCHEMATIC
CIRCUIT SIMULATION
LAYOUT DESIGN -77- LAYOUT DIGITIZATION TO GENERATE I COMPUTERIZED LAYOUT DATA BASE
1. LAYOUT DESIGN RULE CHECKING 2. CONSISTENCY CHECKING BETWEEN
LAYOUT AND CIRCUIT SCHEMATIC
IC IC MASK PATTERN GENERATION
I lC PROCESS I Fig.4.1 The IC design procedure
59
The PD512 has automatic power-down capability which is
controlled by the chip enable signal(CEB). When CEB goes
high, the device automatically powers down and remains in a
low-power stand by mode. This unique feature provides
substantial system level power savings.
4.2.2 Process definition and development
1. Poly-gate CMOS process architecture
The objective of this section is to define a simple n-
well process architecture, which can be used to fabricate
the functional cells described in the next section. This
describes each sequence required in the fabrication process.
The basic characteristics of this process are as follows:
a. It is an n-well process
b. It provides two layers of connections; one poly and on
metal.
c. It offers medium scale integration because it uses very
simple transistor structures and the process can be used
for high voltage by increasing the gate length in
proportion to the depletion width.
d. It requires that the N-wells and the substrate are
connected to VCC and VSS respectively. Such connections
are needed to prevent latch up.
This standard poly-gate CMOS process can be an
excellent process for the implementation of large circuits
such as PD512. The explanation for each process step is
listed above the cross sectional diagrams.
CMOS EPROM PROCESS CROSS SECTION
1. INITIAL OXIDATION ( 5000A )
2. N-WELL MASKIOXIDE ETCHIN-WELL IMPLANT(ph0s)
PHOS
3. N-WELL DRIVE ( 3000A OXIDE IN WELL )
\ N-WELL /
4. OXIDE ETCH /PAD OXIDATION (350A) INITRIDE DEPOSITION (1 500A)
N-WELL
5. ACTIVE MASK1 NITRIDE ETCH NITRIDE
\ N-WELL / OADE
6. P-FIELD MASK 1 P-FIELD IMPLANT (BORON)
BORON NITRIDE
7. FIELD OXIDATION (8500A)INITRIDE & PAD OXIDE STRIP
8. SCRlFlClAL OXIDATION (150A)l OXIDE ETCH
\ N-WELL / I - FOX
9. CELL IMPLANT MASK1 CELL IMPLANT (BORON)
10. DEPLETION IMPLANT MASKIDEPLETION IMPLANT (AS.)
AS. - \ N-WELL /
I 1 .FIRST GATE OXIDATION (350A)l POLY1 DEP &DOPE
POLY1
12. POLY1 MASK1 POLY1 ETCH
13. FIRST GATE OXIDE ETCHIVT ADJ. IMPLANT (BORON)
14. SECOND GATE OXIDATION (350A)l POLY2 DEP. & DOPE 1 POLY2 OXIDATION (450A)
\ N-WELL I 15. POLY2 MASK1 POLY2 OXIDE AND POLY2 ETCH
1 INTERPOLY OXIDE ETCH PR
16. SAE MASK1 POLY1 ETCH
17. SID OXIDATION (150A)
POLY2 POLYI
18. N+ SID IMPLANT MASKI N+ SID IMPLANT
AS.
\ N-WELL /
19. SID RE-OXIDATION(25OA)I P+ SID IMPLANT MASK IP+ SID IMPLANT (BORON)
20. BPSG DEP. (9000A) I FLOW (9256)
BPSG Em
21. CONTACT MASK / CONTACT ETCH
POLY2 POLYI
22. METAL SPUTTER /METAL MASK / METAL ETCH
Eq @g METAL OXIDE SID POLY2 POLYI
N-WELL
2. Parameter Determination and description for simulation
Accurate circuit simulation is only possible by
specifying accurate and meaningful parameters. As the
process varies from time to time, model parameters must be
measured for the typical transistors as well as the worst
case. The parameters are extracted manually or
automatically. The extracted parameters shown in Appendix
A-5 are written in a file for the spice program and are as
described below:
Name
F1
WDEL
TOX
MBL
LAMBDA
KU
LDEL
RD
RS
VTO
GAMMA
UB
Units Description
V/cm Mobility reduction field
m Measured minus drawn channel width
A Represents the oxide thickness
exponent Exponent for mobility reduction due to
source-drain electric field
cm/v Channel length modulation
flag Velocity saturation switch
m Measured minus drawn channel length
ohms Drain resistance
ohms Source resistance
V The threshold voltage at zero
substrate bias
V**O. 5 Surface threshold parameter
cm**2/v-sec Low field bulk mobility
LATD meter Lateral diffusion into channel from
source and drain diffusion
FDS
WIC
MOB
CLM
LDIF
CF1
CGSO
TRD
TRS
TCV
BEX
LMLT
meter
volts
F/meter
l/deg K
l/deg K
v/deg K
EXPON
factor
Field drain to source, controls
reduction of threshold due to source-
drain electric field. default=O
Weak inversion equation selection
Default=O.O (no weak inversion)
Mobility equation selector.Default=O
Channel length modulation equation
selector. Default=O
Fringing field factor for gate-to
source and gate-to-drain overlap
capacitance calculation
Length of lightly doped diffusion
Modified Meyer control for transition
from depletion to weak inversion for
CGSO
Gate-source overlap capacitance per
meter channel width
Temperature coefficient for drain
resistor
Temperature coefficient for source
resistor
Threshold voltage temperature
coefficient
Temperature exponent; BEX is defined
as UO temperature exponent, correction
for UO (low field mobility)
Length multiplier
WMLT
PHI
6 8
factor Diffusion layer shrink reduction
V Surface potential
4.2.3 Functional design of PD512
1. Functional partitioning
The functional design of the PD512 product is based on
the poly-gate high voltage CMOS process. The process is
assumed to have a minimum device length of 3um for high
voltage, 1.8um for low voltage.
PD512 contains an input buffer, R-decoder, S-decoder,
Clock, VPISW and XT decoder. The input buffer is TTL
compatible. It is designed to communicate between a CMOS
circuit and a TTL circuit. R-decoder and S-decoder are
predecoders. A clock circuit is able to generate 2OMHZ to
3OMHZ signals to supply XT decoders and VPISW. VPISW can
switch VCC(5V) to VPP(12V). XT decoders are also
predecoders, but have pump circuits to put high
voltage(l2V) on word lines when circuits are in the program
mode. A functional block diagram of the PD512 system is
illustrated in Fig. 4.2. A computer simulation was performed
for the key functional blocks of PD512.
2. Circuit schematic and simulation
a) Input buffer section
An input buffer is used to interface a TTL level signal
from the outside to the inside of a CMOS chip, it is TTL
compatible. The TTL high logic level is only 2.4V and low
logic level is 0.4V. However, the CMOS level is 5V for high
FIG.4.2 A FUNCTION BLOCK DIAGRAM OF THE PD512 SYSTEM
CEB A4T-A9T A1 2T-A14T
AIHVPGMB
A l H V LGDISTB
INPUT BUFFER
i
CLOCK
A8,A13,A14
*
A6,A5,PL4 CLK7
CLK7B CL1C5 OEBT
A7,A9,A12 CL GHV (SB
'I
S DECODER
s o t s 7
r v
r R DECODER
'I 'I -
VPlSW
I V P I * ROfR7
I I 'I r r
XTDEC XTDEC
v XTNO-XTN7 XTNO-XTN7
70
logic level and OV for low logic level. An ordinary CMOS
inverter switches when the input voltage is about 0.5 VDD,
and the TTL switching threshold should be at 1.4V for a
typical process. CMOS input buffer circuits and layout are
shown respectively in Figs. 4.3 and 4.4. In addition, the
circuit simulation results and LVS results are shown in
Appendix B- 1.
b) R-decoder and S-decoder section
R-decoder and S-decoders include one Nand-3 and two
inverters. Inverter 1 is bigger for driving larger loads.
Figs.4.5 and 4.6 show the schematic and layout of R-decoder
and S decoder. The LVS result is shown in Appendix B-2,
there are six address lines to be fed into them, such as A8,
A13 and A14 for R-decoder and A4, A5 and A6 for S-decoder.
Their decoder schemes are shown below:
Fig.4.3 Schematic of a Input Buffer
&. fig. 4 - 4 :,ayout o f an Input buFfor ci t4~si t I
DRAWING RS DECODER RS DECODER LAST-MODlFlED=Fri Sep 28 13:17:31 1989
Fig. 4.5 Schematic of R- and S-decoder circuits
r . . - . . - ...- j--':, - - . . . . . . . :-.-j . . . . -- . . . . . .- , X ! . . . . . 7 ZJZZ $ ' . . . --" .. :"-. .I- -- . ., . . . . . . . . . , : i . . 1 .
. A
. . . . . . . -..-'"S ... .. -. .... f . 1- z-..-: ... .- . -..,
. . ' I , , . . . ' 4 ; . . A t ::;=
' 1 - . . .I ' . . . . \ . . - . ._ _ I ( ' : ; : i . ., ' '
. a , . + . - , ,.-+ - - . A ?".. * : 7 ..: : - d' :. . . . ... . . ! -. , . ! : j . . . I L-.:: .::3 , ,
! 2': I . - -.j . ...;. ..- . . .,-.I .. r ~ . -.! ; f . : { . . > : .'-'-i
. . . s t
; ( :. .i .- . -. ! .: . . . . . . ,"', -i 1' . , ;- ; ! , ;,.-$. :*& K i 3 - i , f i : , , ; ; : . , j- ! ..LI ,.... ... r .!. , :..;...,.: , ...... _ ..,.. $~ .,.-.. ,.... ., .. '
. ,' L . . . . . .
, .i- : ; ? . ! , a I ; . ! .!' :. : ..,J
' ' . . . . . . . . . . . :. a . i . + i--. -: ; . ;,, , : , . . , ;I . . . . . , ! , '--- .'. . ' ....... ;. . . . . . . . ^ ..!. .4 .... " :. j..! i1 1. . ,<.-! ' ~' I I , - , < * : . - . I '. . ,e .-";A : i
-..- -i .. . $ _ : - - .. 1.. . . . . . . ..., .>.. .., ... *. -- ..-; L.. . ' I > , ' i. . . . . ..; .) . .; ;,,. . . . ..*?
I , I <
....- .... , s ,..- .- ! - - .: . . I .- .., ,i .!.. : ..!. i. . ; ; . ; . . . . . : . , ;/' ,r ;- ! .--... -2
' / i *.. . . . . y'.,.- ;. ... ". ........ ; ...+ . , -. !. * .. i..; .. .-:$
8 , , , I , . < '. - .; - .; , . & - - . . . . . . . . . . *, ; --, :- .b ! if;!,/ .::
! : [... . d . ;;; . . . . . . . . . . . . . > t . ~ , , . * . ,,-& . . . . . . . . . c...' 4 . . . * , i ' .... -2 L / , ; . ,,;.+j; ;
f... -I , .. .{ .,/ '- . - . . . - . . . J . L..'.,...
;. . . , - i ,, i .: . ; . n il:2 '.. . . . .+i. , ,
r-1 ; .-*, , , I . ' I : , , . . I ! ; ! r$
, ' + ! I : i: ,,Yt]j ,,< : h , ; ? I , , I . . ' , : y - 4
1 ! , 4 8 , . . . . _ . . _ . .,I.. . . . ! . , 4 ' .
, l i , ' , ' , r i ' ! . i r \ , ,;,,;: [ ;
, . . . . ..: 5 .... - 1 :,r&q : ' A , 4 ; i 1 . : L l r , . :. ..... /J.- : - . j ,.$J, . r , { , 2 ' i , i : ,a, ; ; ; : f . - ; I , I ,
' ; pi: ;J-JI : , I I n ; : ; . , ,Mi: :l , , , , + ; t s ; i ; ' . ; i . F , :ai;; ,:.: ..;. :.7{..' .;... i... . , , ..&I: ' ,
> , . W* r- --.!. . < r3 t i , ; , >< ;-7j
1 . l k 4 ;
. ! 1 , , - -: . . ID{! ; ?f !;..$ . > . L - ; ! , , - , j ! : . : : @ ..",:i,.$ , :&I, ; . ' ;K;: , :bli,~gl;:;L.~ ,[u, : : ,13\iJ d., ; '7 ' . , , n : i , : , ! @ ! , ; , . . -1 . , ' ; ; u 3
i . . . ~ ire: 2 1 :,."! . . . . . . . . . $.p: "q [I! tu3; : Ll \,$ ; , ,r?l.qf I ? * L.. $,d:.-i L.. -. ,I S. ..+, . . . . . . . . .
..... i 'I . r af- l~n1.1 E O : > I , . i - . .r +
. , ........ / ,* . . . . . . . . . . . !~:~nE;iTrn n:l . : -;- "7 ;
i- f..
' 'd
S-Decoder O/P A6 A5 A4
SO 0 0 0
s1 0 0 1
S2 0 1 0
S3 0 1 1
S4 1 0 0
55 1 0 1
S6 1 1 0
57 1 1 1
c) XT decoder section (XTDEC)
The main purpose of XTDEC is to select the word lines
of EPROM cells. There are two modes for this circuit; one is
read mode, the other is program mode. In read mode, XTDEC
will put 5V on the selected word lines. In program mode
XTDEC will put 16V on the selected word lines. There are
eight inputs to be fed into XTEDC; VPI, CLK7, CLK7B, A9X,
A12XI A7XI GDISTB and GHVB. XTN and XTNB are the outputs of
XTDEC, VPI signal comes from VPISW circuit. A9X, A7X, and
A12X are from address buffers. GDISTB and GHVB are from MIS
and GHVBS. VPI will be 5V in read mode, and will be 12V in
program mode. CLK7 and CLK7B will be active in program mode
and inactive in read mode. A9X, A7X and A12 are select
signals. GDISTB and GHVB are logic signals. XTDEC circuit
simulation results are summarized below:
mode VPI CLK7 CLK7B GDISTB GHVB A7 ,A9 ,A12X XTN XTNB
read 5V inactive inactive 5V 5V 5V 5V OV
program 12V active active 5V OV 5V 15V OV
76
This circuit pumps XTDEC circuit from 9.822V to 15.75VI
and it takes just 500ns.
In addition, the schematic and layout are shown in
Fig.4.7 and Fig.4.8, respectively. Refer to Appendix B-3 for
the complete XTDEC Spice simulation and LVS result.
d) VPI switch section(VP1SW) :
VPISW circuit is capable of switching VPI from 5V to
12V. VPI will supply 5V to XTDEC in read mode, and 12V to
XTDEC in the program mode. There are 4 inputs and 1 output
in VPISW; OEBT, GHV, CLK5, CLK5B and VPI. OEBT is external
pin, and it is TTL low(0.4V) in the read mode and 12V in the
program mode. CLK5 and CLK5B are active in the program mode
and inactive in the read mode. The function of CLK5 and 5B
are to pump the device 29p1s gate voltage to 12V. The spice
circuit simulation results for VPISW are summarized below:
mode OEBT GHV CLK5 CLK5B VPI
read VIL(O.4V) 0 inactive inactive 5V
program 12V 5V active active 12V
Fig.4.9 and Fig.4.10 shows the VPISW schematic and
VPISW cell layout. VPISW Spice simulation and LVS results
are shown in Appendix B-4.
e) CLOCK section:
The CLOCK circuit will produce four important output
signals; CLK7, CLK7B, CLK5 and CLK5B. CLK7 and CLK7B are fed
into XTDEC, and CLK5, 5B are fed into VPISW. The main
Fig.4.7 Schematic of a XTDEC circuit
Fig.4.9 Schematic of a VPISW circuit
81
purpose of the four signals is to pump circuits from 5V to
12V when circuits need a higher voltage. The CLOCK circuit
also as four inputs; VPI, AlHV, AIHVPGMB and LGDISTB. VPI
signal comes from VPISW circuit. AlHV is from address buffer
one (Al), when A1 is supplied a high voltage, AlHV will go
to 5V. Otherwise, AlHV will always be OV.
The spice circuit simulation results for the CLOCK
circuit are summarized below:
mode VPI AIHV AIHVPGWB LGDISTB CLK7.7B CLK5.5B
read 5V OV 5V 5V active active
program 12V OV OV 5V active active
In addition, the schematic and layout are shown in
Fig.4.11 and 4.12, respectively. Refer to Appendix B-5 for
the complete clock Spice simulation and LVS results.
a3
Fig.4.11 Schematic of a CLOCK circui
c x A P T m 5. CONCLUSION
The purpose of this thesis was to install an advanced
CMOS technology, layout versus schematic system (LVS), and
develop a design example (PD512). The thesis objective is
achieved in these three parts.
A new 1.8micron n-WELL CMOS EPROM process technology is
used to upgrade Valid workstation from nMOS to CMOS. In
general, the process for memory chips is more complex than
the process for logic chips. For logic chips, this process
can be reduced several steps such as cell implant, polyl
deposition, and polyl etch. This process provides two layers
of connections: one is a poly2 layer, the other is a metal
layer. If a designer needs one more layer for connections,
the designer can use polyl. This means, the polyl deposition
will be needed. Developing DRC program is very important
work in VLSI design. It must be able to find the violation
of a layout, because DRC violation will cause a failure
design. Some DRC false errors may be produced by DRC
program. These false errors can be eliminated by modifying
the DRC program.
In order to make the old SCALD system COMPARE version
1.3L operating, the author had to use the spice library to
set up a CMOS library. With this work, the designer will be
able to verify the layout of chips. The successful chips
will be determined by the correct layout. In general, the
verification of the layout includes the device size and
85
connectivity checking. The version 1.3L COMPARE is only able
to check the device connectivity. Further improvements for
device size checking may be made in the future if the old
COMPARE version is upgraded to new the version.
In Chapter 4 of this thesis, the author demonstrates
the phases of a semiconductor product development process by
developing a 512k predecoder called PD512. The author has
focused on the following product development stages.
a) New product release procedures
b) CMOS poly gate process architecture development
c) Design and simulation of the key functional blocks
REFERENCE
Neil Weste and Kamran Eshraghian, ttPrinciples of CMOS
VLSI Design - A Systems Perspectivett, Addison-
Wesley, Inc., 1985.
Amar Mukherjes, ttIntroduction to nMOS & CMOS VLSI
Systems Designtt, Prentice - Hall, 1986. Robert H. Hayes and Steven G Wheelwright "Linking
Manufacturing Process and Product Life Cyclestt,
Harvard Business Review, January 1981.
D. Hodges and H. Jackson, ttAnalysis and Design of
Digital Integrated circuittt MCGrow Hill, New York,
1983.
T. Frederiksen, "Intuitive IC CMOS Evolutionlt ,
National Semiconductor Technology Series, 1984.
P. Allen and D. Holberg, ttCMOS Analog Circuit
Designw, Holt, Rinehart and Winston Inc. New York,
1988.
J. Maver and P.B. Denyer, "Introduction to MOS LSI
Designw, Addition Wesly, Reading, Massachuselts,
1983.
ItLayout EDITOR Reference Manualts, Valid logic
systems, Incorporated, California, 1986.
Paul Richman, "MOS Field-Effect Transistors and
Integrated Circuitstt.
Masakazu Sroj it "CMOS DIGITAL CIRCUIT TECHNOLOGYIt ,
87
PRENTICE HALL, INC., NJ, 1988.
11. Dewitt G. Ong, "MODERN MOS TECHNOLOGYn, Mcgraw-Hill,
Inc, 1984.
12. Punknell. Eshraghian, "Basic VLSI Design-Systems and
circuit^^^, PRENTICE HALL, 1988.
13. "SCALD Language Valid COMPILERw, Valid Logic Systems,
INC., California, 1986.
14. "Layout VerificationI1, Valid Logic systems INC.,
California, 1986.
APPENDIX A
A - 1 CMOS color map f i l e
0 0 0 0 193 190 248 1 5 246 0 2 228 171 17 3 13 21 250 4 140 80 150 5 52 60 250 6 110 110 180 7 255 255 0 8 200 80 80 9 60 170 0 10 140 100 40 1 1 49 89 240 12 120 80 150 13 80 127 100 14 100 85 105 15 239 0 0 16 120 100 0 17 235 130 0 18 100 80 0 19 108 127 1 1 7 20 100 80 0 21 150 197 0 22 100 80 0 23 150 130 0 24 110 90 0 25 150 130 0 26 100 80 0 27 150 130 0 28 100 80 0 29 150 130 0 30 100 80 0 31 255 255 255 32 100 100 100 33 0 255 255 63 255 255 255 127 243 249 247 128 200 200 200 129 250 0 0 130 255 180 120 131 250 250 250 132 250 0 0 191 255 255 255 192 3 3 3 250 255 255 255 251 0 180 0 252 200 200 200 253 255 255 255 254 0 240 0 255 -6 -6 -106 256
A - 2 CMOS technology f i l e
888 100 0.10 2 po ly l 0 s o l i d 1 "wire-width" = "2" " p r e f i x " = "PI:" , pf f f f f s t i p p l e 2 0 1020 2040 0 0 808 404 0 0 2020 4040 0 0 404 202 0 "wire-width" = "2"
n a c t i v e 0 s o l i d 2 "wire = "2" Wprefix" = " "
metal 0 s o l i d 4 n u i r e = " 2 " "pre f ix" = " M : "
p a c t i v e 0 s o l i d 8 "wire-width" = "2" " p r e f i x " = " "
poly2 0 s o l i d 16 "wire-width" = "0.6" " p r e f i x " = "P2:" , c o n t a c t f f f f c r o s s 32 "wire-width" = "2" " p r e f i x " = " "
d e p l e t i o n f 9 f 9 empty 16 "wi re -wid th" = " 2 " " p r e f i x " r " "
nwell c5c5 empty 8 "wire width" = "2" " p r e f i x " = " " , c e l l f0 f0 empty 4 "wire widthn = "2" " p r e f i x n = "" , pad i f 0 0 empty 16 9
s a c i f f f empty 16
a c t i v e f f f f . t i p p l e 4 240 240 240 420 810 1008 c007 0 0 c007 1008 810 420 240 240 240 , pplus f f f f s t i p p l e 8 101 202 404 808 1010 2020 4040 8080 101 202 404 808 1010 2020 4040 8080 > nplus f f f f s t i p p l e 16 f f f f O O O O O O O f f f f O O O O O O O
hvim f f f f s t i p p l e 2 101 202 404 808 1010 2020 4040 8080 101 202 404 808 1010 2020 4040 8080
mhvim f f f f s t i p p l e 8 f f f f O O O O O O O f f f f 0 0 0 0 0 0 0
p f i e l d f f f f s t i p p l e 1 240 240 240 420 810 1008 coo7 0 0 coo7 1008 810 420 240 240 240
e r r o r s f f f f s t i p p l e 8 0 1020 2040 0 0 808 404 0 0 2020 4040 0 0 404 202 0 .
networks fff stipple 34 0 606 606 0 0 6060 6060 0 0 606 606 U 0 6060 ti060 0
boundary ffff eeptv 36 "cif name" = "L BND1"
pin-.area ffff stipple 38 1 2 4 8 10 20 40 80 100 200 400 800 1000 2000 4000 B O O 0 "cif name" = "L B N D 2 "
terminal ffff cross 39 "cif-name" ="L TRH"
maskout fff stipple 33 ECCC CCCC 3333 3333 CCCC CCCC 3333 3333 CCCC CCCC 3333 3333 CCCC CCCC 3333 3333 cif-name" = "L MA"
A-3 CMOS design rules
1.0 Purpose:
To define a set of design rules for 1.8 micron N-WELL
CMOS EPROM process technology. The rules are capable of
handling up to 10% linear shrink.
2.0 Drawn layers:
Layer name Description GDS layer
n-WELL 1
Active Both n+ and p+ diffusion 41
N Active n+ diffusion region 2
P Active p+ diffusion region 12
Cell Implant EPROM cell threshold adjustment 5
Poly I Used as the floating gate 6
Depl Implant To open up depletion transistor 7
Poly I1 Control gate and peripheral gate 11
SAE Etch protection during self align 42
poly etch
P+ Implant Open up p diffusion area
Contact
Metal
Pad
3.0 Remaining layers:
Layer name Description GDS layer
Active Merge of n active and p active 41
P-f ield Oversizing n-WELL by 3.5u/side 21
N+ Implant Same data as P+ Implant 14
4.0 Mask set required and alignment sequence:
Mask name
n-WELL
Active
p-f ield
Cell implant
POLY I
Depletion implant
POLY I1
SAE
n+ implant
p+ implant
Contact
Metal
Pad
P.R. Field
D
C
C
D
C
D
C
D
C
D
D
C
D
Align to
major flat
1
1
5.0 Generalized layout rules
Assumption:
5.0.1 The drawn dimension equals the physical
dimension on the wafer. There is dimension
skew for some layers to compensate for
process/etching bias.
5.0.2 Direct misalignment on stepper---------- 0 . 5 ~
Indirect misalignment on stepper-------- 0 . 7 ~
5.0.3 All units listed below are in microns.
5.0.4 Design greater than the minimum is
preferred, whenever a more conservative
layout will not impact the chip size.
5.0.5 Any deviation from these design rules must
be fully documented for review at the time
of the composite review.
5.1 N-WELL LAYER
5.1.1 Minimum width 5.1.2 Minimum spacing
N-WELL
N-WELL
5.2 ACTIUE LAYER
5.2.1 Minimum width 5.2.2 Minimum spacing
5.2.2.1 Low voltage 5.2.2.2 High voltage 5.2.2.3 Medium high voltage
5.2.3 N+ diffusion outside well to well 5.2.4 N+ diffusion inside well to well 5.2.5 P+ diffusion outside well to well 5.2.6 P+ diffusion inside well to well
I : t I I
I I I I
LOW 5.2.2.1 I I L..\.....=.........I
High 5.2.2.2 Medium 5.2.2.3
5.3 CELL IMPLANT LAVER
5.3.1 Minimum ouerlap of POLY 2 gate 1 .O
5.3.2 Minimum ouerlap of diffusion (ACTIUE) 2.0
5.3.3 Minimum spacing to unrelated diffusion 2 .O
AGUOVE
\/
1 I
POLY 2
*\ IMPLANT
YYYYY
5.381 ; Y I Y
Y
Y
le, X
8 5.3.2 Y
Y Y Y l Y Y Y Y Y Y Y Y Y Y Y Y Y Y l Y Y Y l l Y l Y
~YYYYYY.Y'!YYYYYYYY.LYYY!'YYY.YYYY
5.4 POLY 1 LAYER
5.4.1 Minimum gate length for natiue transistor 5.4.2 Minimum spacing 5.4.3 Minimum POLY I extension onto field 5.4.4 Minimum spacing of POLY I on field to
unrelated diffusion 5.4.5 Minimum spacing of extended POLY I onto
field to diffusion 5.4.6 Minimum ouerlap of diffusion at drain side
in memory core 5.4.7 Minimum diffusion extension from POLY I 5.4.8 Minimum ouerlap of channel in core 5.4.9 Minimum POLY I width
. . ~ C T I UE POLY I-r 'x .. .*\
C A E
5.5 DEPLETION IMPLANT LAYER
5.1.1 Minimum oveerlap of gate in the direction of current flow 2 .O
5.5.2 Minimum spacing to unrelated diffusion 2.0
POLY 2
5.6 POLY2 LAYER 5.6.1 Min imum gate leng th
5.6.1.1 Low vol tage and core 5.6.1.2 High uo l tage
5.6.2 Min imum spacing 5.6.3 Min imum POLY2 extension on to f i e l d 5.6.4 Min imum spacing f r o m POLY2 on f ie ld
t o unre la ted d i f fus ion 5.6.5 Min imum spacing f r o m end cap t o
unre la ted d i f fus ion 5.6.6 Min imum over lap o f d i f fus ion 5.6.7 Min imum POLY2 w i d t h
5.7 ETCH PROTECTION LAYER
5.7.1 Minimum spacing t o c o r e POLY I I
5.7.2 Minimum spacing t o core POLY I
Y I
POLY 2
I E 7 C ) Y. . .L
5.8 P+ IMPLANT L A Y E R
5.8.1 Minimum overlap on P+ diffusion 1.4
5.8.2 Minimum spacing to N+ diffusion 1.4
IMPLANT
5.9 CONTACT LAYER
5.9.1 Minimum contact size 5.9.2 Minimum spacing 5.9.3 Minimum ouerlap of diffusion
5.9.3.1 Peripheral 5.9.3.2 Core
5.9.4 Minimum spacing from diffusion contact to gate
5.9.5 Minimum ouerlap to : 5.9.5.1 POLY I I 5.9.5.2 POLY I without POLY l l cross 5.9.5.3 POLY I with POLY I I cross
5.9.6 A l l POLY contact location field oxide only
5.1 0 METAL L A Y E R
5.1 0.1 Minimum width
5.1 0.2 Minimum spacing
5.10 3 Minimum ouerlap o f contact
METAL &
POL
5.1 1 PAD L A Y E R
5.1 1.1 Minimum size 100~100 5.1 1.2 Minimum overlap to metal 5.0 5.1 1.3 Minimum spacing 110 5.1 1.4 Minimum spacing from pad metal to
scribe lane 30 5.1 1.5 Minimum spacing from pad metal to
unrelated metal 20 5.1 1.6 Minimum spacing from pad metal to
diffusion and poly 15
S C R I B E LANE
I
METAL I
DIFFUSION
A - 4 The Extract and DRC program
(512K EPROM 11/88) { E x t r a c t command f i l e f o r 1.8 m i c r o n CMOS p r o c e s s ) {
11 /14 /88 YR change p2nga te n o t i n c l u d i n g p o l y l add badpga te check
1
< < f i l e s > > use epa l .w rk
< < l a y e r s > > p a c t i v e a c t i v e n a c t f ve d e p l e t i o n ~ 0 1 ~ 1 p o l YZ meta 1 PP 1 us nwel 1 c o n t a c t P f pad p f i e l d
{ i n t e r m e d t a t e LAYERS > P 4 nenh penh ndep n a t v n g a t e p 1 n g a t e p2nga te p 9 a t e psubcon t nwe 1 1 c o n t P sd nsd badpga te s u b s t r a t e c r e a t e g t n
< < h i e r a r c h y >> {
r e a d - c o v e r - f i l e 1
d r f t n e g t n c r e a t e g i n = b o u n d a r y andno t (boundary expand - 4 0 . 0 ) pfn-areampin-area o r c r e a t e g l n
analysis-name " e x t r a c t " keep-updated don t - r eana l yze f l a t - ce l l - name " * "
{ I gno re - subce l l " d r a m c e l l " f l a t - c e l l - s t z e 6 .0
donu t -s i ze 12.0 c o n s o l t d a t e edge-1 i m i t 300000
p r e f i x " M : " meta 1 p r e f i x "PZ:" ~ 0 1 ~ 2 p r e f t x "NA:" nsd p r e f i x "PA:" psd p r e f i x " P l : " ~ 0 1 ~ 1
p l n g a t e = ( p o l y l and a c t i v e ) andno t n w e l l p2ngate= ( ( p o l y Z andno t p o l y l and a c t i v e ) andno t n w e l l n a c t i v e = a c t i v e andnot p p l u s nga te=p loyZ and n a c t i v e ndep=ngate and d e p l e t i o n nenh=ngate andno t d e p l e t i o n n s d = n a c t i v e andnot n g a t e p a c t i v e = a c t i v e and p p l u s p g a t e = p o l y 2 and p a c t i v e p e n h r n w e l l and p g a t e p s d = p a c t i v e andno t p g a t e ( ndep= p2nga te and d e p l e t i o n nenh= p2nga te andnot ndep n a t v = p l n g a t e andnot d e p l e t i o n n s d l a c t i v e andno t ( p l n g a t e o r pZnga te )
p g a t e = ( a c t i v e and p o l y 2 ) and n w e l l penh= (pga te and n w e l l ) andno t p f p4 = ( p g a t e and n w e l l ) and p f p s d = a c t i v e andno t p g a t e > ~ s u b c o n t = ~ ( a c t f v e andno t n w e l l ) and c o n t a c t n w e l l c o n t = ~ n w e l l and a c t i v e ) and c o n t a c t
( t o u c h s u b s t r a t e ) t o u c h s u b s t r a t e psubcon t t o u c h n w e l l n w e l l c o n t t o u c h c o n t a c t me ta l p o l y l p o l y 2 psd nsd
t o u c h m e t a l psubcon t n w e l l c o n t
transistor NMOS NENH nenh nsd p o l y 2 s u b s t r a t e t r a n s i s t o r NMOS NDEP ndep nsd p o l y 2 s u b s t r a t e t r a n s i s t o r NMOS NATV n a t v nsd p o l y l s u b s t r a t e t r a n s i s t o r PMOS PENH penh psd p o l y 2 n w e l l t r a n s i s t o r PMOS P 4 p4 psd p o l y 2 n w e l l
< < checks > > < < end > >
< < f i l e s > > use eprom512.wrk
< < l a y e r s > > p a c t i v e n a c t i v e d e p l e t i o n ~ 0 1 ~ 1 p o l Y Z meta 1 nwel 1 c o n t a c t pad hv im mhv i m
i n t e r m e d i a t e LAYERS 1 pimp11 pimp12
P O ~ Y ~ 0 1 ~ s e r r o r - l a y e r spa ana a c t i v e h v a c t n o t h v a c t mhvact notmhvact 1 v a c t mhvnac dumact nwpp 1 us nwnp 1 us PWPP 1 us pwnp 1 us s b a c t 1 ve nwnsd nwpsd pwnsd pwpsd
ga te1 ga teb ga te2 hvga te g a t e depgate nwgate pwgate nga te p g a t e badngate badpga te l badpgate2
ncon t p c o n t p 1 c o n t p 2 c o n t meta 1 c o n t n o t p o l y c o n t n o t m e t a l c o n t n o t a c t c o n t p o l y c o n n e c t
< < hierarchy > > def i n e g i n ignore-multiple "VCC. ignore~rnultiple " V S S " ignore-multiple "VPP"
< < extract > > {Operation for isolation^ donut-size 2 0 . 0
(checks-only)
prefix " P 2 : " ~ 0 1 ~ 2 prefix " M i " metal
get-subcell-data nactive get-subcell-data pactive get-subcell-data polyl get-subcell-data poly2 get-subcell-data metal get-subcell-data contact get-subcel 1-data nwel 1 keep-updated
{nsd and psd in nwell and pwell a r e seperately deflned 1 poly=polyl or poly2 ana-nactive andnot (pactfve expand 1.4) apa-active and (pactive expand 1.4) nwnplus=ana and nwell nwpplus-apa and nwell nwgate=polyZ a n d (nwnplus or nwpplus) nwnsd=nwnplus andnot nwgate nwpsd=((nwell and active) and (pactive expand 1.4)) andnot nwgate
pwnplus=ana andnot nwnplus pwpplus=apa andnot nwpplus pwgate=poly2 and (pwnplus or pwpplus) pwnsd=pwnplus andnot pwgate pwpsd=pwpplus andnot pwgate
poly=polyl or poly2 notpolycont=contact andnot poly
polys=polyl and (poly2 expand 1.0)
touch contact metal nwnsd nwpsd touch contact metal pwnsd pwpsd
(
touch contact metal mhvact notmhvact touch contact metal hvact nothvact touch contact metal notactcont active
t o u c h contact meta 1 notpol ycont pol y touch polys polyl
edge-spacfng nwnsd nwpsd 2.8 error-layer different-node report-edge error-layer 'nwnplus t o nwpplus a t diff n o d e SPACING < 2.8. e d g p s p a c i n g pwnsd pwpsd 2.8 error-layer different-node report-edge error-layer 'pwnplus t o pwpplus a t diff node spacing <2.8' edge-spacing polys polys 5000.8 error-layer same-node report-edge error-layer '2 dlff poly2 touch t h e s a m e polyl - poly
( edge-spacing hvact nothvact 3.8 error-layer different-node report-edge error-layer 'hvacttve t o a11 actlve spacing a t dlff n o d e
edge-spacing mhvact notmhvact 3.8 error-layer different-node report-edge error-layer "mhvactive t o all active spacing a t diff n o d e
edge-spacing notactcont active 2.0 error-layer dffferent-node report-edge error-layer "contact t o active SPACING <2.0 different nodeg
edge-spacing notpolycont poly 2.0 error-layer different-node " report-edge error-layer "contact t o poly SPACING different node < 2.0"
1 < < checks > > analysis-name "drc" donut-size 20.0 defer-cell-edge overlap-max 150.0 edge-limit 300000 keep-updated
flat-cell-size 6.0 flat-cell-name " y l g r g " flat-cell-name "xtprg flat-cell-name "rsprg"
ignore-subcell "epromarray"
(Operation for isolation^ active = pactive or nactive anarnactive andnot (pactive expand-octagon 1.4) sbactive = active fnclude poly hvact=hvim and active nothvact=active andnot hvim mhvact=mhvim and active notmhvact=active andnot mhvact lvact=active andnot hvact mhvnac=mhvim and nactive dumact=active andnot mhvnac gatel-polyl and pwnplus gateb=poly2 and active gatezrgateb andnot gate1 hvgate=gate2 and hvact gate=gatel or gate2 depgate=(poly2 and depletion) and ana badngate=ngate and nwell badpgatelxpgate andnot nwell badpgate2zpgate and depletlon ngate=poly and ana pgate=poly and apa
pimpll=pactive expand-octagon 0 . 9 pimpl2=pactlve expand-octagon 2.6
ncont=ana and contact pcontoapa and contact plcont=polyl and contact p2cont=poly2 and contact metalcont=contact and metal
polyconnect=poly andnot actlve
notmetalcont=contact andnot metal notactcont=contact andnot active
{Design Rules Start f r o m here) (1.6 nwell check) error-edge-style width nwell 3 . 0 'nwell WIDTH < 3.0 ' (1.a) error-edge-style spacing nwell nwell 12.6 "nwell t o nwell SPACING < 12.0' C1.b)
(2.6 active check) error-box-style width active 1.8 'active WIDTH < 1.8' (2.a) error-edge-style enclosure nwpplus nwell 3.2 "pplus over nwell SPACING < 3.2 ' C2.d)
error-edge-style spacing pwpplus nwell 4.0 'pplus outside nwell to nwell SPACING < 4.0' C2.e) error-edge-style spacing pwnplus nwell 9.5 ignore-touching "nplus outside nwell to nwell SPACING error-edge-style spacing pwnplus nwpplus 12.7 *nplus in psub to pplus in nwell SPACING < 12.7"
{ 3.0 pfield no check)
{depletion check) error-box-style enclosure depgate depletion 2.0 "depletion to gate spacing < 2.0" error-edge-style spacfng depletion gate 2.0 ignore-overlaps "depletion to unrelated gate < 2 . 8 "
< 6.0 poly check) error-edge-style wfdth poly 1.8 "poly WIDTH < 1.8" {6.a) error-edge-style spacing polyl polyl 2.0 "polyl to polyl SPACING < 2.0" C6.b) error-edge-style spacing poly2 poly2 2.0 'poly2 to poly2 SPACING < 2.0" (6.b) error-edge-style edge-enclosure gate poly 2.5 error-layer ignore-touching ignort-outsfde report-edge error-layer "poly extension onto field WIDTH < 2.0 C6.f) error-edge-style spacing polyconnect actfve 6.2 fgnore-touchfng "poly on ffeld to active error-box-style width gate1 3.0 "polyl in gate WIDTH < 3.5" (6. ) edge-enclosure gate active 2.0 error-layer ignore-touching ignore-outslde error-edge-style report-edge error-layer "gate in active < 2.0" (6.f)
{ error-edge-style spacfng ngate pactive 2.1 "ngate to pactive SPACING < 2.1" 1
existence badngate "BADngate in nwelln existence badpgatel 'BADpgate outslde nwell" existence badpgate2 "BADpgate in depletionn
{contactact check? error-box-style width ncont 1.8 "nactive contact WIDTH < 1.8' {13.a) error-box-style width pcont 1.8 "pactive contact WIDTH < 1.8' {13.a) error-box-style width contact 1.8 "contact WIDTH < 1.8' <13.a) error-edge-style spacing contact contact 1.8 "contact to contact SPACING < 1.8' (13.b) error-box-style enclosure plcont polyl 1.0 'contact over polyl < 1.0' {13.e> error-box-style enclosure p2cont poly2 1.0 'contact over poly2 < 1.0' {13.e) error-box-style enclosure pcont apa 1.0 "contact overlaps with actual pactfve<lu ' error-box-style enclosure ncont ana 1.0 ignore-touchfng 'contact overlaps with actual error-edge-style spactng contact gate 2 . 0 *contact to gate SPACING < 2.9' {13.g> error-edge-style spacing notmetalcont metal 2.0 'contact to metal' SPACING < 2.0' C13.s)
{metal check) error-edge-style wldth metal 2.5 "metal WIDTH < 2.5" (l4.a) error-edge-style spacing metal metal 2.8 check-for-notch 'metal to metal SPACING < 2.8' C14.b) error-box-style enclosure metalcont metal 0.8 "contact over metal SPACING < 0.8' Zl4.c) < < end > >
A - 5 Spice parameters for simulation
Sk A h 1 P-{'HANkEL. . LIB FMODEL. EPH .MODEL P PMOS Fl=U. 14 kDEL.=U. 2 TOX-223 ES4T= 15. E4 MBL=O. 36 + LAMRL)A=3.7E-5 h b = I .U3 LDEL=-0.2 RD=470 RS=470 + VY=-U.65 C;..lMM4=U. 2 7 ' LIh-230 LATI)=O, 1 I.'DS=0.17 WIC=l MOE)=l + Ci,M=3 METO=U . 0 5 L D I F = , Z CF1-0.24 CF2=0.62 CF3=1 TR1)=2 .UE-3 + TRS=Z.OE-3 T C ' L = - 2 . i E - 3 REX=-1.3 + CJ.4=O.JE-I5 CJP=0.31E-15 EXAz0.5 EXPZ0.33 + ACM=Z PHl=0.6
SFAST ENHANCEMENT N-CHANNEL .MODEL N NMOS F1=0.12 WDEL-0.2 TOXs225 ESAT=S.4E4 MBLs0.32 VT=0.5 GAHMA=0.45 + LGAMMA=O.lI VBO=1.3 UB=710 LATDzO.1 FDSz0.92 LAMBDAz3.3E-5 + KU=1.21 LDEL=-0.2 RD=320 RS=320 WIC=l MOB=1 CLM=3 METO=0.05 + LDIF=2 CF1=0.12 CF2=0.52 CF3=1.36 + TRD=2.OE-3 TRS=2.OE-3 BEX=-1.3 TCV=2.2E-3 + CJA=0.07E-15 CJP=0.24E-15 EXAx0.48 EXP=0.27 + PHI=0.4 ACM=2
SFAST EhH4NCEYFNT N-CHANNEL .MODEL NC NMOS Flz0.12 WDEL=O.Z 1,OX-225 E S A I = ~ . ~ E ~ MBL=0.32 VTz2.0 GAMMA=O.45 + LGAMMA=U. 1 I \;BO=l. 3 ijB=710 LATD=O, I C'US=0.92 l,AHBUA=J. 3E-5 + KU=1.21 LDELr-0.2 RD=320 HS=320 kIC=l MOB=l CLM=3 METU=0.05 + LDIF=2 CF1=0.12 CF2=0.52 CF3~1.36 + TRD=2.OE-3 TRS=2.OE-3 BEX=-1.3 TCV=2.2E-3 + CJA=0.07E-15 CJP=0.24E-15 EXAz0.48 EXP=0.27 + PHI=0.4 ACM=2
SFAST ENHANCEMENT N-CHANNEL depletion .MODEL nD NMOS FlrO.12 WDELx0.2 TUX=225 ESAl=5.4E4 MBL-0.32 VT=-3.0 GAMHA=O.~~ + LGAMMA=O.lI VBO=1.3 UBt7lO LATDrO.1 FDSs0.92 LAMBDAz3.3E-5 + KU=1.21 LDEL=-0.2 RDs320 RS=320 WIC=l MOB=1 CLM=3 METO=0.05 + LDIF=2 CFl10.12 CF210.52 CF3-1.36 + TRD=2.OE-3 TRS=Z.OE-3 BEX=-1.3 TCV-2.2E-3 + CJAt0.07E-15 CJP=O.24E-15 EXA=0.48 EXP-0.27 + ACM=2 PHI=O.4
SFAST NMOS CELL modifv epalcell 3.2 /1.4 cellmodel .MODEL ERA NMOS PHIn0.29 VT-0.9 GAJ4MA=0.8 FDS=0.51 Flr0.031 ESAT=6.5E+4 + LAMBDA=2.2E-6 KLz0.08 F3=0.54 KA11.09 MBLz0.4 MAL=0.55 + KUs1.7 LATDt0.22 CLM=3 MOB=l WIC=l LDEL=-0.25 WDELz0.7 + BETA=30.8E-6 RS=320 RD1320 LDIF=3 + TRDr2.OE-3 TRS=P.OE-3 BEXI-1.3 TCVz2.2E-3
SFAST NMOS CELL modify epalcell 3.2 /1.4 cellmodel .MODEL PRO NMOS PHl=O.OY VTz6.0 GAMMA=O.8 FDSt0.51 F1=0.031 ESAT=6.5E+4 + LAMBb4-2.2E-6 KL=O.OB F3~0.54 KAtl.09 MBLrO.4 MALz0.55 + KU=]. 7 LA'FD=O.'LZ ('LM=.i MOb=l ~ J L ' - 1 LDEL=-0.25 kbEL=O. 7 + BETA=30.8E-6 RS=320 RDr320 LDIF=3 + TRD=2.OE-3 TRS=2.OE-3 BEX=-1.3 TCV12.2E-3 .ENDL FMODEL.EPR
SEPHOM FSMODEL . L 1 B FSMODEL. EPR $FAST P-CHANNEL .MODEL P PMOS Fl=O.lJ WDEL=0.2 TOX=225 ESAT=15.E4 MBLz0.36 t LAMBDA=3.7E-5 KU=1.03 LDEL=-0.2 RD=470 RS=470 + VT=-0.65 GAMMA=0.27,UB=230 LATDzO.1 FDSz0.17 VIC=l MOB=l t CLM=3 METO=O.O5 LDI'F=~ CF1=0.24 CF2~0.62 CF3=1 TRD=2.OE-3 t TRSz2.0E-3 TCV=-2.7.E-3 BEX=-1.3 + CJA=0.3E-15 CJP=0.37E-15 EXA=O.5 EXP=0.33 + PHI=0.6 ACM=2 SSLOW ENHANCEMENT N-CHANNEL .MODEI, N NMOS F l z 0 . 1 4 6 WI)k I . = - . 2 T O X = Z i 5 ESAT=.).8E4 MBL=O. 39 VTz0.9 GAMMAZO. 55 t LsGAMMA=O. 1 3 VRO=I. I UB=590 LATD=O. 1 FDS=O. 76 LAMBDA=2.7E-5 t IiU=1.01 LDEL=0.2 RD=400 RS=400 WIC=l MOB=I CLM=3 WETO=O,lS + LDIF=2 CF1=0.36 CF2=0.23 CF3=0.88 t TRDz2.OE-3 TRSs2.OE-3 BEX+-1.3 TCVs2.2E-3 t CJA=O.l3E-15 CJP=0.42E-15 EXA=0.42 EXP=O.21 + PHI=O. 6 ACM=2 s SSLOV ENHANCEMENT OFF-CELL .MODEL NC NMOS F1=0.146 WDEL=-.2 TOX=275 ESATr4.8E4 MBL=0.39 VT=6 GAMMA=0.55 + LGAMMA=0.13 VBO=1.1 UB=590 LATD=O.l FDSn0.76 LAWBDA=2.7E-5 + KU=1.01 LDEL=O.2 RD=400 RS=4OO WIC=l MOB=1 CLM=3 METO=0.15 + LDIF=2 CF1=0.36 CF2=0.23 CF3=0.88 + TRD=2.OE-3 TRS=Z.OE-3 BEXt-1.3 TCVz2.26-3 + CJAz0.13E-15 CJPn0.42E-15 EXA=O.42 EXPt0.21 + PHI=0.8 ACM=2
SSLOW ERASBLE CELL .MODEL ERA NMOS PHI=0.29 VT=1.2 GAMMAt1.2 FDS=O.41 F1=0.037 ESAT=6.1E+4 + LAMBDA=1.8E-6 KLzO.1 F3r0.44 KA=1.33 UBL=0.46 MALt0.45 + KU=1.5 LATD-0.18 CLM=3 MOB=l WIC=l LDEL=-0.21 WDEL=0.58 + BETA=28.8E-6 RS=4OO RDg400 LDIF=3 + TRD=2.OE-3 TRS=2.OE-3 BEXI-1.3 TCV=2.2E-3
SSLOW PROGRAM CELL .MODEL PRO NMOS PHI=0.29 VT=6.0 GAMMA=l.2 FDS=O.41 Pl=0.037 ESAT=6.lE+4 + LAMBDAz1.8E-6 KL=O.l F3=0.44 KA=1.33 HBL=0.46 ML10.45 + KUz1.5 LATDtO.18 CLM=3 MOB=l WIC.1 LDEL=-0.21 WDELr0.58 + BETA=28.8E-6 RS=400 RD=4OO LDIF=3 t TRD=2.OE-3 TRS=2.OE-3 BEX=-1.3 TCVz2.2E-3
SEPHOM . L l H SCMODbI . F P R SSLOk P-CHANYEL .MODEL P PMOS k1=0.18 kDEL=-0.2 TOXz275 ESAT=l 2.F4 MBI,=(J.44 + LAMBDA=J. 1E-5 Kb=1. 01 LDEI,=O. 2 RD=57O HS=570 + VT=-1.05 GAMMA=0.33 UB=190 LATDz0.1 FDSz0.13 WLC=I MOB=1 + CLM=3 METO=O.l5 LDIF.2 CFls0.48 CF2=0.38 CF3~0.76 TRD=Z.OE-3 + TRS=2.OE-3 TC\=-2.7E-3 BEX=-1.3 + CJAz0.36E-15 CJP=0.49E-15 EXA=0.47 EXPZ0.27 1
t ACM=2 PHI=l SFAST ENHANCEMENT N-CHANNEL .MODEL N NMOS F1~0.12 kDELz0.2 TOX=225 ESAT=5.4E4 MBL=0.32 VTz0.5 GAMMA=0.45 + LGAMMA-0.11 VBO=1.3 UB=710 LATDzO.1 FDSz0.92 LAMBDAz3.3E-5 + KU=1.21 LDEL=-0.2 RD=320 RS=320 WIC=I MOB=l CLM=3 METO=0.05 + LDIF=2 CFlz0.12 CF2=0.52 CF3=1.36 t TRD=Z.OE-3 TRS=2.OE-3 BEX=-1.3 TCVz2.2E-3 t CJA=0.07E-15 CJP=0.24E-15 EXA=0.48 EXPz0.27
t t ACM=2 PHI.0.4 SFAST ENHANCEMENT OFF-CELL .MODEL NC NMOS F1=0.12 WDEL=(J.2 TOX=225 ESATz5.4E4 MBLz0.32 VT=6 GAMMA=0.45 , + LGAMMA=O.ll VB011.3 UB=710 LATD=O.l FDSz0.92 LAMBDAz3.3E-5 t KU=1.21 LDEL=-0.2 RD=320 RSs320 WIC=l MOB=l CLM=3 METO=0.05 t LDIF=2 CF1=0.12 CF2=0.52 CF3=1.36 + TRDz2.OE-3 TRS=2.OE-3 BEX=-1.3 TCV=2.2E-3 t CJA=O.OIE-15 CJP=0.24E-15 EXAz0.48 EXP10.27 + ACM=2 PHIz0.4 SFAST ERASBLE CELL .MODEL ERA NMOS PHI=0.29 VT=0.9 GAMMA=0.8 FDS=0.51 F1=0.031 ESAT=6.SE+IS t LAMBDA=2.2E-6 KL=O.O8 F3i0.54 KA=1.09 MBL=0.4 MAL=0.55 t KUrl.7 LATDz0.22 CLM=3 MOB=l WIC=l LDEL=-0.25 WDEL=0.7 t BETAr30.8E-6 RS=320 LDIF=3 + TRDz2.OE-3 TRSs2.OE-3 BEXI-1.3 TCVz2.2E-3
SFAST PROGRAM CELL .MODEL PRO NMOS. PHIr0.29 VT=6,0 GAMMA-0.8 FDS-0.51 F1=0.031 ESAT=6.51+4 + LAHBDA=2.2E-6 KL=O.OB F3-0.54 KArl.09 MBLzO.4 MALs0.55 + KUtl.7 LATDs0.22 CLM-3 W B = l WIC=l LDEL=-0.25 WDELo0.7 + BETAz30.8E-6 RS=320 LDIF-3 + TRDz2.03-3 TRS=2.OE-3 BEXI-1.3 TCV=2.2E-3
. ENDL SFHODEL. EPR s
STYPI C'4L P-CHANNEL . Ll tc TMODEI, . EPH . MC)DE.I, P PMOS Fl=U. 16 WDEL=O. 'T'0.\=25U ESAl'=13.5E4 MB1,=0.4 + LAMBDAr3.4E-5 KU=l.U2 LI)EL=O. RL)=SZO RS=520 t iT=-0.85 GAMMA=0.3 UB=210 LATDzO.1 FDSZO.15 WIC=l MOB=1 + CLH-3 METO=O.I LUlFsZ CFlz0.36 CF2~0.5 CF3~0.88 TRDz2.OE-3 + TRSz2.0E-3 TC\=-2.7t'-3 HEX=-1.3 + t'JA=O. .(3E-15 CJP=O..LJE-I5 EXAZ0.5 EXP=O.3 + ACH=Z PHI=O. 8 S + LMLT=0.9 WMLT-0.9
ENHANCEMENT N-CHANNEL NMOS Flz0.133 WDEL=O 1'O.Y=250 C:SU"5.1E.I MBL=0.355 VTz0.7 GAHNA=0.5
LGAMMA=O.l2 VBOz1.2 UB=650 LATDzO.1 FDSz0.84 LAMBDAz3E-5 KU=l.l LDEL=O RD=dtiO RS=360 WIC=1 MOB=l CLM=3 METO=O.l LDIF=2 CF1=0.24 CF2=0.4 CF3=1.12 LMLT=O .9 WMLT=O. 9
TKr1=2.0E-3 TRS=2.OE-3 BEX=-1.3 TCVz2.2E-3 CJA=O.lE-15 CJPz0.39E-15 EXA=O.45 EXPz0.24 ACM=2 PH1=0.6
STYPICAL ERASEABLE CELL .MODEL ERA NMOS PHI=0.32 VT=1.05 GAMMA=1.0 FDS=0.46 F1~0.034 ESAT=6.3E+4 t LAMBDA=2.0E-6 KL=0.09 F3=0.49 KA=1.21 MBLz0.43 UAL=0.5 + KU=1.6 LATD=0.2 CLM-3 MOB=1 WIC=l LDEL=-0.23 WDELr0.64 - t BETA=29.8E-6 RS=360 RD=360 LDIF=3 + TCV=2.OE-3 TRD=2.OE-3 TRSz2.OE-3 BEX=-1.3
STYPICAL PROGRAMMING CELL .MODEL pro NMOS PH1=0.32 VT=6v GAMMA=l.O FDS=0.46 F1=0.034 ESAT=6.3E+4 t LAMBDA=2.0E-6 KL=0.09 F3=0.49 KA=1.21 MBL=0.43 NALz0.5 + KUz1.6 LATDz0.2 CLM=3 HOB=I,WIC=l LDEL=-0.23 WDELz0.64 + BETAz29.8E-6 RS=360 RD=360 LDIF=3 + TCVz2.OE-3 TRD-2.OE-3 TRS-2.OE-3 BEX=-1.3
STYPICAL DEP N-CHANNEL CELL .MODEL ND NMOS F1=0.02 WDEL=-0.14 TOX=250 ESAT=2.3E4 NBLo0.26 VT=-2 G A M W A = O . ~ ~ i LGAMMA=0.3 VBO=1.53 UB=560 LATDzO.1 FDSz1.37 LAMRDAz3.7E-6 + KU=l.l LDEL=O RD=360 RS=360 WIC=I MOB=l CLM=l HETO=O.l t LDIF=2 CF1=0.24 CF2=0.4 CF3s1.12 + TRD=2.OE-3 TRS=2.OE-3 BEX=-1.3 TCVs2.2E-3 t CJA=O.lE-15 CJP=0.33E-15 EXAr0.45 EXP=0.24 t ACM=2 PHI=0.36 . ENDL TNODEL. EPR
SSl,Ok P-CH4NNE1, . L i H SMOUt L. EPH .MODLI. P PMOS Fl =O. 18 !dI,EL=-0.2 7OX=275 E,dr\7'=12. E4 MBLzO. 44 t LAMBUA=J. IE-5 k U = 1 .01 LDEL=0.2 HD=570 RS=570 t VT=-1.05 GAMMA=0.33 UB=lYU LA'I'D=O.I FDS=U.13 WIC=1 MOB=1 t CLM=3 MFTO=0.15 LDIF=Z CFl=O.IH CF2~0.38 CF3~0.76 TRD=Z.OE-3 t TRSz2.OE-3 TCV=-2.7E-3 BEX=-1.3 t CJA=0.36E-15 cJP=0.49~-15 ExA~0.47 EXPz0.27 t ACH=2 PHI=0.8
SSLOW ENHANCEMENT N-CHANNEL .MODEL N NMOS F1=0.146 WDEL=-.2 TOX=275 ESAT=4.8E4 MBL=0.39 VT=0.9 GAMMA=0.55 t LGAMM4=0.13 VBO=l.l UH=590 LATDzO.1 FDSz0.76 LAMBDAz2.7E-5 t KU=1.01 LDEL=O.2 RD=400 RS=400 UIC=l MOB=l CLM=3 HETO=0.15 + LDIF=2 CF1=0.36 CF2=0.23 CF3=0.88 + TRD=2.OE-3 TRS=2.OE-3 BEX=-1.3 TCV=2.2E-3 t CJAz0.13E-15 CJP=0.42E-15 EXA=0.42 EXP=0.21 t ACM=2 PHI =O. 6
SS1,OU ENHANCEHENT N-CHANNEL FOR OFF CELL .MODEL ND NMOS F1~0.146 WDEL=-.2 TOXz275 ESAT=4.8E4 MB1,=0.39 VT=-2.0 t GAMMA=O. 55 t LGAl(nA=0.13 VBO=1.1 UB=590 LATD=O.~ FDS=0.76 LAMBDA=2.7E-5 + KU=1.01 LDEL=0.2 RD=400 RS=400 WIC=1 MOB=l CLM=3 METO=0.15 t LDIF=2 CFl=O.Q6 CF2~0.23 CF3~0.88 t TRD=2.OE-3 TRS=2.OE-3 BEX=-1.3 TCV=2.2E-3 t CJA=0.13E-15 CJP=0.42E-15 EXA=0.42 EXP=O.21 + ACM=2 PHI=O.6
SSLOW ERA CELL .MODEL ERA NMOS PBI=0.35 VT=1.2 GAHMA=1.2 FDS=0.41 Fl=0.037 ESAT=6.lE+4 + LAMBDAz1.8E-6 KLzO.1 F3=0.44 KA=1.33 HBLsO.46 MAL10.45 + KU=1.5 LATDrO.18 CLMz3 UOBrl WlC=l LDEL=-0.21 WDEL10.58 + BETAs28.8E-6 RS=4OO RD=4OO LDIF=3 + TCVs2.2E-3 BEX=-1.3 TRD=P.OE-3 TRSz2.OE-3
SSLOW PRO CELL .MODEL PRO NMOS P H I ' = o . ~ ~ VT=6.0 GAMMAsl.2 FDS=0.41 Flr0.037 ESAT=6.1E+4 + LAMBDA=l.EE-6 KLtO.1 F3r0.44 KA=1.33 MBLtO.46 WLx0.45 + KU11.5 LATDz0.18 CLH=3 UOB=l WIC=l LDEL=-0.21 WDELs0.58 + BETA=28.8E-6 RS=4OO RD=4OO LDIFr3 + TCV12.2E-3 BEXI-1.3 TRDt2.OE-3 TRSs2.OE-3
. ENDL SMODEL. EPR
APPENDIX B
B-1 The circuit simulation results and LVS results of a
input buffer circuit
****** h s p t c e 8807a 2:11:14 27-Jan89 u n 1 x ****** c o p y r i g h t 1988 m e t a - s o f t w a r e , l n c . * * * * * s l t e : e l i t e ***** r a b u f * * * * * * i n p u t l i s t i n g * * * * * * . o p t i o n p o s t aspec . w i d t h ou tm80
.model c j n d cja.0.1 cjp.0.33 e x r = 8 . 4 5 exp=#.24 p h t - d . 6 v c c 9 0 5 % ceb 7 $ a n t 1 0 S anb 8 % a n 6 v7 7 11 p u ( 5 0 Sns 2ns 2ns 80ns 90ns ) v l 0 10 11 p u ( 0 . 8 2.4 l 0 n s 2ns 2ns 20ns 4 0 n s ) vsub 5 0 0 v s s 11 0 0 . t r a n I n s 80ns . t e m p 25 . p l o t t r a n v ( 7 ) ~ ( 1 0 ) v ( 8 ) v ( 6 ) m l 1 0 11 11 5 nenh wr58.8 1-4 m2 3 2 11 5 nenh ~ ~ 3 . 0 l e 1 . 8 m3 4 3 11 5 nenh wa15 1 ~ 1 . 8 m4 6 4 11 5 nenh w.75 1=1.8 m5 9 2 3 9 penh w = l 0 1-1.8 m 6 8 3 11 5 nenh w.75 1.1.8 m 7 9 3 4 9 penh w=20 1-1.8 m8 9 4 6 9 penh w a l l 0 1-1.8 m9 9 3 8 9 penh w=140 1 ~ 1 . 8 m l 0 2 10 11 5 nenh w=100 113 m l l 2 7 11 5 nenh w-10 1-1.8 m12 12 1 0 2 9 penh w.25 113 m13 9 7 12 9 p e n h w=30 113 .end
SCALDsystem COMPARE Ver 9.2 SUN3-P1 (Tue Mar 15 01:08:49 PST 1988).
Processing rabuf.lyout
Processing rabuf.sptce
Generattng Body Table
rabuf.lyout BODYTABL E - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
Name Number Name Number ---------------------------------------------------------------------------.
Num Of Bod tes Num Of Sfgnals
Comparing rabuf.lyout rabuf.sptce
13 Num Of Bodtes 1 1 Num. Of S igna 1 s
ant wafersubstrate pmos#25.00/3.00#penh pmos#30.00/3.00+penh pmos#140.00/1.80+penh pmos#140.00/1.80~penh pmos#l0.00/1.80~penh pmos#20.00/1.80bpenh nmos#58.80/4.00#nenh nrnos#75.00/1.80i?nenh nmos#75.00/1.80i?nenh nmos#l0.00/1.80#nenh nmos#l00.'00/3.00#nenh nmos#l5.00/1.80#nenh nmos#30.00/1.80#nenh unS3 unS4 unS9 unSl un95 unSll unS2 unS6 unS7
ant wafersubstrate
pmos#25.00/3.00#penh pmos*30.00/3.00#penh pmos#140.00/1.80#penh pmos#140.00/1.80#penh pmos#l0.00/1.80#penh pmos#20.00/1.80#penh nmos#58.80/4.00#nenh nmos#75.00/1.80#nenh nmos#75.00/1.80#nenh nmos#l0.00/1.80#nenh nmos#l00.00/3.00#nenh nmos#l5.00/1.80#nenh nmos#30.00/1.80#nenh
un%lSinveSSpSout<0> unSlSinveSSpSout<0> ( r a b u f n o r 2 . 4 p ) t ~ n S l S p . n h VCC unSlSlnveS5pSinp<0> cob VS s an . anb
Tha Circuttm Match.
B-2 The LVS result of R-decoder and S-decoder
SCALDsystem COMPARE Ver 9.2 SUN3-PI (Tue Mar 15 01:08:49 PST 1988).
Processing rsdec.spice
Processing rsdec.lyout
Generating Body Table
rsdec.spice BODYTABLE * * * * * * * * *
Name Number Name Num .........................................................................
Num Of eodfes Num Of Signals
10 Num Of Bodies 1 1 Num Of Signals
Comparing rsdec.spfce rsdec.lyout
a 6 s a5s a4s. VCC wafersubstrate s n
-matching---> a6s -matching---> a5s -matching---> a4s -matching---> V C C -matching---> wafersubstrate -matching---> s n
vss pmos#l0.00/1.80Bpenh pmos#l0.00/1.80#penh pmos#l0.00/1.80#penh nmos#34.90/1.80#nenh nmos#34.90/1.80#nenh nmos#34.90/1.801nenh pmos#30.00/1.80#penh nmos#15.00L1.80+nenh pmos#80.00/1.80#penh nmos#125.00/1.80#nenh
unS5 unS4 un$6 unS7
Tho C f r c u i t s Watch.
8 - 3 The spice simulation and LVS result of a XTDEC
circuit
, - * * x i * * C o p ~ r . i C l t r 1 i r , . n i r l 4 - S o t t i ; a r ~ . I I I C . ' = * * * s 8 t * : r ~ ~ Le +i+++
x t j e C * * * * * * lnatlt I 1 s t lng q i c ~ a t l o n e x p i r e s Y U U H **a***
.opt l o n noqt R S D ~ C
.bJdT h 0\ l t=8( ) v c c Y (i 5 X L I J 1 1U $ x t n 11 S l t n b 1 6 S c l k i 14 S c l k 7 b 17 s a?)\ (1
S a l 2 x l Z S a i x 7 S Q d i s t b 1H S g h v b 1 5 v 1 0 1 0 0 1 2 v 8 8 0 5 v12 1 2 0 5 v 7 7 0 5 v l 8 1 8 0 5 - 1 5 1 5 0 0 v l 4 1 4 0 v u ( 0 7 . 5 l O n s 4011s l o o n s 2 0 n s 17011s) \ 1 7 1 7 O P U ( 7 . 5 0 l O n s l 0 O n s 4Ons 2017s 1 7 0 n s ) v s u b 3 0 0 v s s 1 3 0 0 . t r a n 5 n s 5OOns . temp 25 . p l o t t r a n v t l l ) v i 1 7 ) ~ ( 2 6 1 ~ 1 x 7 ) ~ 1 1 1 1 ~ 1 1 7 ) . p r i n t tran v 1 2 6 l v ( 2 7 1 v 1 2 ) ~ ( 1 1 ) m1 26 20 1 3 3 n e n h w=12 1 = 3 . 5 mZ 1 0 26 20 10 p e n h w = 5 . 8 1 = 3 . 5 md 1 0 20 2 6 l u p e n h w=6 1 = 3 . 5 m4 21 1 6 1 3 3 n e n h w=15 L=2.5 m5 1 1 1 1 21 3 n e n h w=15 1 ~ 2 . 5 16 22 9 11 3 n d e p w = 1 0 4 . 1 0 3 1 = 3 . 0 6 2 m i .i 15 22 3 n d e p w=120 1 - 3 . 5 mH 1 0 26 27 3 n e n h w=6 1=20 8 9 6 Y 20 3 n a t v w=30 1 = 3 mi0 27 27 2 3 n a t v w = 5 4 . 1 9 1 1 = 4 . 7 2 1 a l l 2 2 1 1 3 n a t v w=54 .194 1 = 4 . 7 2 1 m12 1 7 2 1 7 3 n a t v w=23 .2 1 = 4 3 . 3 0 6 0 1 3 14 27 1 4 3 n a t v w=23.2 1 = 4 3 . 3 0 6 m14 5 6 1 3 3 n e n h w=102 .311 1 = 1 . 8 0 5 ml5 1 6 4 1.3 3 n e n h w=100 .5 1 = 1 . 8 m16 9 6 5 9 p e n h w=259 .8 1 = 1 . 8 a 1 7 9 4 1 6 9 p e n h w=130 .2 1 = 1 . 8 a 1 8 6 4 1 3 3 n e n h w=40 1 = 1 . 8 m19 9 4 6 Y p e n h w=30 1 = 1 . 8 m20 2 3 1 8 1 3 3 n e n h w=40 1 = 1 . 8 m21 24 7 1 3 3 n e n h w = 2 5 . 1 l = l . 8 m22 4 1 9 2 3 3 n e n h v = 4 0 1 = 1 .8 m Z Y 2 5 1 2 24 3 npnh 1.=25.1 1 - 1 . x m24 1 9 8 2 5 3 n e n h v = Z 5 . l 1-1 . H
a 2 5 9 1 8 4 Y p e n h w-40 l = l . 8 m26 9 1 9 4 Y p e n h w=40 1-1 . H mZ7 9 7 1 9 9 p e n h w=10 1 = 1 . 8 m2H 9 1 2 1 9 9 p e n h w=10 1 ~ 1 . 8 m29 9 8 1 3 9 p e n h w=10 1 - 1 . 8 . e n d
O P E N I N G P L O T F I L E O N U N I T = 7
****** h s p i c e 8 8 U i a 9 : J t i : 6 3 1 - a u g 8 9 u n 1 x ****** coppriqht 1 9 8 8 meta-software,inc. *****slte:elite ***** xtdec ****** transient analysis tnom= 2 5 . 0 0 0 temp= 2 5 . 0 0 0 ******
time (abcdef )
v ( 0 : 11 0 . 5 . 0 0 0 0 1 0 . 0 0 0 0 1 5 . 0 0 0 0 2 0 . 0 0 0 0
t t t t t
9 . 8 2 2 -e------t------+------2------a-d---c+-------+------+------ t - 9 . 8 2 2 e t t 2 a d c + + t + 9 . 8 2 2 e t t 2 a d c + + t + 9.777 t e + t 2 t at d c+ + + t 9.894 t e t t 2 t a d c + t t t
1 0 . 0 8 7 t t e + 2 t a dc+ + + t
1 0 . 2 9 6 t t e t 2 t t t +a 2t + 1 0 . 5 1 7 t t et 2 t + a cd t + t
1 0 . 7 6 6 t t t2e t t a ctd + t t
1 1 . 0 2 t i t t 2 e t t a ctd t + t 1 1 . 2 8 8 -+------+-----Z+------e------+--- a - c + - d - - - - + - - - - - - + - - - - - - t - 11 , 2 6 0 t t 2 t e + a ctd t t t 1 1 . 1 5 4 t t 2 + e t a ctd t + t
1 1 . 0 3 2 t + Z t e t a cd t + t 1 0 . 9 1 2 + + Z t e t a c d + + t
10.7ti6 t 2 t e t + a dct t t t
1 0 . 6 4 1 t 2 + t e t t a t i c + t t t 10.528 + 2 t t e t +a d C + t + t
1 0 . 4 1 5 t 2 t t e + tad ct t t + 1O.:i04 t Z t t e t + Z c + t t + 1 0 . 1 9 3 - + - 2 - - - - + - - - - - - + p - - - - - + - - - - - - - - - - c + - - - - c + - - - - - - + - - - - - - t - - - - - - + - 1 0 . U 8 4 +'L + e t d a c l t t t
9 7 2 t e + t d a c t t t t
9 . 9 7 1 2 t e t + d a c + t t + 9.368 2 t e t + ti a c t t t t 9.967 2 + e t * d a c + t t t
9.966 2 te t + d a c + t t i
1C1.247 t 2 e t + d +a c + t t t 10.540 + 2et + d a ct t t t
1 0 . 9 3 2 + e + 2 t l d + a c + t t t I \ .SH9 -+---p--+--~---+------t~-----+---a-c+------+------t------+- 1 2 . 3 2 2 t e t 2 + td t c R t + t
1 3 . I Y . i t e + t 2 t -1 t c + a t t t I . ) . f l T Z + e t + 2 + d t C+ R t t t
I I J l l 4 o t + 3 + + ,- +
t e + + 2+ d t r t t a + + P + + Y + +d c + + a + + +e + 2 + + d c+ + a + + 2 + + 2 + + a + + + e+ 2 + + c +d t a + .I
+ + +2e + + + +I c+ d +a + + 2 e + + c + dta + t'
+ + 2 + e + c + +ad + t
+ + 2 + e + c + + 2 + 4
-+------+---2--+------e------+-----c+-----c+------*d-----+------t
****** h s P i c e 8807a 9:46: 6 3 1 - a u q 8 9 u n i x ****** copvrieht 1988 meta-software,inc. *****site:elite *+*** xtdec ****** transient analysis tnom= 25 .000 temp= 2 5 . 0 0 0 ******
voltaqe 'i
0 : 2 6 12.0000 12 .0000 1 2 . 0 0 0 0 12 .0006 12 .0004 1 2 . 0 0 0 5 12 .0005 12 .0005 12 .0004 12 .0005 12 ,0004 11.9996 11 .9997 11.9997 11 .9997 11.9993 11.9994 11 .9994 1 1 . 9 9 8 9 11 .9888 11 .9775 1 1 . 9 7 6 0 11 .9770 11.9825 11 .9832 1 1 .9854 1 1 . 9 8 7 1 11 .9897 1 1 . 9 9 1 1 11 .9925 1 1 . 9 9 3 6 11 .9946 11 .9954 11 .9961 1 1 ,9968 12 .0192 12 .0151 1 2 . ( ~ 6 i l 12 .0617 1 2 . UOhO 12 . 0000 12 .004 1 1 1 . 9 9 4 7 1 2 . O O k i l
I U 4 I I
loltaue 0 : 2 1 0 . 2 0 4 0 10 .2040 1 0 . 2 0 4 0 1 0 . 1 1 8 2 10.3474 1 0 . 6 2 5 9 10 .8967 11 .1686 11.4399 1 1 . 7 1 14 1 1 . '9825 11 .9132 1 1 . 7 5 9 1 11.5825 11 .4009 11 .0994 10 .7691 10.4180 10 .0629
9 .7043 9 . 3 4 8 8 8 . 9 9 9 0 8 .6578 8 .6384 8 .6283 8.6247 8 .6215 9 . 5 2 4 0
10.4267 '
11 .3267 I Z ' . 22UJ 13 .1132 14 . O O O f i 14 .8877 15.7735 15 .7726 15 .7729 15.4296 I5.0Uh.l 14 .7390 14.3914 14 .0444 1 .i . tr913 1.4. 4560 , : I ( i I
vol tape 0 : l l
9 .8218 Y.HZ18 9 . 8 2 1 8 9 . 7 7 7 0 9 . 8 9 3 9
10.U872 1U.2956 10 .5167 1 0 . 7 6 5 5 11 .0258 11 .2884 11 .2599 11 .1545 11 .0920 1 0 . 9 1 2 5 10 .7660 10 .6415 1 0 . 5 2 8 1 10,4154 LO. 3037 1 0 . 1 9 2 9 10 .0837
9 . 5 7 7 1 9 . 9 7 1 0 9 . 9 6 7 9 9. 9667 9 . 9 6 5 7
1U. 2475 10 . 5401 10 .9 . i 21 1 1 .5893 1 2 . . > 2 2 % I J . 1 9 2 5 I-i.1~.521 I 4. YO9 2 1 4 . 9 7 2 2 I 4 . y n n n 1 4 . 7 1 X i 1 4 . J T 8 ~ 14 . . . I 1 1 h
1 4 . 1 i t l ( 1
1 4 . u5nJ l . t . 9434 I . i . M 7 .$ ii 1 , , 4,47,,
***** i o b concl
SCALDsystem COMPARE Ver 9 .2 SUNS-PI (Tue Mar 15 01:08:49 PST 1988) .
P rocess fng x t d . s p i c e
P r o c e s s i n g cmpexp.dat
Gene ra t f ng Body Tab le
x t d . s p i c e BODYTABL E * * * * * * * * *
Name Number Name Number ............................................................................
Num Of Bod ies Num O f S l g n a l s
Comparing x t d . s p l c e cmpexp.dat
2 9 Num O f Bod ies 2 6 Num O f S i g n a l s
c l k 7 c l k 7 b VP f x t n b x t n ghvb gd i s t b a9x a 12x a7x v C C w a f e r s u b s t r a t e
c l k 7 c l k 7 b VP f x t n b x t n ghvb gd t s t b a9x a12x a7x V C C w a f e r s u b s t r a t a
The C i r c u i t s Match .
B-4 The spice s i m u l a t i o n and LVS result of a VPISW
circuit
Thu Aun 31 21:41:19 PDT 1989 ****** copvriqht 1988 meta-software,lnc. *****slte:el~te vp1sws ****** .option nopaqe aspec post dcon=l dv=1000 .width out=80 vcc 16 0 5 vsub 6 0 0 vss 19 0 0 .tran lOns llOOns .plot tran v121 ) v( 17) ~ ( 2 0 ) v(221 vll81 .temp 25 v20 20 19 pu ( 0 5 Ions 2ns 2ns lOns 2511s) v22 22 19 pu ( 5 0 lOns 2ns 2ns lOns 25ns) v17 17 19 pu ( 5 0 lOOOns 2ns 2ns loons 1100ns) v21 21 19 dc 12v ml 15 16 10 6 ndep w=5 1=25 r2 11 16 9 6 ndep u=5 1=25 m3 21 25 25 6 nenh w=300 1=3 a4 22 27 22 6 nenh w=47 1=8.5 a5 24 16 18 6 ndep w=300 1=3 a6 20 2 20 6 nenh w=47 1=8.5 r7 16 26 24 6 ndep w=300 1=.3..5 m8 20 3 20 6 nenh w=47 L-8.5 a9 19 9 19 6 ndep w=40 1=10 m10 21 14 2 6 nenh w=18 1=4 mll 19 10 19 6 ndep w=40 1-10 a12 25 4 4 6 nenh w=100 1 - 1 . 8 m13 12 1 b 4 6 nenh w=5O l = J ml4 21 4 18 6 nenh w=lU00 1=3 mi5 27 27 3 6 natv w=45 1=4 m16 3 3 4 6 natv w=45 1=4 el7 2 2 27 6 natv w=45 1-4 m18 11 17 19 6 nenh w=4 1-4 119 12 7 19 6 nenh w=40 1=1.8 a20 16 17 1 1 16 penh w=5 1=4 121 13 8 19 6 nenh w=5 1 = 5 0122 14 7 19 6 nenh w=8 1=1.8 a23 16 7 12 16 penh w=40 1 = 1 . 8 a24 16 8 13 16 penh w=5 1=5 a25 15 9 19 6 nenh w=5 1=5 a26 16 7 14 16 penh w=8 1=1.8 m27 8 10 19 6 nenh w=5 L-5 m28 16 9 15 16 penh w=5 1=5 a29 16 10 8 16 penh w=5 1 = 5 m30 26 13 19 h nenh w=ZO 1=1.8 a31 26 17 19 b nenh w=20 l=l.H m.42 23 13 26 16 penh w=4U l=1.8 m33 16 17 2 3 lh penh w=40 111.H m.34 5 1.4 19 6 n ~ n h w = l O l=1 . X m . i 5 7 1 7 n h npntl w=l I 1 I = 1 . X mJh 1 6 1.3 7 1 1 . w n h w=.iO l = l . n m.47 I h I i i Ih p r n t ~ w = . 4 0 I = I . X
. ~ n r l
****** transient analvsis ****** l e g e n d :
time ( a b c d e )
0 . 10 .0000n 20 .0000n 30 .0000n 40 .0000n 50 .0000n 60 .0000n 70 .0000n 80 .0000n Y O . 0000n
100 .0000n 110.00001-1 120 .0000n 130 .0000n 140 .0000n 150 .0000n 160 .0000n 170 .0000n 180 .0000n 190 .0000n 200 .0000n 210 .0000n 220 .0000n 230 .0000n 240 .0000n 250 .0000n 260 .0000n 270 .0000n 280 .0000n 290 .0000n 300 .0000n 310 .0000n 320 .0000n 330 .0000n 340 .0000n 350 .0000n 360 . 0000n 3 70.000Un .48U. 0000n J '40.0000n 400 .0000n 410.UU00n 420 .0000n 4 3 0 . UUOUn 44U.OOUOn 1 5 0 . U00Un 4 6 0 . U000n 4 70. OOUOn J X O . CIOOUn 1 4 , ' i l O i I ~ l , ,
v ( 0 : 2 1 ) 0 . 5 .0000 10 .0000 15 .0000 20 .0000
t t t t + 12.000 -c - - - - - -+-e- - - -2 - - - - - -+- - - - - - - - - -a+- - - - -a t - - - - - - t - - - - - - t - - - - - - t - 12 .000 c + e 2 t t at t t t
1 2 . 0 0 0 d + e 2 t t at t t t
12.000 c t e 2 t t at t t + 12.000 d + e 2 t t a t t t t
12.000 c t 3 t t a t t t t
12 .000 c + $ t + a l + t t
12.0UO d t 2e t t at t t t
1 2 . 0 0 0 c + 2e t + at t t t
1 2 . 0 0 0 d t 2 e t t at t t t 12.000 -c------+------2-e----t------
12.000 c + 2 e t t at + t t
12.000 d t 2 e + t at t t t
12 .000 c t 2 e t t at t + t
1 2 . 0 0 0 d + 2 e t t a t t t t
12 .000 c t 2 e t t at t t t
12.000 c t 2 e t + at t t t
12.000 d t 2 t e t at t t t
12 .000 c t 2 e t at t t t
12 .000 d + 2 + e t at t + t 1 2 , 0 0 0 -c------+------2------te-----+-----at------t------+------t- 12 .000 c t 2 t e t at t t t
12.000 d t 2 t e t at t t t
12.000 c t 2 + e t at t t + 12.000 d t 2 t e t a t t t t
12 .000 c t 2 t e t at t t + 12.000 c t 2 t e t a t t t t
12 .000 d t 2 t e t at t t t
12.000 c t 2 t e t at t t + 12.OOU d t 2 t e t a t t t t 12.000 -c- - - - - -+- - - - - -2- - - - - -+- - - - . - -e- t - - - - -at - - - - - - t - - - - - - t - - - - - - t - 12.000 c t 2 + e t a + t t + 12.000 d t 2 t e t at t t t
12 .000 c + 2 t e t at t t + 12.000 d t 2 t e at t t t
12 .000 c + 2 t e t a + t t t
12 .000 c t 2 t e t at t t t
12.0U0 d t 2 t e a + + t t
12.0iJ0 c t 2 t e a t t t t
12.000 d t 2 t t e a+ t t t 12.000 -c- - - - - -+- - - - - -2- - - - - -+- - - - - - - - - -a+-- - - -at - - - - - - t - - - - - - t - - - - - - t -
12.000 c t 2 t e at t t t
12 .000 d t 2 t t e a + t + t 12.Uo0 c t 2 t t e R t t t t
12.UU0 d t 2 t t e at t t t
1 2 . O O U c t 2 t t e at t t + 12 .000 c t Z t te at + + t
12.000 rl t 2 t t e at t t t 1 Z . 000 r t 2 + te 8 t t t t I ' . . " I < 1 + + + C A + +
P a t P a+ e a t
e a t e a+ e a+
ea+ ea+ ea+
***** lob concluded vp1 sws ****** l o b statistics strmmarv ******
S C A L D s y s t e m C O M P A R E Ver 9.2 SUNS-P1 (Tue Mar 15 01:08:49 PST 1988).
Process ing v p isw. sp fce
Process ing v p i sw. 1 you t
Genersting Body Table
vp l c w . lyout
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . hame N u m b e r Name Number - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .
N u m O f Bodiec N u m Of S lgnals
3 7 N u m Of Bod its 2 6 N u m O f Signals
Comparing vplsw.splce vp1sw.lyout
oebt -matching---> oebt VP f -matching---> v p f wafer substrate -matchfng---> wafersubstrate v s s -matching---> v s s nmos+45.50/4.00#natv -matching---> nmos#45.00/4.88+natv nmos#lB05.H0/3.00+nenh -matching---> nmos#l00H.B0/3.H8#nenh nmos#300.0B/3.B8#nenh -i3atchlng---> nmos#300.H8/3.0H~nenh
Tho C l r c u l t s Match.
B-5 The spice simulation and LVS result of a CLOCK
circuit
l ' t111 A I I ~ : ( I 2 2 : : j X : 18 P[)T 1 9 x 9 tar*** c < ~ ~ ~ v l . i g l ~ t 1 9 8 8 m r t i l - s o t t c i i r . ~ , ~ r l r . . * * * * * + I ! , . : , , I ~ t < -
<- I I< **a***
. ovt I on a s p r c ~~ost, d c o n : l r l \ = l O ( l 0 \ . r c 2 2 O 5 v 2 . i 2:1 0 I " v
21, 2 ( i ( 1 Ov
v.3 I .i 1 (1 l>Ll1 s e i u 5 l O u c l l l s 211s 211s I ~ ~ 0 1 1 ~ ~ I I ~ I l l l l ~ I v 3 u :3u 0 5\, $ \ P I 2.4 $ ~ l h v Z t i
$ a l h v p q m b 3 1 s s t h :ro $ c l k 7 2 7 fi c l k 7 t > 2 Y % c l k 5 2 5 $ c l k 5 h 2 8 vsub 5 U O v s s 2 4 U 0 . t r a n 5ns 1 O O O n s u l c . i c v 1 3 t i l = 5 v v l 1 3 ) = U v ( 9 ) = 5 v v l l t i ) = O \ I I $ l = 5 v v l l X . ) = O r - v l 1 l ) = 5 v 1 4 1 = 0 + v l X I = 5 v v ( 7 ) = O v l 2 5 ) = 1 v ( 2 ) = 5 \ . v ( 3 ) = 0 v ( 1 2 ) = 5 v ( l O l = 5 v v l 1 9 I=O v ( 2 0 ) = 5 + v l 2 1 l = O v ( 1 5 l = O v1 1 4 l = 5 v l 3 7 ) = 5 v ( . iH ) = 5 . p l o t 1 r . a 1 1 \ I 2 7 1 \ * I 2 9 1 ~ ( 2 5 1 v l Z X ) v l . i i I \ . I . < H I \ . ( : { I . t t,nll' 2 5 n ~ l .I7 1 9 1 0 ;17 p e n 1 1 w = 5 1=3. .5 in2 Z J 3 8 :it; :I r r a t v w = t i 1 = 4 m J 3 7 2 2 2 2 5 n a t v w = 1 5 1 - 3 . 5 nl l 1 2 2 2 111 5 r l n t \ w = . l O l =:1 1115 1 1 I x 2 I :> r l t ? l l l l w = 5 1 = 5 1111, 2 6 Z 2.4 5 I~e l \ l h w r 4 O 1 - 1 . H m i 1'2 .i 2 1 5 l l rnlt w = l O l = I . H lllX ') 4 2.) .-> ~ I ~ I I I I * = I 0 I = 1 . X m 9 l i 2 4 .i r 1 r t 1 1 1 w = 6 l = l . P 1 n 1 0 2 2 1 8 1 1 2 2 u e r r l r w - l l r I=:, m i l 25 T 2.4 5 r r e r l l ~ v = . S U I = l . 8 11112 2 2 2 :H 2 2 ) ) t>r111 h = j I l I = I .P. r n l .{ 7 X 2 I 5 ~ ~ r r ~ l i w = 1 5 1 = 1 .8 n 1 l 4 2 2 :i I 2 2 2 rent1 u=25 1 z I . H m 1 5 2 2 4 '4 2 2 ~ w r ~ t ) w = 1 0 1 = 1 .8 1 1 1 l l i H 1 2 1 .i 1 1 # . 1 i l 1 W - 2 0 ( = I . X m l i 2 2 li 1 3 2 2 p e t l l ~ w = t i l = l . t ( m l 8 I b 9 2 4 5 n ~ r ~ h w = 3 1 = 5 m l 9 2 2 7 2 5 2 2 pent1 w = 5 0 I = I . H n l2O 4 9 2 - 1 5 nptlh id='lU I = I . X m 2 I 1 i l t j 2 4 5 11e11t l w = 5 1 = 5 m 2 2 2 2 X 7 2 2 prnh w = 1 5 1 - 1 .8 m2:{ 1 H 1 7 2.1 5 1rf.11t1 w=!> 115 1n2sI 2 2 '1 H 2 2 1wr111 w = X O I = 1 .H m 2 3 2 2 Y lti 2 2 p e n h w = 1 0 1 = 5 m Z 0 2 2 9 .I 2 2 r ~ e r r h w = Z O 111 . H m 2 i 2 2 I f i 1 7 2 2 penh w = l U 1 - 5 i n 2 8 2 2 1 7 I H 2 2 r w n h w = l O 11% rnZY 19 I I J 2 I .-b ~ l ~ r l l , v = I l l I = . j . . I
TI,'{II 'Jl l I ' 1 I 4 r a ~ ~ ~ l ~ \. = J 6 I = ' I . :,
m.41 21 2 t l 2 4 5 ~ P I I ~ , w - 2 5 L = . 4 . 5 m32 29 14 24 5 nenh w = Y 6 l = d . > m33 27 15 2 4 5 nenh w - 3 6 lz.4.5 1x134 9 13 24 5 nenh w=5 1 - I . & mJ5 9 11 24 5 nenh w=5 1=5 m36 .I4 13 9 22 pcnh w=20 1=5 m J 7 22 11 34 22 penh w=ZO 1=5 mJ8 3 26 24 5 nenh w=10 L=1.8 m39 3 8 24 5 nenh w=10 1=1.8 m40 35 26 3 22 penh w=20 1=1.8 a41 22 8 35 22 penh v-20 121.8 m42 37 10 19 37 penh w=6 1 ~ 3 . 5 m43 37 19 20 37 penh w=25 1=3.5 844 37 20 21 37 penh w=25 1=3.5 m45 37 14 29 37 penh *=I20 1=3.5 a46 37 15 27 37 penh *=I20 1=3.5 a47 14 15 24 5 nenh w=25 1=3.5 m48 14 21 24 5 nenh us25 1=3.5 m49 15 14 24 5 nenh w=25 1=3.5 a50 15 20 24 5 nenh w=25 1=3.5 a51 36 30 24 5 nenh w=lO 1=1.8 n52 6 31 36 5 nenh r=10 1=1.8 a53 22 30 6 22 penh u=10 1=1.8 a54 22 31 6 22 penh w=10 1=1.8 m55 32 15 14 37 penh w=25 1=3.5 m56 37 21 32 37 penh w=25 1=3.5 m57 33 14 15 37 penh w=25 1=3.5 m58 37 20 33 37 penh w=25 1=3.5 Sm59 38 38 38 5 nenh w=10 1=4 mml 38 38 100 5 nenh u=10 1=4 mm2 100 100 101 nenh w=5 1=4 am3 101 101 22 nenh w=5 1=4 S 1060 23 23 38 5 nenh w=10 1 - 7 m61 23 38 37 5 nenh u=305.6 i=2.5 1062 24 16 24 5 ndep u=23.Z 1=18..{2 m63 24 1 7 24 5 ndev ut23.2 I=lfJ.J2 m64 24 18 24 5 ndep w=23.2 1=18.32 a65 24 9 24 5 ndep w=23.2 1=18.32 m66 24 11 24 5 ndep -23.2 l=lH.JZ .macro load 1 7 vp i a1 1 2 1 24 natv ~ ~ 2 3 . 2 1=6.925 m2 2 2 3 24 natv w=5.8 1=3.5 m3 vpi vpi 2 24 nenh w=5.9 1=15 a4 3 3 24 24 natv w=5.8 1=3.5 m5 7 3 7 24 natv w-5.8 1-3.5 . end8 xl 27 29 vpi load m=8 cl 27 24 lpf rl 27 100 lk x Z 100 29 vpi load a=64 1-2 100 101 lk c 2 101 24 lpf x3 101 29 vpi load m=8 . end ****** copyriqht 1988 mets-softuare.inc. *****site:elite clk ****** trans ient anal v s i s tnom= 25.000 temp= 25 ****** leqend:
n : v f o : 2 7 )
v l 0 : 2 7 1 - 5.OUt)U 0 . 5 . OUUO 1 0 . 0 0 0 0 1 5 . 0 0 0 1 t
t + + + 0 . - + - - - - - - + - - - - - - 4 - - c - - - + - - - - - - 2 - - - - - - + - - - t - - - - - - t - - - - - - + - - - - - - * 4 . 1 2 2 + t 2 b + a 2 f + + + 1 . 4 1 1 + t 2 + a c Z + f t + 4 .771 + t 2 + aceb f + + ti
*I :I 5.617 t + Zb + d a e + f + + t.
i . 2 b l + t 2 + d 2e t'+ t t
5 4 9 . 4 2 5 ~ 1 + + 2 a + d i ! f + + + t
170.43581 + + 3 + 3 f + + + t
133.514m + + 3 t 3 f + + + t
lZ8.895m + + 3 + 3 f + + + t 128.419=-+------+------3------+----- d z - f - - - - + - - - - - - + - - - - - - + - - - - - - + 1 1 8 . 7 7 6 ~ 1 + t 3 + 2 c f + + + t
4 .641 + + 2 + a2e f + + t
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7.857 t + 3 + c + 2 f + t
8 . 1 9 5 + + 3 + c + 2 f + + 8 . 3 5 9 + + 3 + c + ae f + + 8 . 4 3 7 + + 3 + c + 2 f + t
8 . 4 8 1 + t 3 + c + 2 f + + 7 .737 - + - - - - - - + - - - - - - 3 - - - - - - + - - - - - - d - - - - - - w - - - f + - - - - - - + - - - - - - t 7 .277 + + 2 + d a + 2 f + t
364.970m + + 2 A + d2 f + + + + 1 5 7 . 9 4 9 ~ 1 + + 3 + 3 f + + + +l
1 2 9 . 4 7 6 s + + 3 + 3 f + + + 1 2 6 . 5 9 4 ~ 1 + + 3 + 3 f + + + 126.766. + + 3 + 3 f + + + 127.035m + + 3 + 3 f + + + 102.231m + + 3 + 2 c f + +
j +c
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5 , 4 4 5 -+------+------2b-----+------ cae----+f-----+------+------+ 6 . 9 5 8 + + 3 + c se+ f + + t
7 .762 + + 3 + c +2 f + + + 8 . 1 5 2 + + 3 + c + 2 f + + 8 . 3 3 6 + + 3 + c + 2 f + + 8 . 4 2 8 + + 3 + c + 2 f + 8 . 4 7 6 + + 3 + c + 2 f + 8 . 0 1 8 + + 3 + d +2 f + + + I
:I 7 .903 + + 2 t d +3 f + +I
5 9 4 . 3 9 3 ~ + + Z a + d 2 f + + + +I 172 ,063~-+- - - - - -+- - - - - -3 - - - - - - - -+- - - - - -3 - f - - - -+- - - - - -+- - - - - -+- - - - - -+ , 137.208m + + 3 + 3 f + + + t
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3 . 0 7 5 + + 2 + a e b c f + + + + 5 .272 + + 2 b + c a e + f + + + 6 . 7 7 8 + + 3 + c a e + f + + + 7 . 6 7 0 + + 3 + c a e f + + + 8 .112 -+------+------3------+------c------- -+-2----f--- - - -+------+ 8 . 3 1 6 + + 3 + c + 2 f + + 8 . 4 1 6 + + 3 + c + 2 1 + + 8 . 4 7 1 + + 3 + c + 2 f + + 8 . 1 9 8 + t 3 + d + 2 f + + 7 . 7 2 0 + + 2 + d b e a f + + + I . 3 0 9 + + 2 a + d 2 + f + + +
106.557m + + 2 a + 3 f + + + + l d l Y' /c;m + A 1 -, .-
. . . . . 128.jq~m t + J t J t ' • t t t
L27.&ljm-t------+------3------t------jjf----t------t------t------ t-
128.102m t t 3 t 3 f + t + t
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1.754 t t 2 a t 2 c f + t t t
5.309 t t 2 t b c a e +f t t t
6.502 t t 3 t c n e t f + t t
7.521 t t J + c 2 f t t t
8.046 t t 3 t c t 2 ft + + 8.287 t t .i + c t 2 t' +. t 8.404 t t 3 t c + ' L f t ' t 8.462 -+------+------J------+------c------+--2---f------t------t- 8.273 + t 3 t d t 2 f t + 7.377 + t 2 t db e a f + t t
2.811 t t 2 + a d b e t f t t t
207.382~ t t 'La t 3 f t t + t
142.311m t t 3 t 3 f t t t t
129.969. l t 3 t 3 f t t t t
128.785~ t t 3 t 3 f t t t t
128.862~ t t J t 3 f + t t t
119.217. t t 3 t 2c f + t t t 791.538D-+------t------22R----t---222CCf----+------+------+------+-
5.279 t t 2 t bcae tf + t t
6.327 + t 3 t c a e t f + t t
7.448 t t 3 + c 2 f t + t
8.004 + t 3 - + c tae f + t t 8.265 t t 3 + c t 2 f t t
8.394 t t 3 t c t 2 f t t
8.455 t t 3 + c t 2 f t t
8.415 + t 3 t d t ea f t t 7.401 t t 2 b t d ea f + + t 4.834 -+------t------2------+---------bs+----bet----f-t------t------t-
247.059. t t 2a t 3 f t t t + 151.018~ t t 3 t J f + t t t
13U. 072m t t 3 t 3 f + t t t
128.853~ t t 3 t 3 f + t t t
129.517r t t 3 t 3 f l t t t
128.333r t + 3 t 3 f t t t t
241.120m + t 2 a t 2 c f + t t t
5.057 t t 2 t 3 e f + t t
6.065 t t 3 t c a e t f + t t 7.330 - + - - - - - - + - - - - - - 3 - - - - - - + - - - - - - - - c - - - - - - ~ - - - - f - + - - - - - - + - - - - - - + - 7.943 t t 3 t C t2 ft t t
8.236 t t 3 + c t 2 f t t
8.379 t t 3 t c t ae f t t
8.447 t t 3 t c t 2 f + t
8.486 + t 2 d t c t 2 f t t
7.590 t t 3 t d 2 ft t t
6.346 t t 2 t d a 2 ft t t
298.321. t + 2 a + d2 F t t t t
155.706m t + 3 t 3 f t t + t )30.790m-+------+------3------+------3-f----+------+------+------+- 129.351~ l t 3 t 3 f l t t t
129.786. t t 3 t 3 f t t t t
129.948m t t 3 t d2 f + t t + llY.6RBm t t 3 t 2 c f l t t t
4 . r i 1 3 t t 2 t a2e f t t t
5.708 + + 2 b t c a e t f + t t
7.141 + t 3 t c a r f t t + 7.854 .t t 3 + r t 2 Yt t t
U.lk4 t t 3 t r t 2 t 4 + 8.35f, - + - - - - - - t - - - - - - ~ - - - - - - + - - - - - - , . - - - - - - + - a e - - f - - - - - - + - - - - - - + -
SCALDsystem COMPARE Ver 9.2 SUN3-P1 (Tue Mar 15 01:88:49 PST 1988).
Processing clk-s.1yout
Processing clk-s.spice
Generatfng Body Table
clk-s.lyout BODYTABL E
Name Number Name Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Num O f Bodies Num O f Signals
Comparing clk-s.lyout clk-s.spice
5 4 Num O f Bod i e s 3 1 Num O f Signals
clk7 clk7b VP V C C
~ g m b wafersubstrate vss lgdistb pmos#25.00/3.50#p4 prnos#25.00/3.50#p4 pnos#25.00/3.50#p4 pmos#25.00/3.50#p4 pmos#120.00/3.50#p4 pmos#120.00/3.50tp4 pmos#6.00/3.50#p4 pmos#5.00/3.50Xp4 pmosX25.00/1.80#penh pmos#20.00/1.80#penh pmos#20.80/5.00#penh pmos#20.00/5.00#penh
clk7 c 1 k7b VP f v C C
pgmb wafer substrate VSS lgdfstb
pmos#Z5.00/3.SB#p4 pmos#25.00/3.50#p4 pmost25.00/3.58#p4 pmos#25.00/3.50#p4 pmos#120.00/3.50+p4 pmos#120.00/3.50#p4 pmos#6.00/3.50#p4 pmos#5.00/3.50+p4 pmos#25.00/1.80#penh pmos#20.00/1.80#penh pmos#20.00/5.00#penh pmos#20.00/5.00#penh
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