Chapter 12Chapter 12

Registers and CountersRegisters and Counters

Ilsub ChungIlsub Chung

(2007. 11. 26)(2007. 11. 26)

OutlineOutline

Analysis and Design of Combinational LogicAnalysis and Design of Combinational Logic

Last Time

Flip-flops

Flip-flop Timing Specifications

Simple Counters

GeneralGeneralSimple CountersSimple Counters

Digital counter consists of a collection of flip-flops Digital counter consists of a collection of flip-flops • Change states in prescribed sequence Change states in prescribed sequence

Flip-flops are commonly used to design countersFlip-flops are commonly used to design counters• Most straightforward counter is ripple dividerMost straightforward counter is ripple divider

o Use T FF or Toggle FF Use T FF or Toggle FF

J-K flip-flop can be converted to a T or toggle flip-flop J-K flip-flop can be converted to a T or toggle flip-flop • By connecting together J and K inputs By connecting together J and K inputs

Divide by 2 CounterDivide by 2 CounterSimple CountersSimple Counters

Clock input can be used as a data input Clock input can be used as a data input • Divide by 2 circuit divides input CK by 2 Divide by 2 circuit divides input CK by 2

J, K inputs are connected together and pulled up to VccJ, K inputs are connected together and pulled up to Vcc• Force excitation inputs “high”Force excitation inputs “high”

o Causing FF to toggle on every CKCausing FF to toggle on every CK

If negative edge pulse is used If negative edge pulse is used

Divide by 4 CountersDivide by 4 Counters

Simple CountersSimple Counters

Divide by 4 Counter requires 2 FFsDivide by 4 Counter requires 2 FFs• Divide by 4 counter divides the input CK frequency by “4”Divide by 4 counter divides the input CK frequency by “4”

Both J-K FFs are connected Both J-K FFs are connected • To form toggle FF with Q output of 1To form toggle FF with Q output of 1stst FF FF

o Providing the input to the secondProviding the input to the second

22ndnd FF divides the Q output from 1 FF divides the Q output from 1stst FF by 2 FF by 2 • Thereby dividing the input frequency “4” Thereby dividing the input frequency “4”

Divide 8 CountersDivide 8 Counters

Simple CountersSimple Counters

Requires 3 FFsRequires 3 FFs• Each FF is connected as a toggle flip-flopEach FF is connected as a toggle flip-flop

All J-K FFs are connected to toggle with Q output of 1All J-K FFs are connected to toggle with Q output of 1stst FF FF o Providing the input to 2Providing the input to 2ndnd FF, Q output to 3 FF, Q output to 3rdrd input input

Asynchronous counterAsynchronous counter Modulo-n countersModulo-n counters

• N states : terminal countN states : terminal count• Modulo-8 counter has 8 statesModulo-8 counter has 8 states

Johnson CounterJohnson Counter

Simple CountersSimple Counters

Connecting output of one FF to input of another FF Connecting output of one FF to input of another FF FF FF

• Offset by a CK pulse from preceding FF output Offset by a CK pulse from preceding FF output Produce a series of outputs from each FF Produce a series of outputs from each FF

• Offset by Offset by one CK pulseone CK pulse from preceding FF output from preceding FF output Synchronous operation Synchronous operation

• CK pulse cause FF action at the same CK time CK pulse cause FF action at the same CK time

Q’Q’DD is fed back to D is fed back to DAA

Johnson CounterJohnson Counter

Simple CountersSimple Counters

Initially reset all FF Initially reset all FF • Negative edge of 1Negative edge of 1stst set FF A : Q set FF A : QAA is “1” is “1”• The states of other FFs do not changeThe states of other FFs do not change

o No input changeNo input change 22ndnd CK pulse set FF B, 3 CK pulse set FF B, 3rdrd set FF C, etc. set FF C, etc. 44thth CH set FF D : Q CH set FF D : QDD is “1” is “1”

• Q’Q’DD is “0” is “0” o Changing QChanging QAA

Johnson Counter can be used to produce time delay Johnson Counter can be used to produce time delay

Ring CounterRing Counter

Simple CountersSimple Counters

Ring counter produces a continuous pattern from FF outputsRing counter produces a continuous pattern from FF outputs• Ability to load particular stateAbility to load particular state• Synchronous operationSynchronous operation

Initialized using “PRE and RESETInitialized using “PRE and RESET• 0010110100101101

• Active low input : FF3, FF5, FF6, FF8Active low input : FF3, FF5, FF6, FF8• Others are reset Others are reset

Data are shifted from one FF to next on Data are shifted from one FF to next on • Negative edge of CK pulseNegative edge of CK pulse

Assume Assume 10001100 is preloaded10001100 is preloaded• 11stst negative CK pulse : Q negative CK pulse : Q11 goes to “0” goes to “0”• QQ22 change its state also : “0”->”1” change its state also : “0”->”1”

Generate a repeating n-bit patternGenerate a repeating n-bit pattern LSB output is connected to MSB inputLSB output is connected to MSB input

Ring CounterRing Counter

Simple CountersSimple Counters

MSI Integrated CircuitsMSI Integrated Circuits Various counter is possibleVarious counter is possible

• Simple ripple binary counters Simple ripple binary counters • Synchronous up-down decade counters Synchronous up-down decade counters

Flip-Flops, Simple Counters, and ResistersFlip-Flops, Simple Counters, and Resisters

MSI Asynchronous CountersMSI Asynchronous Counters

MSI Integrated Circuit CountersMSI Integrated Circuit Counters

SN74176 is a TTL MSI decade or BCD counter SN74176 is a TTL MSI decade or BCD counter • 2 Clock inputs2 Clock inputs• AsynchronousAsynchronous

11stst CK input is present only for 1 CK input is present only for 1stst FF FF• FF can be used as a high speed prescalerFF can be used as a high speed prescaler

o Divide by 2 Divide by 2 Q output of FF A is not connected to others Q output of FF A is not connected to others

• Allow user to connect it to 2Allow user to connect it to 2ndnd CK input CK input• Or use the single FF separately from remaining 3 FFsOr use the single FF separately from remaining 3 FFs

FF B and D are triggered by the CK 2 inputsFF B and D are triggered by the CK 2 inputs FF C is triggered by QFF C is triggered by QBB

• AsynchronousAsynchronous

MSI Asynchronous CountersMSI Asynchronous Counters

MSI Integrated Circuit CountersMSI Integrated Circuit Counters

Configurable CounterConfigurable Counter

MSI Integrated Circuit CountersMSI Integrated Circuit Counters

Binary CounterBinary Counter

MSI Integrated Circuit CountersMSI Integrated Circuit Counters

MSI Synchronous CounterMSI Synchronous Counter Synchronous counters have all CK inputs to FF connected together Synchronous counters have all CK inputs to FF connected together

• State changes occur simultaneouslyState changes occur simultaneously• Synchronous operationSynchronous operation

Initialized using “PRE and RESETInitialized using “PRE and RESET• 0010110100101101

• Active low input : FF3, FF5, FF6, FF8Active low input : FF3, FF5, FF6, FF8• Others are reset Others are reset

Data are shifted from one FF to next on Data are shifted from one FF to next on • Negative edge of CK pulseNegative edge of CK pulse

MSI Integrated Circuit CountersMSI Integrated Circuit Counters

MSI Synchronous CounterMSI Synchronous Counter To provide even longer count sequences : CascadeTo provide even longer count sequences : Cascade

• ENP, ENT, and RCO linesENP, ENT, and RCO lines RCO is an output signal asserted when terminal count is reached RCO is an output signal asserted when terminal count is reached

• It is used to link a lower order decade counter to next higher It is used to link a lower order decade counter to next higher orderorder

ENT and ENP are input enable signals : ENT and ENP are input enable signals : Control counting counterControl counting counter Connecting RCO-ENT : cascadingConnecting RCO-ENT : cascading Common CK is presented to all of ICs in parallelCommon CK is presented to all of ICs in parallel Ripple carry from one decade to another is provided by RCO-ENTRipple carry from one decade to another is provided by RCO-ENT ENT signal is used to control the entire counterENT signal is used to control the entire counter

MSI Integrated Circuit CountersMSI Integrated Circuit Counters

MSI Synchronous CounterMSI Synchronous Counter

Sequential Circuit ModelsSequential Circuit Models

MSI Integrated Circuit CountersMSI Integrated Circuit Counters

Chapter 5Chapter 5

Flip-Flops, Simple Flip-Flops, Simple Counters, and RegistersCounters, and Registers

Ilsub ChungIlsub Chung

(2002. 11. 19)(2002. 11. 19)

OutlineOutline

Last Time

Simple Counters

Register

GeneralGeneralSimple CountersSimple Counters

Digital counter consists of a collection of flip-flops Digital counter consists of a collection of flip-flops • Change states in prescribed sequence Change states in prescribed sequence

Flip-flops are commonly used to design countersFlip-flops are commonly used to design counters• Most straightforward counter is ripple dividerMost straightforward counter is ripple divider

o Use T FF or Toggle FF Use T FF or Toggle FF

J-K flip-flop can be converted to a T or toggle flip-flop J-K flip-flop can be converted to a T or toggle flip-flop • By connecting together J and K inputs By connecting together J and K inputs

Divide by 2 CounterDivide by 2 CounterSimple CountersSimple Counters

Clock input can be used as a data input Clock input can be used as a data input • Divide by 2 circuit divides input CK by 2 Divide by 2 circuit divides input CK by 2

J, K inputs are connected together and pulled up to VccJ, K inputs are connected together and pulled up to Vcc• Force excitation inputs “high”Force excitation inputs “high”

o Causing FF to toggle on every CKCausing FF to toggle on every CK

If If negative edge pulsenegative edge pulse is used is used

Divide by 4 CountersDivide by 4 Counters

Simple CountersSimple Counters

Divide by 4 Counter requires 2 FFsDivide by 4 Counter requires 2 FFs• Divide by 4 counter divides the input CK frequency by “4”Divide by 4 counter divides the input CK frequency by “4”

Both J-K FFs are connected Both J-K FFs are connected • To form toggle FF with Q output of 1To form toggle FF with Q output of 1stst FF FF

o Providing the input to the secondProviding the input to the second

22ndnd FF divides the Q output from 1 FF divides the Q output from 1stst FF by 2 FF by 2 • Thereby dividing the input frequency “4” Thereby dividing the input frequency “4”

Divide 8 CountersDivide 8 Counters

Simple CountersSimple Counters

Requires 3 FFsRequires 3 FFs• Each FF is connected as a toggle flip-flopEach FF is connected as a toggle flip-flop

All J-K FFs are connected to toggle with Q output of 1All J-K FFs are connected to toggle with Q output of 1stst FF FF o Providing the input to 2Providing the input to 2ndnd FF, Q output to 3 FF, Q output to 3rdrd input input

Asynchronous counterAsynchronous counter Modulo-n countersModulo-n counters

• N states : terminal countN states : terminal count• Modulo-8 counter has 8 statesModulo-8 counter has 8 states

Johnson CounterJohnson Counter

Simple CountersSimple Counters

Connecting output of one FF to input of another FF Connecting output of one FF to input of another FF • Offset by a CK pulse from preceding FF output Offset by a CK pulse from preceding FF output

Produce a series of outputs from each FF Produce a series of outputs from each FF • Offset by Offset by one CK pulseone CK pulse from preceding FF output from preceding FF output

Synchronous operation Synchronous operation • CK pulse cause FF action at the same CK time CK pulse cause FF action at the same CK time

Q’Q’DD is fed back to D is fed back to DAA

Johnson CounterJohnson Counter

Simple CountersSimple Counters

Initially reset all FF Initially reset all FF • Negative edge of 1Negative edge of 1stst set FF A : Q set FF A : QAA is “1” is “1”• The states of other FFs do not changeThe states of other FFs do not change

o No input changeNo input change 22ndnd CK pulse set FF B, 3 CK pulse set FF B, 3rdrd set FF C, etc. set FF C, etc. 44thth CH set FF D : Q CH set FF D : QDD is “1” is “1”

• Q’Q’DD is “0” is “0” o Changing QChanging QAA

Johnson Counter can be used to produce time delay Johnson Counter can be used to produce time delay

Ring CounterRing Counter

Simple CountersSimple Counters

Ring counter produces a continuous pattern from FF outputsRing counter produces a continuous pattern from FF outputs• Ability to load particular stateAbility to load particular state• Synchronous operationSynchronous operation

Initialized using “PRE and RESETInitialized using “PRE and RESET• 0010110100101101

• Active low input : FF3, FF5, FF6, FF8Active low input : FF3, FF5, FF6, FF8• Others are reset Others are reset

Data are shifted from one FF to next on Data are shifted from one FF to next on • Negative edge of CK pulseNegative edge of CK pulse

Ring CounterRing Counter

Simple CountersSimple Counters

Assume Assume 10001100 is preloaded10001100 is preloaded• 11stst negative CK pulse : Q negative CK pulse : Q11 goes to goes to

“0”“0”• QQ22 change its state also : “0”- change its state also : “0”-

>”1”>”1” Generate a repeating n-bit patternGenerate a repeating n-bit pattern LSB output is connected to MSB LSB output is connected to MSB

inputinput

MSI Integrated CircuitsMSI Integrated Circuits Various counter is possibleVarious counter is possible

• Simple ripple binary counters Simple ripple binary counters • Synchronous up-down decade counters Synchronous up-down decade counters

Flip-Flops, Simple Counters, and ResistersFlip-Flops, Simple Counters, and Resisters

MSI Asynchronous CountersMSI Asynchronous Counters

MSI Integrated Circuit CountersMSI Integrated Circuit Counters

SN741176 is a TTL MSI decade or BCD counter SN741176 is a TTL MSI decade or BCD counter • 2 Clock inputs2 Clock inputs• AsynchronousAsynchronous

11stst CK input is present only for 1 CK input is present only for 1stst FF FF• FF can be used as a high speed prescalerFF can be used as a high speed prescaler

o Divide by 2 Divide by 2 Q output of FF A is not connected to others Q output of FF A is not connected to others

• Allow user to connect it to 2Allow user to connect it to 2ndnd CK input CK input• Or use the single FF separately from remaining 3 FFsOr use the single FF separately from remaining 3 FFs

FF B and D are triggered by the CK 2 inputsFF B and D are triggered by the CK 2 inputs FF C is triggered by QFF C is triggered by QBB

• AsynchronousAsynchronous

MSI Asynchronous CountersMSI Asynchronous Counters