chapter7 circuits

Elec3017:Electrical Engineering Design

Chapter 7: Circuits and Communication

A/Prof D. S. Taubman

September 1, 2008

1 Purpose of this ChapterThis chapter cannot possibly take the place of an electronics course, so it isassumed that you already have the basics under your belt. You may alreadyhave seen a number of the circuit ideas introduced in this chapter, but then youmight not have. Our goal is to be as practical as possible, pointing out someof the configurations and concepts with which every electrical engineer shouldhave some familiarity.Seeming as all the lecture notes for this course are being created for the first

time, it is not possible to provide a comprehensive written coverage here at thepresent time. For this reason, many sections of these notes serve only to indicatethe circuit configurations which are discussed during lectures and provide youwith some brief pointers. If, for some reason, you are unable to attend lectures(this is generally a mistake), you can use these pointers to conduct your ownresearch. A good general reference is [1].Many electronics design projects end up involving some form of communica-

tion, in the presence of noise and interference. These projects tend to be donebadly, due to a lack of knowledge of the fundamental principles. In Section 5,we attempt to bridge this knowledge gap, by providing a minimal treatmentof the concepts of matched filtering and receiver synchronization, with circuitexamples.

2 Voltage SourcesTopics covered are as follows:

• Regulated power supplies• Establishing a voltage reference with zener diodes — remember to use aceramic capacitor to reduce high frequency noise.

1

c°Taubman, 2006 ELEC3017: Circuits and Communication

• Establishing a voltage reference using a forward biased diode — remembertemperature sensitivity (Ebers-Moll equation).

• A few words about temperature stabilized voltage reference IC’s.

3 Driving CircuitsTopics covered are as follows:

• Driving solenoids and relays — remember fly-back diodes and snubber cir-cuits.

• Driving LED’s and LED displays• Driving digital transmission lines — remember R-C transient suppressioncircuits.

4 Opamp CircuitsTopics covered are as follows:

• Inverting, non-inverting, summing and differential amplifiers• Peak detectors and recifier circuits• Digitally controlled integrators — circuits and choosing suitable compo-nents

5 CommunicationsSince the material in this section is more difficult than the others, we providesome additional explanation of the theory here. We cannot afford to be con-cerned with general communication theory, so we will focus primarily on theproblem of robustly detecting codes (i.e., signal patterns) and modulated bi-nary data sequences in the presence of noise and interference. The methodsdescribed here can be used with RF, IR or even audio physical communicationsmedia.

Sidebar: The word “media” is plural. Its singular form is “medium.” Thus, anIR link forms a single communications medium, whereas IR and RF aretwo different communications media.

Totally unrelated sidebar: While we are on singular and plural forms oftechnical English terms, here is one common error that grates most deeplyupon the ear: The word “criterion” is the singular of “criteria.” Please getthis around the right way!!!


5.1 Mathematical Description of the Transmitted Signal

At a fundamental level, we are concerned with transmitted signals of the fol-lowing form:

x (t) =Xk

sk · g (t− kT ) (1)

Here, T is the symbol period, sk is the kth symbol value, and g (t) is knownas the shaping pulse. Equation (1) states the transmitted signal is formed byconcatenating scaled copies of the shaping pulse. During the first symbol period(first T seconds), x (t) is equal to g (t) scaled by s0. During the second symbolperiod, x (t) is equal to g (t− T ) scaled by s1 — i.e., delay g (t) by T seconds, toshift it into the second symbol period, and then multiply by s1 — and so on.For simplicity, we restrict our attention here to the following scenarios:

Repeating code: In this case, sk = 1 for all k so that x (t) is a periodicwaveform, with period T , the first period of which is given by g (t). Wethink of g (t) as some kind of code, which is used to indicate the presenceof a transmitter. The goal of the receiver, in this case, is to figure outwhether or not the code is being transmitted and hence to deduce whetherthe transmitter is nearby. A typical application of this is the garage dooropener. Each garage door looks for a specific code g (t), whose presenceindicates that the door should be opened (or closed, if it is already open).The code g (t) should have a high degree of uniqueness and other garagedoor codes, or randomly generated codes, should have an extremely lowprobability of being detected by the receiver. Other codes may be regardedas sources of interference. The reason for repeating the code g (t) is to givethe receiver time to lock onto the pattern. It may require many repetitionsbefore the receiver can correctly detect the code in a robust manner — moreon this shortly.

On-off keying: In this case, sk ∈ 0, 1, so that in each symbol interval, thecanonical shaping pulse g (t) is either present or absent. Presence or ab-sence may be interpreted by the receiver as a binary digit, so that eachsymbol period has the opportunity to signal a single bit.

Antipodal signalling: In this case, sk ∈ −1, 1, so that in each symbol inter-val, either g (t) or −g (t) is transmitted. Again, this allows for the trans-mission of a single binary digit in each symbol period. One importantadvantage of antipodal signalling over on-off keying is that the receiverneed only decide whether the received signal looks more like g (t) or itsinverse within each symbol period — this decision is essentially indepen-dent of the amount by which the signal may have been attenuated overthe transmission medium. For on-off keying, on the other hand, attenua-tion in the transmission medium biases the detection process toward thedetection of a 0 (off). On the other hand, antipodal signalling presentsgreater challenges for synchronization — particularly for the recovery ofthe transmitter’s symbol clock at the receiver.


5.2 Matched Filters for Optimal Reception

For the sake of this simple treatment, we will regard the signal recovered bythe receiver as a scaled copy of the transmitted waveform plus additive whiteGaussian noise. We write this as

y (t) = αx (t) + n (t) (2)

=Xk

αg (t− kT ) · sk + n (t)

An important property of truly white noise processes is that they have infinitepower. To see this, let ΓN (f) be the power spectral density of the noise process,as a function of frequency f . For a truly white noise process, ΓN (f) = N0/2is constant1, for all frequencies. Now the noise power in the time domain isexpressed by the variance of n (t). That is,

σ2N = E£n2 (t)

¤=

Z ∞−∞ΓN (f) df =∞!!

What this means is that instantaneously sampling a truly white noise waveformn (t) at any given time instant t will produce sample values of infinite magnitudewith probability 1.This might sound ridiculous at first. Of course, the noise cannot have infinite

power. However, its power spectrum is often well approximated as flat over allfrequencies of interest, i.e.

ΓN (f) =N0

2

The trick, then, is to filter the signal before sampling it, in order to avoid theamplitude of the sampled noise process far exceeding that of the signal of inter-est. Filtering the noise process limits the range of frequencies over which ΓN (f)departs significantly from 0, which drastically reduces the value of σ2N producedby the above integral. This is a very real phenomenon. For communicationsystems, we don’t just take samples of the received waveform and then process.We should always include some kind of analog filter.Fortunately, the best kind of analog filter depends on the shaping pulse g (t)

alone, and can often be implemented or approximated quite simply with the aidof a switched opamp integrator. This best filter is called a matched filter, butit is most easily understood and implemented if you don’t think of filtering atall. Instead, let h (t) be any scaled version of g (t); that is,

h (t) = βg (t) (3)

Suppose that the receiver is perfectly synchronized with the transmitter. Thenthe variable which best indicates what was transmitted in symbol period k —

1We adopt here the usual convention of writing N0/2 for the magnitude of the two-sidedpower spectrum (having values for both positive and negative frequencies). This means thatthe power passed by a band-pass filter with passband given by B0 ≤ |f | ≤ B1 is equal toN0 · (B1 −B0).


i.e., between time kT and (k + 1)T — is

rk =

Z T

0

y (t+ kT ) · h (t) dt (4)

Putting equation (2) into the above equation, we see that

rk = sk · αβZ T

0

g2 (t) dt+ β

Z T

0

g (t)n (t) dt

= sk · αβEg + n0k

Here, Eg denotes the total energy in the shaping pulse2

Eg =

Z T

0

g2 (t) dt

. It can be shown that the noise term, n0k is a zero mean Gaussian randomvariable with variance

σ2N 0 =N0

2β2Eg

Now, since the the standard deviation of n0k (i.e., σN 0) varies as βpEg and the

magnitude of the transmitted signal component, sk ·αβEg, varies as αβEg, it isclear that the key to robust reception is to make αEg much larger than

pEg.

There are three ways to do this:

1. Make α as large as possible — this corresponds to making the receiver moreefficient, or bringing it closer to the transmitter, so that it receives a largerportion of the transmitted signal power.

2. Make the amplitude of g (t) as large as possible — this corresponds toincreasing the transmitter power.

3. Make the duration of g (t) as large as possible — this corresponds to slowingdown the communication, integrating for a longer period at the receiverbefore deciding what was transmitted.

Given that receiver efficiency and transmitter power are likely to be constrainedby technology and/or regulatory standards, the third mechanism is the onlything that a designer has direct control over. In summary, the longer you inte-grate at the receiver, the more robust your detection mechanism will be.The above discussion may still seem rather abstract. To bring things sharply

into focus, let us consider how to implement the receiver model in equation(4). Suppose, for simplicity, that g (t) is a square wave pattern, consisting ofalternating −1’s and 1’s, as shown in Figure 1. In this case, the matched receiver

2We think of the energy in a signal as the integral of its squared amplitude. The originof this convention is that we think of the signal as a voltage waveform, applied across a 1Ωresistor. Of course, we can replace the load resistor with R, and then the energy is just scaledby 1/R, but this is of no fundamental importance.


)(tg

t

0 T1−

1+)(tg

t

0 T1−

1+

Figure 1: Example shaping pulse.

R2rk

y(t)

CR1R1

S2

S1

S3

R2rk

y(t)

CR1R1

S2

S1

S3

Figure 2: Matched filtering receiver for square wave shaping pulses. The circuitis an integrator, driven either by y (t) or −y (t), depending on the state of theMOSFET switches (e.g. those provided by a CD4066 quad bilateral switch IC)S1 and S2. Switch S3 is used to dump charge at the start of each symbol period.The output rk holds the correct value at the end of each symbol period.

can be implemented using the circuit shown in Figure 2. Here, switch S1 isclosed when g (t− kT ) is +ve, while switch S2 is closed when g (t− kT ) is −ve.The factor β in equation (3) depends on the selection of parameters (resistorsand capacitor) in the opamp integrator. The switch S3 is closed very briefly atthe start of each symbol period. It is important that the on resistance of thisswitch is as small as possible, so that very little of the symbol integration periodneed be wasted in dumping the capacitor’s charge in preparation for the nextperiod. To simplify things, you might design your shaping pulse g (t) to containan initial period in which g (t) = 0, during which capacitor charge dumping canoccur. The longer this initial period is, the easier it will be for a receiver tofully dump the charge on the integrator’s capacitor, but this charge dumpingperiod will also reduce the value of Eg, which determines the communicationrobustness. We can now consider the circuit shown in Figure 2 in light of thethree communication scenarios outlined at the beginning of this section.

Repeating code: In this case, our objective is simply to determine whether


or not the transmitter is present. The output rk from the integrator atthe end of one symbol period, is given by

rk =

½αβEg + n0k if transmitter present

n0k if no transmitter

Evidently, both the presence and absence of a transmitter may producenon-zero values for rk, so we must determine a threshold κ and checkwhether or not rk > κ. The threshold should be some multiple of theRMS noise amplitude, e.g., κ = 4σN 0 or more. In order to make detectionmore reliable, we should consider integrating for multiple symbol periods.For example, we can always think of x (t) as being generated by symbolswith period 2T , each of which is of the form g (t) + g (t− T ) — i.e., twocopies of the g (t) shaping pulse. These double length symbols have twicethe energy, so the detection process will be more immune to noise; thevalue of σN 0 (and hence κ) increases by

√2, but the signal received when

a transmitter is present increases by a factor of 2. By integrating fora large number of symbol periods, we can reliably detect extremely weaktransmitted signals in the presence of a large amount of noise. On the otherhand, the effect of non-idealities in our integrator will become accentuatedas we try to integrate for longer periods of time.

On-off keying: In this case, our objective is to determine whether or not thesymbol transmitted in each symbol period is a 0 or a 1. To do this,we again compare the value of rk with a threshold κ at the end of eachsymbol period. In this case, integrating for multiple symbol periods isnot an option for improved reliability at the receiver. Thus, to achievethe desired level of robustness, we must carefully select the symbol periodlength used by the transmitter.

Antipodal signalling: In this case, we again check the value of rk producedby the integrator at the end of each symbol period. The possible valuesare given by

rk =

½αβEg + n0k if sk = 1−αβEg + n0k if sk = −1

Noting that the noise has zero-valued mean, so that n0k is as likely tobe positive as negative, the optimal detection strategy is to decide thatsk = 1 if rk > 0 and sk = −1 if rk < 0. One nice property of antipodalsignalling is that we don’t need to select a threshold at all (if you like, thethreshold is always 0). All we need is to detect the sign of the integratoroutput at the end of each symbol period. Again, robustness to noise canbe increased by extending the duration (and hence energy) of each symbolperiod.

5.3 Design of Shaping Pulses

The shaping pulse is a kind of code that the receiver is looking for. We have al-ready said that long shaping pulses (i.e., long symbol periods) will give increased


robustness to noise and interference. At the end of the previous sub-section, weconsidered shaping pulses which alternate between +1 and −1. Smoother pat-terns (typically windowed sinusoids) can be much more interesting from theperspective of bandwidth preservation, but we will not consider them here dueto limited time, and the increased practical complications of matched filtering.For your ELEC3117 project, strict bandwidth conservation is unlikely to be asignificant issue.For practical reasons, you might not have the luxury of transmitting

both negative and positive levels. For example, if you are using an IR (in-frared) system, you only have the opportunity to transmit positive levels oflight. As another example, you might well be using pre-existing RF modula-tion/demodulation modules which give you access only to the amplitude of themodulated RF signal. You can readily obtain 433MHz transmit/receive mod-ules of this form from electronics hobby stores. In any event, the best way towork in such an environment is to add a constant to the otherwise signed signalx (t) so as to render it strictly positive. Thus, for example, if g (t) consists ofan alternating sequence of 1’s and −1’s, you have only to add 1 to x (t) to geta signal which alternates between 0 and 2. It turns out that this need not haveany impact upon our optimal matched filtering receiver, so long as the matchedfilter is insensitive to the addition of constant signal offsets. To arrange for this,it is sufficient to ensure that the shaping pulse has a mean value of 0 (prior toadding offsets), i.e., Z T

0

g (t) dt = 0

This simply means that g (t) spends as much time in the 1 state as it does inthe −1 state. The matched filter h (t) will then also have have zero mean. Evenif you are not forced to signal only with positive amplitudes, it is always a goodidea to arrange for the shaping pulse to have zero mean, since then the receiverwill be insensitive to constant voltage offsets which might appear in your circuitfor any number of reasons — e.g., opamp input voltage offsets, background lightin an optical signalling scheme, etc.The second consideration we mention here applies when you wish to dis-

tinguish between multiple different transmitters, as in the garage door openerexample. Suppose each transmitter has a separate shaping pulse (or code), gi (t),where i is the index of the transmitter. It is important that the matched filterfor transmitter i is insensitive to the shaping pulse used by another transmitterj 6= i. That is, we wantZ T

0

gi (t) gj (t) dt ≈ 0, whenever i 6= j.

More generally, we need to recognize that the various transmitters are notlikely to be synchronized with each other. This means that interference fromtransmitter j may be any shifted copy of gj (t), as far as the matched filter fortransmitter i is concerned. Ideally, then, we would like the following property


to hold: Z T

0

gi (t) gj (t− τ) dt ≈ 0, for all i 6= j and all τ ∈ (−T, T )

Equivalently, we want

gi (t) ∗ gj (−t) u 0, ∀i 6= j

One way to arrange for this is to make gi (t) and gj (t) oscillatory waveformswith different frequencies. In the case where the transmitted signal is a repeatingcode (as in the garage door opener), we know that the signal produced by anytwo transmitters, i and j, are repeating patterns with different shaping pulsesgi (t) and gj (t). In this case, the objective of good code design is to make surethat Z T

0

gi (t) gj (t− τ modT ) dt ≈ 0, for all i 6= j and all τ ∈ [0, T ]

The important difference here is that we are interested in the cyclically shiftedversion of gj (t) — shifted by τ and then wrapped around in the symbol interval[0, T ].In general, these “orthogonality” conditions cannot be achieved exactly in

practice, but they can help you to understand the desirable properties for shap-ing pulses. If the shaping pulses are long and are chosen randomly, you caninterpret codes from other transmitters as random noise. Again, the longeryour receiver can integrate for, the more robustly it will discriminate its owntransmitter’s signal from the other “noise” signals.

5.4 Clock Synchronization

In the preceding treatment, we have assumed that the receiver is perfectly syn-chronized with the transmitter. That is, the receiver is assumed to know exactlywhen each symbol period starts and finishes, so that it can correctly multiplythe received signal by h (t) and integrate over the relevant period. In practice,the receiver is not normally synchronized a priori, so that synchronization is anextremely important element in the overall detection process. Synchronizationis a big topic, which we cannot fully cover here, so we will provide only sufficientinformation to get you going.Let us assume that both the transmitter and the receiver use stable crys-

tal oscillators whose frequencies are very close to each other — e.g., to severalparts-per-million. This means that the initially unknown delay between thetransmitter’s clock and the receiver’s clock changes only very slowly. Just howslow you can make this (or need to make this) will depend on the details ofyour design. The most obvious receiver synchronization strategy is a kind oftrial-and-error approach. To understand this, consider the case of the endlesslyrepeating code (as in the garage door opener example), and suppose we use thematched receiver shown in Figure 2. The output of the receiver rk, is maximized


when the transmitter and receiver use exactly the same symbol periods. Sincethe switches in the receiver are operated by a digital logic circuit, all that is re-quired is a sequential state machine that progressively adjusts the window overwhich integration occurs, hunting for the window which maximizes rk. That is,the receiver forms

rτkk =

Z T

0

x (t+ kT + τk) h (t) dt,

incrementing the delay τk, in each successive symbol period k, until it has triedvalue of τk which span the interval [0, T ), at which point it determines thevalue of τk which yielded the largest value of r

τkk . If all we are doing is trying

to determine whether or not a transmitter is present, we simply compare thismaximum value of rτkk with the detection threshold κ, discussed above3. Weneed, of course, to decide on a step size

∆τ = τk+1 − τk.

This is simply the amount of extra delay we add at the end of one integrationperiod (of duration T ) before commencing the next integration period. Thenumber of periods that we will need to consider is equal to T/∆τ , so it willtake us T 2/∆τ seconds to find the best match. There is thus a clear trade-offbetween the robustness achieved by integrating for long periods of time (largeT ) and the delay precision ∆τ which can be achieved within a given amount oftime.The above simplistic hunting strategy can be improved in a number of ways,

if required. The classic approach is to perform an initial hunt for the delay τ ,using a coarse step size ∆τ , and integrating for only a short period of time (e.g.,only one symbol period, or even a fraction of a symbol period). This first stage,produces a number of promising candidates which yield largish values for rτkk ,after which a second stage considers just these few candidates, integrating forlonger, and making fine adjustments to τk. To do this under digital control,you would probably need to incorporate an A/D converter into your design,together with an FPGA or micro-controller to manage the hunting algorithm.This adds a level of complexity that you might not be prepared to considerwithin the scope of your ELEC3117 project, but it is good to be aware thatsuch possibilities exist.So far, we have considered only the case where the signal x (t) consists of

a repeating code. This conceptually allows us to hunt for a match, for as longas we like, since every symbol period should be the same. If on-off keying isused, you can use essentially the same strategy to hunt for an initial lock tothe transmitter’s symbol clock, bearing in mind that your initial estimate forτk might be corrupted by the fact that the optimal delay is tested (integrated)during a symbol period when the transmitted symbol is 0. To avoid this, youmay hunt through multiple iterations of the sequence of possible delays and youmight design your transmit strategy to include a long period during which the

3Equivalently, we compare each rτkk with κ and report that the transmitter exists when a

value is found which exceeds κ.


symbol which is transmitted is constantly equal to sk = 1. Once the initial lockhas been obtained, the ongoing decoding process needs to be prepared to makeminor adjustments to the symbol clock, inserting or removing a clock cycle everyso often from the receiver timing sequence. One way to do this is to run multiplematched filter circuits in parallel, each operating with a slightly different delay(e.g., one with a delay slightly less than the current estimated value, and onewith a delay slightly larger than the current estimated value). The matchedfilter which yields the largest value for rk indicates the best estimate of thedelay to be used during the next symbol decoding period. If the symbol isdecoded as a 0, no adjustment is made, since there is no useful synchronizationinformation in x (t), otherwise, a 1 is decoded and the symbol clock delay isadjusted as appropriate for the next symbol.The above strategy can also be used for antipodal signalling, except that a

good lock to the symbol clock is indicated by the magnitude (i.e., the absolutevalue) of rk, regardless of whether it is +ve or −ve. To ensure that the initialhunt for a good symbol lock works correctly, it is a good idea to design yourshaping pulse g (t) such that it is not close to a shifted version of −g (t). Thus,a periodic square wave pattern for g (t) would not be a good choice.

5.5 Modulation and Variations on the Theme

You are no doubt familiar with the concept of amplitude modulation, wherea periodic waveform (usually a sinusoid) is scaled by the information bearingsymbols. Modulation is in fact already covered by the description provided inthe preceding section. On the one hand, we can always define g (t) to be therelevant oscillatory waveform, in which case sk provides the modulating ampli-tude. More generally, we can construct our shaping pulses from the productof a high frequency carrier waveform c (t), and a more slowly varying envelopefunction ρ (t), i.e.,

g (t) = c (t) · ρ (t)Here, ρ (t) has bounded support, of duration T seconds, whereas c (t) can be anunbounded oscillatory carrier.In principle, nothing stops us from applying the techniques described in the

preceding sections for optimal matched receiver design and clock recovery. Inpractice, however, there is one problem. During clock recovery, it is importantthat our receiver’s search precision ∆τ is significantly smaller than a single cycleof the carrier, since otherwise the match may be very poor. However, there areusually a very large number of cycles of the carrier in each symbol period. Thismeans that T/∆τ is very large — thousands, millions, even billions, dependingupon the context. In view of this difficulty, the clock recovery system is generallydecomposed into two phases: carrier clock recovery; and symbol clock recovery.Once the carrier has been recovered, we can use a much coarser step size ∆τ tosynchronize the symbol clock, so long as the symbol period T is a multiple of


the carrier period. To see this, note that equation (4) can be written

rk =

Z T

0

y (t+ kT ) · h (t) · dt

=

Z T

0

y (t+ kT ) · βc (t) ρ (t) · dt

= β

Z T

0

[y (t+ kT ) c (t+ kT )]| z d(t)

·βρ (t) · dt

In the third line of the above equation, we have used the fact that c (t) =c (t+ kT ) for all integers k. Evidently, it is sufficient to demodulate the re-ceived signal y (t) by multiplying it by the recovered carrier c (t), after whichthe matched filter operates on the demodulated signal d (t), using the effectiveshaping pulse, ρ (t). The step size ∆τ required to lock onto the symbol clockneed only be small in relation to the features in ρ (t), which is generally a muchlower bandwidth signal than g (t).For carrier clock synchronization, there are a number of techniques which

can be employed. To ensure a unique result, it is best if the envelope componentof the shaping pulse has a non-zero mean value. For the sake of simplicity, wewill assume that Z T

0

ρ (t) · dt > 0 (5)

In the simplest case, ρ (t) ≥ 0, ∀t, but this is not strictly necessary. Equation(5) is the condition required for a pilot tone to exist, meaning that the receivedsignal y (t) contains some component of the original carrier waveform. To seethis, note that demodulating by the correct carrier leaves

d (t) = y (t) c (t)

= αx (t) c (t) + n (t) c (t)

= αc2 (t)Xk

skρ (t− kT ) + n (t) c (t) ,

which has a positive average value.One way to lock onto the carrier, then, is to adjust the phase of the local

carrier at the receiver until a low-pass filtered version of the demodulated signald (t) becomes as large as possible. Indeed, this is one method that can beused. A more common strategy, however, is to generate a quarter cycle delayedversion cq (t) of the ideal carrier waveform and arrange for y (t) cq (t) to havean average value of 0. This is the basic idea behind the common phase lockedloop (PLL). Let us be more precise. Let c0 (t) be the carrier signal whichthe receiver will use to demodulate y (t). Then we want the average value ofy (t) c0 (t) to be as positive as possible. Now consider the half cycle delayedcarrier, c0 (t− T/2). Assuming that the carrier has a 50% duty cycle, we havec0 (t− T/2) = −c0 (t), so that y (t) c0 (t− T/2) should have an average value


R2

y(t)

CR1R1

cq(t)>0

R3

cq(t)<0 -cq(t)y(t)

VoltageControlledOscillator(VCO)

fδFreq.Divider(counter))(tcq

)(0 tc

crystal

R2

y(t)

CR1R1

cq(t)>0

R3

cq(t)<0 -cq(t)y(t)-cq(t)y(t)

VoltageControlledOscillator(VCO)

fδFreq.Divider(counter))(tcq

)(0 tc

crystal

Figure 3: Simple phase locked loop, using a 1’st order low-pass filter (formedby R3 and C), an integrator circuit driven by positive and negative versionsof y (t), and a voltage controlled oscillator (VCO). The output of the VCO isdivided down to form the receiver’s carrier clock c0 (t) and a quarter sampledelayed version cq (t) = c0 (t− T/4).

which is as negative as possible. Between these positive and negative extremes,we expect y (t) c0 (t− T/4) to have an average value of 0. If we find that theaverage value of y (t) c0 (t− T/4) is positive, the receiver’s carrier clock c0 (t)must be running ahead and needs to be delayed a little. Similarly, if the averagevalue of y (t) c0 (t− T/4) is negative, the receiver’s local version of the carrieris running behind and needs to be advanced a little. This is achieved by thesimple PLL circuit shown schematically in Figure 3.Before concluding this section, we note that there is no need to use the same

shaping pulse g (t) for each symbol sk. We can generalize equation (1) to

x (t) =Xk

gsk (t− kT )

where there is a distinct shaping pulse gsk (t) for each possible symbol valuesk. For binary signalling, we let sk take one of the values 0 or 1 and definetwo shaping pulses g0 (t) and g1 (t). In the preceding treatment, each of theseshaping pulses was a scaled version of the single waveform g (t). However,this is not necessary. A popular alternative is to use oscillatory waveforms (orcarriers) with two frequencies — this is called frequency modulation. These couldbe sinusoidal carriers, square waves or anything else, but the signal generationand matched filtering processes become particularly simple for square waves,even if the bandwidth spread is not so good. If g0 (t) and g1 (t) are not scaledversions of the same waveform, we will need two separate matched filters (i.e.,two integrators) in the receiver, one for each scaling function. In each symbol


period k, we form

rk,0 =

Z T

0

y (t+ kT ) h0 (t) dt and rk,1 =

Z T

0

y (t+ kT ) h1 (t) dt

If rk,0 is larger than rk,1 we decode the symbol as sk = 0. Otherwise, we decidethat sk = 1. This is an optimal detection rule so long as h0 (t) = βg0 (t) andh1 (t) = βg1 (t) involve the same scaling factor β. For maximum robustness, thematched filter for rk,0 should not respond to g1 (t) and the matched filter forrk,1 should not respond to g0 (t). This can be arranged by designing g0 (t) andg1 (t) as orthogonal signals, i.e.,Z T

0

g0 (t) g1 (t) dt = 0

Carrier and symbol clock synchronization can be carried out using essentiallythe same techniques which we described above.

5.6 Digitally (or Software) Defined Radio

In the foregoing discussion, we have supposed that the inegration process re-quired for matched filtering is carried out in the analog domain. An alternativeapproach is to convert the incoming signal y (t) into a sampled digital signal

y [n] = y (t)|t=n/fs (6)

with sampling frequency fs, and then replace all inegration operations withsums. Thus, for example, equation (4) becomes

rk =

TfsXn=0

y [n+ kTfs] · h [n] .

This approach is fundamentally equivalent to analog integration, so long as thefollowing conditions are met:

1. The sampling process in equation (6) must not involve significant aliasing.That is, prior to sampling the continuous received signal y (t), it must bepassed through a suitable anti-aliasing filter which strongly attentuatescomponents with frequencies above fs/2. The most important thing thatthis does is to remove noise power. Without the anti-aliasing filter, noisepower is effectively amplified by sampling, which renders the receiver muchless robust to errors.

2. The A/D converter used during sampling needs sufficient numerical preci-sion to cover the range of expected signal amplitudes, without adding toomuch noise of its own (due to quantization). In some applications, thismight require quite a high precision A/D converter.


Ideally, the sampling clock has the property that Tfs is an integer, meaningthat there are a whole number of samples in each symbol period. One way toarrange for this is to drive the sampling clock from a PLL which is locked to anunderlying carrier frequency, assuming that there is such a carrier and that thesymbol period is designed to be an integer multiple of the carrier period. This,however, still relies on the presence of analog components for carrier synchro-nization and demodulation. For an all-digital receiver, the situation is a bit morecomplex. The simplest approach is to use a sampling clock frequency which isso high that we can represent the symbol period (and any carrier period) as alarge integer multiple of the sampling clock in the receiver, adding or removinga sample from this period from time to time so as to achieve synchronization.Digital processing has a number of advantages over analog matched filter-

ing. One of these is that the system is easily reconfigurable to handle differenttransmission schemes; this is particularly true if the system is implemented insoftware, using a DSP or general purpose CPU. Another advantage is that thedigital processor does not introduce any errors of its own, after the initial quan-tization and aliasing distortions produced by sampling. This means that thedigital integration process does not suffer from the problems of analog compo-nents whose gains do not match precisely — e.g., the positive and negative inputsto the integrator in Figure 2.Perhaps the most significant advantage of digital processing is that multiple

matched receivers can be implemented simultaneously by fast hardware proces-sors. This is particularly important for clock synchronization. In Section 5.4,we suggested a hunting technique for synchronizing the receiver’s clock withthe transmitter. This hunting technique requires the matched receiver to beapplied many times in sequence, shifting the clock by ∆T each time, until thebest match is found. With only one analog matched filter, this can take a longtime, since each step in the hunting process requires T seconds and the numberof steps is T/∆T . To speed the process up, multiple analog matched filters canbe implemented, but this is costly and may suffer from mismatches amongstthe parallel analog circuits. A more cost effective solution is to run multipledigital matched filters in parallel. One way to do this is to load 2T seconds ofthe received signal y [n] into memory and then to evaluate

r(i) =

TfsXn=0

y [n+ i∆Tfs] · h [n] , for each i ∈∙0,

T

∆T

¶∩ Z

searching for the value of i which maximizes r(i).

6 Micro-ControllersMicro-controllers are small microprocessors which are targeted at the design ofstand-alone electronic consumer products of moderate to low complexity. Themain distinctions between a micro-controller and a general purpose CPU are:


1. Micro-controllers are principally designed to work with their own inter-nal RAM and programmable ROM, rather than interfacing with externalmemory chips.

2. Micro-controllers normally include additional embedded functions, suchas A/D and D/A converters, LCD display drivers and the like, so as toreduce the number of external chips that will be required for a completesolution.

3. The main external interfaces provided by micro-controllers consist of acollection of I/O lines. These are generally software configurable to beused as inputs or outputs, for either analog or digital purposes, so that asmall package can be used to serve a large number of different purposes.

4. The CPU inside most micro-controllers is fairly simple, with an 8-bit or16-bit data path and only a small set of assembly language instructions.

The features described above serve to keep chip count and power consumptionto an absolute minimum, since these are usually important issues for electronicproducts. A small number of micro-controllers allow you to attach externalmemory chips, but by the time you go to this amount of effort, perhaps youshould be considering a real CPU.Micro-controllers are available from various manufacturers. For your

ELEC3117 design project, we suggest that you use either the PIC micro-controllers from “Microchip Technology Inc.” (www.microchip.com), or one ofthe TMS430 micro-controllers from Texas Instruments Inc. The PIC micro-controllers use an 8-bit data path, while the MS430 series are 16-bit micro-controllers. As for sourcing components and development/programming kits,we have the following recommendations:

• The Electronics Workshop keeps stock of several micro-controllers, whichthey can sell to you for a good price. The Electronics Workshop alsohas quite a few PIC programming kits, with development software, whichthey can lend to you for a limited period of time, subject to a deposit(fully refundable). These kits can be used to program the afore-mentionedchips, plus a range of other ones. If you wish to purchase your own PICprogrammer, the staff in the Electronics Workshop are happy to help youlocate suppliers, or even to arrange the purchase. Prices tend to be abit less than $100. The PIC micro-controllers come in easy-to-use (andeasy-to-solder) DIP packages.

• The MSP430 micro-controllers are quite a bit more difficult to work withthan the PIC series, but they are more powerful. One difficulty is theuse of a low supply voltage (typically 3.3V). The other is the fact thatall packages are of the surface mount variety (as opposed to DIP), whichcan be difficult to solder or otherwise connect into your circuit unless youhave finely honed skills. Nevertheless, one very interesting product is theMSP430 eZ430-F2013 development tool. This tool is entirely packaged in


a device the size of a USB thumb drive, which contains a MSP430F2013component mounted on a convenient break-out board, to which you cansolder. This development tool costs around US$20. The local supplierfor these micro-controllers is “AVNET Electronics Marketing.” We arestill trying to arrange a special rate for purchasing these devices (and theprogramming tool), but you might like to contact AVNET yourself.

7 Programmable LogicMany designs call for some significant amount of digital logic, to interface com-ponents, implement state machines or control complex timing and addressingsequences. Constructing this logic from discrete TTL/CMOS logic devices is of-ten either practically infeasible or overly expensive, in terms of both componentcount and power consumption. CPLD’s (Complex Programmable Logic De-vices) and FPGA’s (Field Programmable Gate Arrays) are designed to addressexactly these situations. Both types of devices contain internal arrays of pre-defined logic elements and flip-flops, whose interconnects can be programmedelectronically. FPGA’s tend to be much more sophisticated than CPLD’s, pro-viding many more flip-flops, more sophisticated logic elements (usually definedby programmable lookup tables), and often quite a bit of on-chip RAM. In fact,modern FPGA’s are so densely integrated that it is possible to program them toimplement entire general purpose CPU’s (potentially many interacting CPU’son the same chip), in addition to dedicated logic and arithmetic functions.Fortunately, most of the complexity of programming CPLD’s and FPGA’s is

abstracted for you by sophisticated design tools, which do their best to make theinternal architecture of the device transparent. All design tools support someform of schematic capture technique to describe the digital circuit you want toimplement. To facilitate this, libraries of standard digital logic components areprovided for you to place and connect on a schematic diagram. You can thenturn your own schematics into new library components to be incorporated intomore complex designs. Ultimately, everything is built up from gates and flip-flops, including all the standard library components. Subsequent synthesis toolsthen map the configuration onto the device’s internal resources and allow youto assign component pins to logic lines in your digital circuit. As an alternativeto schematic capture, it is possible to use a hardware description language todescribe your digital circuit. The two most popular hardware description lan-guages are VHDL and Verilog. These are often both supported by the relevantmanufacturer’s design tools.If you would like to learn techniques such as these and use them in your

ELEC3117 design project, the Electronics Workshop has some tools which willfacilitate the process. For relatively simple designs, you can use the XC9572Xilinx CPLD, which comes in a square 44-pin package. The Electronics Work-shop has a number of programming tools which can be used to program theXC9572 via a parallel port; once you are done, the chip can be removed andmounted on a socket (the workshop has these as well) which is relatively easy


to solder to, having widely spaced pins. Alternatively, the workshop has a num-ber of “breakout” boards which allow you to mount an XC9572 and then wirethe pins to your own breadboard using screw-type terminals — these requireno soldering, although you need to be careful to keep your leads short. Theworkshop also has a number of much larger demonstration boards they can lendyou, which can be used to program and subsequently deploy a Xilinx SPARTANFPGA, the XC2S200. You cannot remove these chips and use them separately inyour project, but you can interface your prototype to the demonstration boardthrough the edge connectors which are provided. The Electronics Workshop canoffer you some help with this if required.In order to encourage you to learn and use CPLD’s (or FPGA’s) for your

project, a demonstration of the process will be given in lectures. A number ofthe lab demonstrators may also be able to help you in this regard. Softwarefor programming the Xilinx components can be obtained from the ElectronicsWorkshop and installed on your PC under an open license. This software cor-responds to version 4.1 of the Xilinx Foundation tools. The software install andruns without incident on Windows 98 and Windows 2000 operating systems.Unfortunately, the software is not fully compatible with Windows XP, for thefollowing two reasons:

1. After running the usual install script, you will find that your WindowsXP machine does not boot up again properly. You can overcome thisproblem by powering down the machine and booting again, selecting the“Last Good Version” option. You then need to go into the “System” areaof the control panel, select the “Advanced” tab and click “EnvironmentVariables,” doing the following:

• Create a new environment variable named “Xilinx” and set it to thevalue “C:\Xilinx” — assuming you installed the development tools inthat location.

• Edit the “path” environment variable, adding “C:\Xilinx\bin\nt” tothe path list — entries in the path list are separated by semicolons(i.e., the “;” character).

After you have done the above, you will need to reboot your system onemore time; otherwise, when you use the Xilinx tools they will continuallyreport that the “Xilinx” variable has not been set.

2. The software methods for accessing the parallel port under Windows XPare fundamentally different to those offered by Windows 98 and Windows2000. As a result, even after following the above steps, you will not actuallybe able to program the Xilinx chips from Windows XP, although you cando everything else and bring your files to the lab or workshop to programthe chip.

To avoid the problems described above, an alternate approach is to downloadthe latest Xilinx development tools from www.xilinx.com. There is a free version


for web-based download. Unfortunately, though, the install executable is nearly1GB in size.

References[1] P. Horowitz andW. Hill, The Art of Electronics (2 ed ), Cambridge University

Press, 1989

chapter7 circuits

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