1 of 20

Changes /1 to /2 FTM PC3550M

Incorporating changes from FDR/PRR review of March 2018

Sheet 2 - ATCA PSU

Correct silkscreen for C323 (82uF/100V). Move Polarity marker (+) to other pin.

Sheet 2 – Removal of CPLD#1 (Motivation is to remove need for Xilinx ISE design and programming software.)

(After this modification, the FTM will no longer automatically switch from Hub to Node mode

depending upon slot position, this now being done manually using the link headers below)

Remove CPLD U87 and replace with a 74LVC8T245 wired as diagram below.

Also remove U82, U92, U136 and D1 with associated Rs and Cs and links PL29, LO18 and LO19.

3 pins intentionally

left unconnected

2 of 20

Replace each of test-pads LK40, 42 – 46 with 2-pin header having new pin connected to ground,

similar to drawing below. Could these links be combined into a single 6 x 2-row header block.

Also remove Resistors R442 – R445 & R448 (connected to HW_ADDR<*> signals)

Because the replacement backplane driver for TTC-INFO no longer has a select pin, the signal

DRIVE_INFO_N from PL4 pin 1 now goes to Control FPGA U62 pin A11 on sheet 8 in which the MGT

output could be muted. Most of the outputs are not connected to the backplane when FTM is in a

Node slot)

Rename signal IN_SHELF_N to DEBUG_ADDR_N and add a 2-pin header from this to ground.

Sheet 2 – Reinstate Auto selection of Hub/Node mode using NOR gate.

Add the following circuit, a NOR Gate with capacitor and three FETs, to sheet 2 with components

placed near U82 and PL4.

The NOR gate is a Texas Instruments SN74LVC1G27DBVR part in SOT-23-6 package.

(ie DigiKey # 296-17119-1-ND) Pin-swap pins 1,3 & 6 as needed.

3 of 20

Change note text on schematic above PL4 from “LINK ALL A-B FOR HUB1 USE, ALL OPEN FOR NODE

USE” to read “LEAVE OPEN FOR NORMAL USE, FOR COMMISSIONING ONLY”

Sheet 2 – Change SW3 for a two position switch

Replace SW3 with APEM part TL36W0050. (ie. Farnell 1082497).

Electrically and footprint equivalent to existing TL39W0050 which has 3 rest positions.

Sheet 2 - LEDs

LEDs DS21 – DS23 Anodes are now connected to VCC_3V3 and driven by U62 instead of CPLD (see

sheet8)

Add a new red LED and series resistor to schematics and place LED into vacant space of LP6.

New signal ALERT_LED_N connects back to U62 pin B15.

Sheet 7 – Add Green front panel LED for PLL status.

Add a fourth instance of LED circuit with FET gate driven by signal “PLL0_lock”.

Sheet 7 – Remove Unused reconfigure circuit

Remove U67 , U68 , R98 , R431, C822.

Signal C_RECONFIG_B on U62 pin M23 to be deleted.

4 of 20

Sheet 8 –Add 3.3V power to bank 18 of U62 , Reconnect LEDs

Rewire the VCCO_18 to VCC_3V3 (instead of ground). Add a 100uF capacitor as per bank12 of U62.

Wire signals HUB1_LED_N, NODE_LED_N and AERR_LED_N to pins A13, A15 and B14 of U62.

Connect U62 pin Y25 to ground and nearby add NOTE “PCB version”

Sheet 8 – Add rotary switch for setting Crate Address.

Switch is a hexadecimal rotary switch from APEM type P36103 ( ie Farnell # 1082472. )

Connect each of the above four SHELF_NUM? signals to unused pins of Bank18 of U62. Suggest using

pins K13, J14, J16, H16 , connected to suit routing. Suggest placing switch to South / SE of U62.

5 of 20

Sheet 7 – Add two diodes to PL24

Prevents back-feeding of D1 + D2_PROGB signals which may be pulled low elsewhere.

Use one BAT54C package: (BAT54C available in SOT23 from Farnell 1843689)

Sheet 7 – FLASH SPI - Link header added to disconnect from U62

Insert a link header between U62 Control FPGA and signals DFLASH1_SELN and DFLASH2_SELN.

Add two 4.7K pullups to DFLASH1_SELN and DFLASH2_SELN.

Sheet 7–Create Connections to PCA9641 on sheet 17

On sheet 7, rename two signals on U62 Bank12 (keeping resistors). and and wireU92 on sheet 17

Pin AE25: MPOD_SCL to FPGA_MPOD_SCL

Pin AF25: MPOD_SDA to FPGA_MPOD_SDA

6 of 20

Sheet 7 - Removal of CPLDs #2 and #3

There are some loose-ends which are reconnected by renaming signals on U62 I/O bank 12

Sheet 33 - Removal of CPLDs #2 and #3

Sheet 33: remove R292, U35 and U52 (CPLDS #2 & #3) with their attached capacitors.

Remove PL15, PL16, SW2, PL17, U27 with their attached R’s and C’s.

(This leaves only U122 and U123 (74LVC1G17) and their associated components on the sheet. )

Sheet 34 - FLASH VIO supply

TLVH431 Symbol is wrong, anode and cathode swapped. Update D2, D3 and D4.

Also change value of R273 and R274 to 22ohm and use 0603 package,

and change value of R314 to 12 ohm and use 0603 package.

Sheet 34 – SPI Switch simplified

Remove U46, U47, U48 , U53 and U54.

Remove LK11 and signals CFLASH_SELN and FLASH_MOSI_2V5.

Reconnect signals:

CFPGA_MOSI to CFLASH_MOSI

CFPGA_CCLK to CFLASH_CLK

CFPGA_CSN to CFLASH_CSN

7 of 20

Sheet 35 – Replace U15 with linear regulator Texas Inst. TPS7A4518

Replace U15 with the following circuit, having also removed R242 and LC3.

Ensure C37 , C546 and regulator input are (re)connected to VCC_2V5.

Replace Shunt resistor RS2with 0.01 ohm part LVK25R010FER ( ie Farnell # 1462327)

Sheet 35 – Upgrade U23 DC/DC to 10A part

U23. Replace with the slightly larger PTH08T240WAD voltage converter, wired as follows.

R256 value remains at 12.1k ohm.

*

*

* = sense wires, ends

located near OC8-OC9

8 of 20

Sheet 35 – Upgrade U69 DC/DC to 50A part.

Future firmware designs may require more current from the VCCINT_1V0 supply.

The new DC/DC a PTH08T250WAD uses more board area, but will hopefully fit in same space

between adjacent DC/DC and the front-panel connectors.

The new pinout has been super-imposed on the existing schematic symbol.

Existing capacitors are retained, but some resistors need changing:

R434 to 39K , 1% or 5%. R410 changed to 330K, 1% or 5%.

Sheet 35 – Upgrade Current sensing shunts

Replace U75 and U76 by a 0.0005R 3W shunt such as a Vishay/ Dale WSL4026L5000FEB or the

smaller WSL2726L5000FEB

Replace U21 by a 0.002R/2W shunt from same range and footprint, an Ohmite LVK25R0002FER.

Sheet 35 – Add test-pads to MGTAVCC_1VX supply

For measuring voltage drop across power-plane, add 3mm square pads to land test-probes.

Add 9 pads topside of PCB connected to MGTAVCC_1VX supply, 4 per U10 and U11 located near

corners of their BGA package, plus one pad for U62 located near lower-right corner of BGA.

9 of 20

Sheets 35 and 36 – Add FPGA Overvoltage Protection

Add 7 instances of the following circuit to each of the DC/DC converters as given in the table below:

LTC1696 is in 6 lead TSOT-23 package, BSS138L is in SOT-23 package.

SUPPLY INHIBIT pin Rs Resistor value LTC1696 Location

VCCINT_1V0 U69/1 205 OC2 – OC3

MGTAVCC_1VX U70/1 255 OC2 – OC3

MGTAVTT_1V2 U23/11 * 412 OC8 – OC9

MGTVCCAUX_1V8 U15/4 1.02k OC8 – OC9

VCC_1V8 U104/11 1.02k OC2 – OC3

VCC_2V5 U96/11 1.74k OC2 – OC3

VCC_3V3 U90/11 2.55k OC2 – OC3

* = U23 now a PTH08T240WAD part

The outputs of all the LTC1696s are ORed together using schotky diodes onto an OV ALARM signal

which drives a front-panel LED. The OV_ALARM signal is also buffered onto the IPMC IPMIO(0) pin.

Short

connection

near sense

wires

10 of 20

Sheets 12, and 19 – Change Virtex-7 Bank-0 supply to 1.8V

Modify U11 as follows:

Repeat above for U10 on sheet 19.

Insert buffers

11 of 20

Sheet 32 – JTAG chain repair from changing Virtex-7 bank-0 supply

and from removal of CPLDs

Insert into JTAG chain, a 2.5V/1.8V level translator upstream of D1_TDI and a 1.8V/2.5V level

translator downstream of D2_TDO as shown below:

Remove JTAG signals CPLD1_TDI , CPLD1_TDO, CPLD1_TCK and CPLD1_TMS and their series

resistors, and bridge across to next device. Repeat for CPLD2 and CPLD3 signals.

12 of 20

Sheet 4 – IPMC signals

Add 1k0 pull-ups to MAN_3V3 for existing signals A_OK_N, B_OK_N and MAN_INTRPT.

Add circuit with 74LVC1G17 as shown below (to connect OV_ALARM onto IPMC in SK43)

Sheets 12 & 19 – DSS FPGA Address pin and PCB Revision. Remove signal DSS1_SPARE2 (from pin B12 on U11). Similarly remove signal DSS2_SPARE2 from U10.

Connect pin B12 on U11 to ground, but leave pin B12 on U10 floating.

Add a ground to pin B11 on both U10 and U11.

(This becomes a “PCB revision” input for the DSS FPGA)

Sheets 14 and 21 – MGT polarity inverted

Signals on pins A3 and A4 of U11 need (un)swapping. Repeat for U10.

Sheets 14, 15, 21, 22 and 31 – NB7VQ14 input bias

U7, U8, U17, U16 and U64 all need 100nF capacitors placed in series on pins 1 and 4.

Pin2 should be re-connected to pin3 with 100nF capacitor added from pin3 to ground.

13 of 20

Sheet 27 – Clock selection inverted

Rewire LO26 so that a link connects HUB_SELECT to ground as shown below.

Sheets 28 and 29– Add another LEMO to monitor Reference clocks

SK14. Single LEMO replaced by dual LEMO (which matches style of others on front panel).

Note R431 should be located near U52. Sheet 28:

Sheet 29:

Sheet 37 – FAN connector

PL1, PL 2 and PL 21. Swap pins 1 & 3 on footprint. See Molex drawing AE-6410-N at

http://www.molex.com/pdm_docs/sd/022272031_sd.pdf (fixed on layout footprint)

Sheet 39 – Daughter cards

PL4, PL5, PL6 and PL7. Change pin/header-strip to socket-strip connector

Cut from MILL-MAX 32-pin socket strip , part number 310-93-132-41-001000

14 of 20

Sheet 17 –I2C Arbitration chip PCA9641 U92 added

This effectively inserts U92 into the top of the MPOD I2C bus. MPOD_SCL and MPOD_SDA need 4k7

pull-ups to VCC_3V3 as shown.

Add two zero-ohm resistor links as shown below.

(this sets a default connectivity to bypass device.)

15 of 20

Sheet 38 – Adding two more ADCs (AD7998-0)

Duplicate the circuit of the existing two ADCs but connect the four control pins (on right of symbol)

to new signals : FPGA_CONV_N, FPGA_ALERT_N, FPGA_SENSOR_SDA and FPGA_SENSOR_SCL :

Sheet 8 – and connecting these ADCs to Control FPGA

Add a 4.7K pull-ups to VCC_3V3 to each of the four signals and connect these to Bank 18 of U62.

(Suggest maybe pins A12, B12, C11 and C12 , but any convenient pins will do as the firmware can be

adjusted to suit.) Locate the resistors near the ADCs but not critical where placed.

16 of 20

Sheet 31 – Change drivers U60 & U72 for a faster part: NB7L1008M.

Use the existing 10nf decoupling capacitors on VCC_2V5 for these devices.

(One capacitor can cover pins 1 & 32 and another capacitor for pins 8 & 9)

C173 and C256 re-used and placed near pin4 of each device.

Resistors R102 and R103 no longer serve a purpose and can be removed.

17 of 20

Sheet 39 - Change of Front panel connector PL12

Change PL12 to a 2 x 8 way connector ( from a 2 x 7 way type)

A suitable part available from Farnell # 2215293.

Add two more buffer circuits as shown below.

This creates two new signals TRIG_TYPE6 and TRIG_TYPE 7.

TRIG_TYPE6 connects to the Control FPGA U62 pin AJ29. TRIG_TYPE 7 connects to U62 pin AK28.

18 of 20

Layout of Front panel LEDS

Schematic Sheets 36, 37 and 2 –

Move DS12 into LP2

Move DS24 into LP3 (space vacated by DS12)

Move DS29 into LP7 (space vacated by DS24)

Update Sheet37 to show new grouping of light-pipes. Move DS29 circuit over from sheet 36.

Schematic Sheet 32 - Move PL32 JTAG connector nearer front panel

Rotate PL32 90deg clockwise and move into space on the other side of U104.

Also move associated components , U97, U99 , R155, R156, C331 and C334.

19 of 20

Component change – MMCX connector

Change MMCX S/M connectors to MMCX through-hole part.

( Because MMCX S/M connectors are easily ripped-off PCB)

Due to change in footprint from Surface-mount to Through-hole, the following MMCX will need

tracks moved to underside of PCB so as to remove stubs on very-high speed signals:

SK38, 39, 41 & 42. SK7 to SK10 , SK17 to SK20, SK 12 & 15. SK13 and 16. SK21 to SK24. SK33 & 34.

New or updated Constraints

Sheet 28, in and out of R431

The following are 50 ohm single-ended at 1 GHz

LEMO_MONITOR

SK14 pin 1

Sheet 29, in and out of U35

Following are 100 ohm differential at 1 GHz

MGTREF0_P

MGTREF1_P

MGTREF_P

Sheet 31, in and out of U64, U60 and U72

These differential signals should be upgraded in speed If not already at 10 GHz.

TTCINFO_OUT_P

TTC_INFO_DSS1_P

TTC_INFO_DSS2_P

TTC_INFO_BACK1_P

TTC_INFO_BACK2_P

All the N04_TXD_C_P ... N15_TXD_C_P and HUB_TXD_C_P

All the N04_TXD_P ... N15_TXD_P and HUB_TXD_P

20 of 20

Updating Notes on Schematic

Sheet 2

Remove notes with BANK1 and BANK2 , located at bottom of sheet.

Add note near PL4

LINK ALL A – B FOR HUB1 USE

ALL OPEN FOR NODE USE

Edit note near PL34 to say

LINK FOR MANUAL POWER-ON

Sheet 7

Add near PL6

LINK 1-2 TO FORCE MAC ADDRESS

Add near PL24

LINK 1-2, 3-4 AND/OR 5-6 TO CONFIGURE FPGAS

Add near PL7

LINK 1-2 AND 3-4 TO ENABLE IPBUS ACCESS TO FLASH

Sheet 26

Add under PL19

LINK BOTH 1-2 OR BOTH 2-3 FOR I2C ACCESS

Sheet 29

Add under PL19

LINK TO SELECT MGTREF1

OPEN TO SELECT MGTREF0

Sheet 35

Edit note near U69 that begins with “VCCINT” to say “MAX 50A”