ceng 331 course slides chapter 5

7/23/2019 CENG 331 Course Slides Chapter 5

1/73


2/73

11/99 Computer Organization & Architecture Ch.5 - 3.0

T B P : N ?T B P : N ?

T F C C C

T T : D S C P

Control

Datapath

Memory

ProcessorInput

Output

inst. set design technology

machinedesign

Arithmetic


T B P : T P PT B P : T P P

P : I C C

P ( ) :

C C

I ... S :

A : O D :

CPICPI

Inst. CountInst. Count Cycle TimeCycle Time


3/73


H D P : H D P :

1. A => ISA

2. S

3. A 4. A

.

5. A



4/73


TT MIPSMIPS I FI F

A MIPS 32 . T :

R

I

J

T : : , , : : : / : :

op target address02631

6 bits 26 bits

op rs rt rd shamt funct061116212631

6 bits 6 bits5 bits5 bits5 bits5 bits

op rs rt immediate016212631

6 bits 16 bits5 bits5 bits


S 1 : TS 1 : T MIPSMIPS SS

ADD S B

U , ,

U , ,

OR I

, , 16

LOAD STORE

, , 16

, , 16

BRANCH

, , 16










5/73


L R TL R T

RTL A op | rs | rt | rd | shamt | funct = MEM[ PC ]

op | rs | rt | Imm16 = MEM[ PC ]

inst Register Transfers

ADDU R[rd] R[rs] + R[rt]; PC PC + 4

SUBU R[rd] R[rs] R[rt]; PC PC + 4

ORi R[rt] R[rs] | zero_ext(Imm16); PC PC + 4

LOAD R[rt] MEM[ R[rs] + s ign_ext( Imm16)]; PC PC + 4

STORE MEM[ R[rs] + sign_ext(Imm16) ] R[rt]; PC PC + 4

BEQ if ( R[rs] == R[rt] ) then PC PC + 4 +sign_ext(Imm16)] || 00

else PC PC + 4


S 1: R I SS 1: R I S

M &

R (32 32 ) RS

RT W RT RD

PC E A S A 4 PC


6/73


S 2: C S 2: C DD

C ES E

C


S IS I

I

Why do we need this stuff?

PC

Instructionmemory

Instructionaddress

Instruction

a. In st ructi on memor y b. Program co unter

Add Sum

c. Adder

ALU control

RegWrite

RegistersWriteregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Writedata

ALUresult

ALU

Data

Data

Registernumbers

a. Registers b. ALU

Zero5

5

5 3

16 32Sign

extend

b. Sign-extension unit

MemRead

MemWrite

Datamemory

Writedata

Readdata

a. Data memory unit

Address


7/73


O IO I

A T :

,

Clock cycle

Stateelement

1Combinational logic

Stateelement

2


A / S V :

T : ( ) ( )

M I DM I D

RegistersRegister #

Data

Register #

Datamemory

Address

Data

Register #

PC Instruction ALUInstruction

memory

Address


8/73


C L EC L E

A

MUX

ALU

32 A

B32

Y 32

Select

M UX

32

32

A

B32

Result

OP

A L

U

32

32

A

B32

Sum

Carry

A d d er

CarryIn


S E : RS E : R

RS D F F

N W E

W E :

(0): D O (1): D O D I

Clk

Data In

Write Enable

N N

Data Out


9/73


S E : R FS E : R F

R F 32 : T 32 : A B O 32 : W

R : RA ( ) A ( ) RB ( ) B ( ) RW ( )

W ( ) W E 1

C (CLK) T CLK ONLY D , :

RA RB A B .

Clk

busW

WriteEnable

3232

busA

32busB

5 5 5RW RA RB

32 32-bitRegisters


B D

RR FF

Mux

Register 0Register 1

Register n 1

Register n

Mux

Read data 1

Read data 2

Read registernumber 1


Read registernumber 1 Read

data 1

Readdata 2


Register fileWriteregister

Writedata Write


10/73


RR FF

N :

n-to-1decoder

Register 0

Register 1

Register n 1

C

C

D

DRegister n

C

C

D

D

Register number

Write

Register data

0

1

n 1

n


S E : I MS E : I M

M ( ) O : D I O : D O

M :

A D O W E = 1: D I

C (CLK) T CLK ONLY D , :

A D O .

Clk

Data In

Write Enable

32 32DataOut

Address


11/73


C MC M

A C T = CLK Q + L D P + S + CS

(CLK Q + S D P C S ) > H T

Clk

Dont CareSetup Hold

.

.

.

.

.

.

.

.

.

.

.

.

Setup Hold


C P & C TC P & C T

C : C

:C Q + L P C L +S

Clk

.

.

.

.

.

.

.

.

.

.

.

.


12/73


CC SS E C TE C T

T :T CLK1T CLK2

C T C S CLK Q + L D + SC T CLK Q + L D + S + C S

Clk1

Clk2 Clock Skew

.

.

.

.

.

.

.

.

.

.

.

.

Clk1 Clk2


CC

S (ALU, / , .)

C ( )

I 32

E : $8, $17, $18I F :

000000 10001 10010 01000 00000 100000

op rs rt rd shamt funct

ALU'


13/73


S 3: AS 3: A D PD P

R T R D A

I F R O E O


3 : O I F 3 : O I F

T RTL F I : [PC] U :

S C : PC PC + 4 B J : PC

32

Instruction Word Address

InstructionMemory

PCClk

Next AddressLogic


14/73


3 : A & S3 : A & S

R[ ] R[ ] R[ ] E : U , , R , R , R , , ALU R W :

32

Result

ALUctr

Clk

busW

RegWr

32

32

busA

32busB

5 5 5

Rw Ra Rb

32 32-bitRegisters

Rs RtRd

AL

U




RR R T : O R T : O

Rs RtRd

32

Result

ALUctr

Clk

busW

RegWr

3232

busA

32busB

5 5 5

Rw Ra Rb

32 32-bitRegisters

AL

U

Clk

PC

Rs, Rt, Rd,Op, Func

Clk-to-Q

ALUctr

Instruction Memory Access Time

Old Value New Value

RegWr Old Value New Value

Delay through Control Logic

busA, B

Register File Access Time

Old Value New Value

busW

ALU Delay

Old Value New Value

Old Value New Value

New ValueOld Value

Register WriteOccurs Here


15/73


3 : L O I3 : L O I

R[ ] R[ ] Z E [ 16] ]11


6 bits 16 bits5 bits5 bits rd?

immediate016 1531

16 bits16 bits0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

32

Result

ALUctr

Clk

busW

RegWr

32

32

busA

32busB

5 5 5

Rw Ra Rb

32 32-bitRegisters

Rs

Z er oEx t

M ux

RtRdRegDst

Mux

3216imm16

ALUSrc

A L

U

Rt?


3 : L O3 : L O

R[ ] M [R[ ] + S E [ 16]] E : , , 1611


6 bits 16 bits5 bits5 bits rd

32

ALUctr

Clk

busW

RegWr

32

32

busA

32

busB

5 5 5

Rw Ra Rb

32 32-bitRegisters

Rs

RtRd

RegDst

Ex t en

d er

M ux

Mux

3216

imm16

ALUSrc

ExtOp

Clk

Data InWrEn

32

Adr

DataMemory

32

A L

UMemWr

M ux

W_Src

??

Rt?


16/73


3 : S O3 : S O

M [ R[ ] + S E [ 16] ] R[ ] E : , , 16



32

ALUctr

Clk

busW

RegWr

32

32

busA

32

busB

55 5

Rw Ra Rb

32 32-bitRegisters

Rs

Rt

Rt

Rd

RegDst

Ex t en d er

M ux

Mux

3216imm16

ALUSrcExtOp

Clk

Data InWrEn

32 Adr

DataMemory

MemWr

A L

U

32

M ux

W_Src


3 : T B I3 : T B I

[PC]F

E R[ ] == R[ ] C

(E ) C PC PC + 4 + ( S E ( 16) 4 )

PC PC + 4




17/73


DD B O B O

, , 16 D ( )



32

imm16

P C

Clk

0 0

A d d er

M ux

A d d er

4nPC_sel

Clk

busW

RegWr

32

busA

32

busB

5 5 5

Rw Ra Rb

32 x 32-bitRegisters

Rs Rt

E q u a

l ?

Cond

P C Ex t

Inst Address


P A T :P A T :A S CA S C DD

i m m

1 6

32

ALUctr

Clk

busW

RegWr

32

32

busA

32

bu sB

55 5

Rw Ra Rb

32 x 32-bitRegisters

Rs

Rt

Rt

RdRegDst

Ex t en

d er

M ux

3216imm16

ALUSrcExtOp

M ux

MemtoReg

Clk

Data InWrEn32 Adr

DataMemory

MemWr

AL

U

Equal

Instruction

0

1

0

1

01

< 0 : 1 5 >

Imm16RdRtRs

=

A d d er

A d d er

P C

Clk

0 0

M ux

4

nPC_sel

P C Ex t

Adr

InstMemory


18/73

11/99 Computer Organization & Architecture

B DB D

U

PC

Instructionmemory

Readaddress

Instruction

16 32

Add ALUresult

Mux

Registers

Writeregister Write

data

Readdata 1

Readdata 2

Readregister 1Readregister 2

Shiftleft 2

4

Mux

ALU operation3

RegWrite

MemRead

MemWrite

PCSrc

ALUSrc

MemtoReg

ALUresult

Zero ALU

Datamemory

Address

Writedata

Readdata M

ux

Signextend

Add


A A C PA A C P R :

T CLK ONLY D , :

A O .

Critical Path (Load Operation) =PCs Clk-to-Q +Instruction Memorys Access Time +

Register Files Access Time + ALU to Perform a 32-bit Add +Data Memory Access Time +Setup Time for Register File Write +Clock Skew

Clk

5

Rw Ra Rb

32 32-bitRegisters

Rd

AL

U

Clk

DataIn

Data Address

IdealData

Memory

Instruction

Instruction Address

IdealInstructionMemory

C l k

P C

5Rs

5Rt

16Imm

32

323232

A

B

N e x

t A d d r e s s


19/73


A A IA A I

DataOut

Clk

5

Rw Ra Rb32 32-bitRegisters

Rd

AL

U

Clk

DataIn

Data Address Ideal

DataMemory

Instruction

Instruction Address

IdealInstruction

Memory

C l k

P C

5Rs

5Rt

32

323232

A

B N e x

t A d d r e s s

ControlControl

DatapathDatapath

Control Signals Conditions


S 4: GS 4: G DD :: RTLRTL CC

ALUctrRegDst ALUSrcExtOp MemtoRegMemWr Equal

Instruction

< 0 : 1 5 >

Imm16RdRsRt

nPC_sel

Adr

InstMemory

DatapathDatapath

ControlControl

Op

Fun

RegWr


20/73


M C SM C S

R , R , R I 16

PC_ :

0 PC PC + 4;

1 PC PC + 4 +S E (I 16)

00

Addr

InstMemory

A d d er

A d d er

P C

Clk

0 0

M ux

4

nPC_sel

P C Ex t

i m m

1 6


M C SM C SE O : , ALU : 0 B; 1ALU : , ,

MemWr: write memory

MemtoReg: 1 Mem

RegDst: 0 rt; 1 rd

RegWr: write dest register

32

ALUctr

Clk

busW

RegWr

32

32

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst

Ex t en d er

M ux

3216imm16

ALUSrcExtOp

M ux

MemtoReg

Clk

Data InWrEn32 Adr

DataMemory

MemWr

AL

U

Equal

0

1

0

1

01

=


21/73


C SC S

inst Register Transfer ADD R[rd] R[rs] + R[rt]; PC PC + 4

ALUsrc = RegB, ALUctr = add, RegDst = rd, RegWr, nPC_sel = +4

SUB R[rd] R[rs] R[rt]; PC PC + 4

ALUsrc = ___, Extop = __, ALUctr = ___, RegDst = ___, RegWr(?), MemtoReg(?), MemWr(?),nPC_sel =__

ORi R[rt] R[rs] + zero_ext(Imm16); PC PC + 4


LOAD R[rt] MEM[ R[rs] + sign_ext(Imm16)]; PC PC + 4


STORE MEM[ R[rs] + sign_ext(Imm16)] R[rs]; PC PC + 4


BEQ if ( R[rs] == R[rt] ) then PC PC + sign_ext(Imm16)] || 00 else PC PC + 4



C S (A )C S (A )inst Register Transfer

ADD R[rd] R[rs] + R[rt]; PC PC + 4

ALUsrc = RegB, ALUctr = add, RegDst = rd, RegWr, nPC_sel = +4

SUB R[rd] R[rs] R[rt]; PC PC + 4

ALUsrc = RegB, ALUctr = sub, RegDst = rd, RegWr, nPC_sel = +4

ORi R[rt] R[rs] + zero_ext(Imm16); PC PC + 4

ALUsrc = Im, Extop = Z, ALUctr = or, RegDst = rt, RegWr, nPC_sel = +4

LOAD R[rt] MEM[ R[rs] + sign_ext(Imm16)]; PC PC + 4

ALUsrc = Im, Extop = Sn, ALUctr = add,MemtoReg, RegDst = rt, RegWr, nPC_sel = +4

STORE MEM[ R[rs] + sign_ext(Imm16)] R[rs]; PC PC + 4

ALUsrc = Im, Extop = Sn, ALUctr = add, MemWr, nPC_sel = +4

BEQ if ( R[rs] == R[rt] ) then PC PC + sign_ext(Imm16)] || 00 else PC PC + 4

nPC_sel = EQUAL, ALUctr = sub


22/73


S 5: L S 5: L

PC_ (OP == BEQ) EQUAL 0ALU (OP == 000000 ) B ALU (OP == 000000 )

(OP == OR ) OR (OP == BEQ)

E O (OP == OR ) M W (OP == S )M R (OP == L )

R W : ((OP == S ) (OP == BEQ)) 0 1

R D : ((OP == L ) (OP == OR )) 0 1


E : L IE : L I

32

ALUctr

Clk

busW

RegWr

32

32

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst

Ex t en

d er

M ux

3216imm16

ALUSrcExtOp

M ux

MemtoReg

Clk

Data InWrEn32 Adr

DataMemory

MemWr

AL

U

Equal

Instruction

0

1

0

1

01

< 0 : 1 5 >

Imm16RdRtRs

=

i m m

1 6

A d d er

A d d er

P C

Clk

0 0

M ux

4

nPC_sel

P C Ex t

Adr

InstMemory

sign ext

addrt+4


23/73


24/73


. ., ALU E : $1, 100($2)

35 2 1 100

16

ALU (5 8 ):000 AND001 OR010 add110 subtract111 set-on-less-than

CC


M 3 ALU

00 = , 01 = ,11 =

D ( ):

ALUOpcomputed from instruction type

CC

ALUOp Funct field OperationALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0

0 0 X X X X X X 010X 1 X X X X X X 1101 X X X 0 0 0 0 0101 X X X 0 0 1 0 1101 X X X 0 1 0 0 0001 X X X 0 1 0 1 0011 X X X 1 0 1 0 111


25/73


CC

Instruction RegDst ALUSrcMemto-

RegReg

riteMemRead

Memrite Branch ALUOp1 ALUp0

R-format 1 0 0 1 0 0 0 1 0lw 0 1 1 1 1 0 0 0 0sw X 1 X 0 0 1 0 0 0beq X 0 X 0 0 0 1 0 1

PC

Instructionmemory

Readaddress

Instruction[310]

Instruction [2016]

Instruction [2521]

Add

Instruction [50]

MemtoReg ALUOpMemWrite

RegWrite

MemReadBranchRegDst

ALUSrc

Instruction [3126]

4

16 32Instruction [150]

0

0Mux

0

1

Control

Add ALUresult

Mux

0

1


Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Shiftleft 2

Mux

1

ALUresult

Zero

Datamemory

Writedata

Readdata

Mux

1

Instruction [1511]

ALUcontrol

ALU Address


CC

S ( )

Operation2

Operation1

Operation0

Operation

ALUOp1

F3

F2

F1

F0

F (50)

ALUOp0

ALUOp

ALU control block

R-format Iw sw beq

Op0

Op1Op2Op3

Op4Op5

Inputs

Outputs

RegDst

ALUSrc

MemtoReg

RegWrite

MemRead

MemWrite

Branch

ALUOp1

ALUOpO


26/73


A

, ALU

C

O S C SO S C S

We are ignoring some details like setup and hold times

Clock cycle

Stateelement

1Combinational logic

Stateelement

2


S C IS C I

C : (2 ), ALU (2 ), (1 )

MemtoReg

MemRead

MemWrite

ALUOp

ALUSrc

RegDst

PC

Instructionmemory

Readaddress

Instruction[310]

Instruction [20 16]

Instruction [25 21]

Add

Instruction [50 ]

RegWrite

4

16 32Instruction [150 ]

0Registers

Writeregister Writedata

Writedata

Readdata 1

Readdata 2

Readregister 1Readregister 2

Signextend

ALUresult

Zero

Datamemory

Address Readdata M

ux

1

0

Mux

1

0

Mux

1

0

Mux

1

Instruction [15 11]

ALUcontrol

Shiftleft 2

PCSrc

ALU

Add ALUresult


27/73


S C P : ?

O S : :

PC

Memory

Address

Instructionor data

Data

Instructionregister

RegistersRegister #

Data

Register #

Register #

ALU

Memorydata

register

A

B

ALUOut


ALU PC M

O

. ., ALU ?

M AM A


28/73


F : (

) (

)

W M ( )

RR ::

Next-statefunction

Current state

Clock

Outputfunction

Nextstate

Outputs

Inputs


RR ::

E :

A friend would like you to build an electronic eye for use asa fake security device. The device consists of three lights linedup in a row, controlled by the outputs Left, Middle, and Right,

which, if asserted, indicate that a light should be on. Only onelight is on at a time, and the light moves from left to rightand then from right to left, thus scaring away thieves whobelieve that the device is monitoring their activity. Draw the

graphical representation for the finite state machine used to specify the electronic eye. Note that the rate of the eyesmovement will be controlled by the clock speed (which should not be too great) and that there are essentially no inputs.


29/73


B ,

A ( )

M AM A

Shiftleft 2

PC

Memory

MemData

Writedata

Mux

0

1


Writedata

Readdata1

Readdata2

Readregister 1

Readregister 2

Mux

0

1

Mux

0

1

4

Instruction[150]

Signextend

3216

Instruction[2521]

Instruction[2016]

Instruction[150]

Instruction

register

1 M

ux

0

32

Mux

ALUresult

ALUZero

Memorydata

register

Instruction[1511]

A

B

ALUOut

0

1

Address


I F

I D R F

E , M A C , BC

M A R

W

!

F E SF E S


30/73


U PC IR .

I PC 4 PC. C RTL "R TL "

IR = Memory[PC];PC = PC + 4;

T !Can we figure out the values of the control signals?What is the advantage of updating the PC now?

S 1:S 1: I FI F


R C

RTL:

A = Reg[IR[25-21]];B = Reg[IR[20-16]];ALUOut = PC + (sign-extend(IR[15-0])


31/73


ALU ,

M R :ALUOut = A + sign-extend(IR[15-0]);

R :ALUOut = A op B;

B :if (A==B) PC = ALUOut;

S 3 (S 3 ( ))


L

MDR = Memory[ALUOut];or

Memory[ALUOut] = B;

R

Reg[IR[15-11]] = ALUOut;

.

S 4 (RS 4 (R ))


32/73


Reg[IR[20-16]]= MDR;

What about all the other instructions?


SS ::

Step nameAction for R-type

instructionsAction for memory-reference

instructionsAction forbranches

Action for jumps

Instruction fetch IR = Memory[PC]PC = PC + 4

Instruction A = Reg [IR[25-21]]

decode/register fetch B = Reg [IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0])


33/73


H ?

lw $t2, 0($t3)lw $t3, 4($t3)beq $t2, $t3, Label #assume notadd $t5, $t2, $t3sw $t5, 8($t3)

Label: ...

W 8 ? I $t2 $t3

?

S QS Q


V :

U ,

I

I CI C


34/73

H

?

G SG S FSMFSM

PCWritePCSource = 10

ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01PCWriteCond

PCSource = 01

ALUSrcA =1 ALUSrcB = 00

ALUOp= 10

RegDst = 1RegWrite

MemtoReg = 0

MemWriteIorD = 1

MemRead

IorD = 1

ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00

RegDst=0RegWrite

MemtoReg=1

ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00

MemRead ALUSrcA = 0

IorD = 0IRWrite

ALUSrcB = 01 ALUOp = 00

PCWritePCSource = 00

Instruction fetch Instruction decode/register fetch

Jumpcompletion

BranchcompletionExecution

Memory addresscomputation

Memoryaccess

Memoryaccess R-type completion

Write-back step

( O p = ' L W

' ) o r ( O p =

' S W ' ) ( O p

= R - t y p

e )

( O p

= ' B E

Q ' )

( O p =

' J ' )

( O p = ' S W ' )

( O p =

' L W ' )

4

01

9862

753

Start


I :

F S M CF S M C

PCWrite

PCWriteCondIorD

MemtoReg

PCSource AL UO p

AL US rcB

AL US rcA

RegWrite

RegDst

NS 3NS 2NS 1NS 0

O p 5

O p 4

O p 3

O p 2

O p 1

O p 0

S 3

S 2

S 1

S 0

State register

IRWrite

MemRead

MemWrite

Instruction registeropcode field

Outputs

Control logic

Inputs


35/73


PLA IPLA I

I I ?Op5

Op4

Op3

Op2

Op1

Op0

S3

S2

S1

S0

IorD

IRWrite

MemReadMemWrite

PCWritePCWriteCond

MemtoReg

PCSource1

ALUOp1

ALUSrcB0 ALUSrcARegWriteRegDstNS3NS2NS1NS0

ALUSrcB1 ALUOp0

PCSource0


ROM = "R O M "

A ROM , 2 ROM. .

" ", " "

ROMROM II

m n

0 0 0 0 0 1 10 0 1 1 1 0 00 1 0 1 1 0 00 1 1 1 0 0 01 0 0 0 0 0 01 0 1 0 0 0 11 1 0 0 1 1 01 1 1 0 1 1 1


36/73


H ?6 , 4 = 10 ( . ., 210 = 1024 )

H ?16 , 4 = 20

ROM 210 20 = 20K ( )

R , ,

. .,

ROMROM II


B 4 16 , 24 16 ROM

10 4 , 210 4 ROM

T : 4.3K ROM

PLA

'

S (# # ) + (# #)

F = (10 17)+(20 17) = 460 PLA

PLA ROM ( )

ROM ROM PLAPLA


37/73


C : " " +1

A I SA I S

AddrCtl

Outputs

PLA or ROM

State

Address select logic

O p [

5 0 ]

Adder


1

Control unit

Input

PCWritePCWriteCondIorD

MemtoRegPCSource

ALUOp ALUSrcB ALUSrcARegWriteRegDst

IRWrite

MemReadMemWrite

BWrite


DDDispatch ROM 1 Dispatch ROM 2

Op Opcode name Value Op Opcode name Value000000 R-format 0110 100011 lw 0011000010 jmp 1001 101011 sw 0101000100 beq 1000100011 lw 0010101011 sw 0010

State number Address-control action Value of AddrCtl0 Use incremented state 31 Use dispatch ROM 1 12 Use dispatch ROM 2 23 Use incremented state 34 Replace state number by 0 05 Replace state number by 0 06 Use incremented state 37 Replace state number by 0 08 Replace state number by 0 09 Replace state number by 0 0

State

O p

Adder

1

PLA or ROM

Mux3 2 1 0

Dispatch ROM 1Dispatch ROM 2

0

AddrCtl




38/73


MM

?

PCWritePCWriteCondIorD

MemtoRegPCSource

ALUOp ALUSrcB ALUSrcARegWrite

AddrCtl

Outputs

Microcode memory

IRWrite

MemReadMemWrite

RegDst

Control unit

Input

Microprogram counter


O p [

5 0 ]

Adder

1

Datapath


BWrite


M (M )M (M )

C D M C

Microprogramming:

-- A Particular Strategy for Implementing the Control Unit of aprocessor by "programming" at the level of register transferoperations

Microarchitecture:

-- Logical structure and functional capabilities of the hardware asseen by the microprogrammer

Historical Note:

IBM 360 Series first to distinguish between architecture & organizationSame instruction set across wide range of implementations, each withdifferent cost/performance


39/73


MM II

MainMemory

executionunit

controlmemory

CPU

ADDSUB

AND

DATA

.

.

.

User programplus Data

this can change!

AND microsequence

e.g., Fetch

Calc Operand AddrFetch Operand(s)CalculateSave Answer(s)

one of these ismapped into oneof these


A , , , .

MM

LabelALU

control SRC1 SRC2Registercontrol Memory

PCWritecontrol Sequencing

Fetch Add PC 4 Read PC ALU Seq Add PC Extshft Read Dispatch 1

Mem1 Add A Extend Dispatch 2LW2 Read ALU Seq

Write MDR FetchSW2 Write ALU FetchRformat1 Func code A B Seq

Write ALU FetchBEQ1 Subt A B ALUOut-cond FetchJUMP1 Jump address Fetch


40/73

MM Field name Value Signals active Comment

Add ALUOp = 00 Cause the ALU to add.

ALU control Subt ALUOp = 01 Cause the ALU to subtract; this implements the compare for branches.

Func code ALUOp = 10 Use the inst ruct ion' s funct ion code to determine ALU control .SRC1 PC ALUSrcA = 0 Use the PC as the first ALU input.

A ALUSrcA = 1 Register A is the first ALU input.B ALUSrcB = 00 Register B is the second ALU input.

SRC2 4 ALUSrcB = 01 Use 4 as the second ALU input.Ex te nd AL USr cB = 10 Us e o utp ut of th e s ig n e xte ns io n u nit as th e s ec on d AL U in pu t.Ex ts hf t AL USr cB = 11 Us e th e o ut pu t o f th e s hift -b y-t wo un it as th e s ec on d AL U in pu t.Read Read two registers using the rs and rt fields of the IR as the register

numbers and putting the data into registers A and B.Wr ite AL U Re gWr ite , Wr ite a re gis te r u sin g th e r d fi eld of th e IR as th e re gis te r n umb er an d

Register RegDst = 1, the contents of the ALUOut as the data.control MemtoReg = 0

Wri te MDR RegWrite, Wri te a register using the r t f ie ld of the IR as the reg is te r number andRe gDs t = 0, th e c on te nt s o f th e MDR as the da ta .MemtoReg = 1

Re ad PC Me mR ead , Re ad me mo ry u si ng th e PC a s a dd re ss ; wr ite re su lt in to I R ( an dlorD = 0 the MDR).

Memory Read ALU MemRead, Read memory using the ALUOut as address; write result into MDR.lorD = 1

Wr ite AL U Me mWrit e, Wr ite me mo ry us in g th e AL UO ut as ad dr es s, co nte nt s o f B as th elorD = 1 data.

ALU PCSource = 00 Write the output of the ALU into the PC.PCWrite

PC write control ALUOut-cond PCSource = 01, If the Zero output of the ALU is active, write the PC with the contentsPCWrit eC ond o f t he re gis te r AL UO ut.

jump address PCSource = 10, Write the PC with the jump address from the instruction.PCWrite

Seq AddrCtl = 11 Choose the next microinstruction sequentially.Sequencing Fetch AddrCtl = 00 Go to the first microinstruction to begin a new instruction.

Dispatch 1 AddrCtl = 01 Dispatch using the ROM 1.Dispatch 2 AddrCtl = 10 Dispatch using the ROM 2.


H . MH . M

NOTE: previous organization is not TRUE horizontalmicroprogramming; register decoders give flavor of encodedmicrooperations

Most microprogramming-based controllers vary between:

horizontal organization (1 control bit per control point)

vertical organization (fields encoded in the control memory andmust be decoded to control something)

Horizontal

+ more control over the potentialparallelism of operations in thedatapath

- uses up lots of control store

Vertical

+ easier to program, not verydifferent from programminga RISC machine in assemblylanguage

- extra level of decoding mayslow the machine down


41/73


N : 1 , ( ) V 780 400K !

L :

,

H CISC: T U ROM ( RAM) I

MM .. M EM E


D M SD M S

S

G ( . ):

P ( . ., ALU &ALU )

C ,

U

T ,


42/73


MM :: TT

D

S A : E

D

I ( ROM) A E

C

C

I D , SLOWER :

C ROM RAM

N


EE

E

&

A

user program

normal control flow:sequential, jumps, branches, calls, returns

SystemExceptionHandlerException:

return fromexception


43/73


I E ? I E ?

MIPS .

W

.

T ?


T T ET T E

I

T

( ) ( ) ( )


44/73


MIPSMIPS ::

, ;

.

I/O E II OS I EA I EU I E

H E E I


A E HA E H

T A : I V PC MEM[ IV_ + 00] 370, 68000, V , 80 86, . . .

RISC H T PC IT_ + 0000 S , PA, M88K, . . .

MIPS A : PC EXC_ A

RESET TLB

iv_basecause

handlercode

iv_basecause

handler entry code


45/73


S SS S

P V , 68 , 80 86

S MIPS EPC, B V , S , C

S R M88 S


A A MIPSMIPS ISA E ?ISA E ?

EPC 32 ( 14 0).

C . I MIPS 32 ,

. A 5 2 :

=0 =1 ( 13 0). B VA

( 8 0) S ( 12 0) C EPC , C , B VA , S B PC,

01000000 00000000 00000000 01000000 (8000 0080 ) M PC PC + 4, EPC

( ); PC PC 4


46/73


B P : / B P : /

B ( / )

.

E

O/S


P IP I

P A O

S P IBM D , , ... MIPS

I

P , , .

M


47/73


H C D E H C D E FSDFSD

U I 1 .

W , , 0 (R ), , , 12.

S 1.

A C 4 ALU , O ALU.

T

N : C .

C


M C SM C SIR


48/73


SS

S &

C M

E

N PC

F CP , :

N :T AND


S : M S : M

I I

I

I RAM ROM

I

T

?


49/73


T B PT B P

Initialrepresentation

Finite statediagram Microprogram

Sequencingcontrol

Explicit nextstate function

Microprogram counter+ dispatch ROMS

Logicrepresentation

Logicequations

Truthtables

Implementationtechnique

Programmablelogic array

Read onlymemory



50/73


I O

Vdd

OutIn

Symbol Circuit

B C :B C : CMOSCMOS II

OutIn

Vdd Vdd Vdd

Out

Open

Discharge

Open

Charge

Vin

Vout

Vdd

Vdd

PMOS

NMOS


B C :B C : CMOSCMOS L GL GNAND Gate NOR Gate

Vdd

A

B

Out

Vdd A

B

Out

Out A B

A

B

Out A B Out

0 0 10 1 11 0 11 1 0

A B Out0 0 10 1 01 0 01 1 0


51/73


G CG C

I PMOS :I OK PMOS NOR

NOR H > L L > HI NMOS :

I OK NMOS NAND NAND L > H H > L

Vdd

A

B

Out

Vdd

A

B

Out

NAND Gate NOR Gate


I RI R

0 > 1, 1 > 0 NOT O 1 > 0: V (5 ) 0

1 > 0, 0 > 1 NOT O 0 > 1: 0 V (5 )

OutIn

Time

Voltage

1 => Vdd

Vin Vout

0 => GND


52/73


F T MF T M

< > E C T C < > C (C) L < > F < > C F

(C )S P < > S T (G)T C / G

Reservoir

Level (V) = Vdd

Tank(Cout)

Bottomless Sea

Sea Level(GND)

SW2SW1

Vdd

SW1

SW2Cout

Tank Level (Vout)

Vout


S CS C

T P D = S = 1 + 2C C1 :

C I

Vdd

Cout

Vout

Vdd

C1

V1 Vin

V1 Vin Vout

Time

G1 G2 G1 G2

Voltage Vdd

Vin

GND

V1 Vout

Vdd/2d1 d2


53/73


R : C DR : C D

S D ( > 2) ! = D ( > 3)

D (V > V2) = D (V > V1) + D (V1 > V2)

D (V > V3) = D (V > V1) + D (V1 > V3)C P = T N C1 = C + C G 2 + C G 3

Vdd

V2

Vdd V1 Vin V2

C1

V1 VinG1 G2

Vdd

V3G3

V3


R : G C/L C D MR : G C/L C D M

C C ( ) : ( > )

, , VHDL

THL(A, ) = F I D + L

L

Cout

Vout A B

X

.

.

.

CombinationalLogic Cell

Cout

Delay Va -> Vout

X X

X X

X

X

Ccritical

Internal

Delay

delay per unit load


54/73


C GC G

I F :

F (H >L, L >H, H >Z, L >Z ... .) I ( ) L ( / F)

E : 2 NAND G

Out A B

For A and B: Input Load (I.L.) = 61 fF

For either A -> Out or B -> Out:Tlh = 0.5ns Tlhf = 0.0021ns / fFThl = 0.1ns Thlf = 0.0020ns / fF

Delay A -> OutOut: Low -> High

Cout

0.5ns

Slope =0.0021ns / fF


A S E : 2 1A S E : 2 1 MM

I L (I.L.)A, B: I.L. (NAND) = 61 FS: I.L. (INV) + I.L. (NAND) = 50 F + 61 F = 111 F

L D D (L.D.D.): S G 3TAY = 0.0021 / F TAY = 0.0020 / FTBY = 0.0021 / F TBY = 0.0020 / FTSY = 0.0021 / F TSY = 0.0020 / F

Y = (A and !S)or (B and S)

A

B

S

Gate 3

Gate 2

Gate 1Wire 1

Wire2

Wire0

A

B Y

S

2 x1 M

ux


55/73


2 12 1 MM : I D C: I D C

I D (I.D.):A Y: I.D. G1 + (W 1 C + G3 I C) * L.D.D G1 + I.D. G3B Y: I.D. G2 + (W 2 C + G3 I C) * L.D.D. G2 + I.D. G3S Y (W C ): I.D. I + (W 0 C + G1 I C) * L.D.D. I +

I D A Y

1 C :A W 1 C C .

Y = (A and !S) or (A and S)

A

B

S

Gate 3

Gate 2

Gate 1Wire 1

Wire2

Wire0


2 12 1 MM : I D C ( ): I D C ( )

I D (I.D.):A Y: I.D. G1 + (W 1 C + G3 I C) * L.D.D G1 + I.D. G3B Y: I.D. G2 + (W 2 C + G3 I C) * L.D.D. G2 + I.D. G3S Y (W C ): I.D. I + (W 0 C + G1 I C) * L.D.D. I +

I D A YS E :

TAY = TP G1 + (2.0 * 61 F) * TP G1 + TP G3= 0.1 + 122 F * 0.0020 / F + 0.5 = 0.844

Y = (A and !S) or (B and S)

A

B

S

Gate 3

Gate 2

Gate 1Wire 1

Wire2

Wire0


56/73


A : 2 1A : 2 1 MM

I L : A = 61 F, B = 61 F, S = 111 FL D D :

TAY = 0.0021 / F TAY = 0.0020 / FTBY = 0.0021 / F TBY = 0.0020 / FTSY = 0.0021 / F TSY = 0.0020 / F

I D :TAY = TP G1 + (2.0 * 61 F) * TP G1 + TP G3

= 0.1 + 122 F * 0.0020 / F + 0.5 = 0.844F E : TAY , TBY , TSY , TSY

A

B Y

S

2 x1 M

ux

A

B

S

Gate 3

Gate 2

Gate 1 Y


CS152 L ECS152 L ENAND2, NAND3, NAND 4NOR2, NOR3, NOR4IN 1 ( )IN 4 (

)

D

OR2NOR2

P R: S 1GND: S 0

M


57/73


S ES E T M T M

S T : I BEFORE H T : I REMAIN

C Q :O S , :

I C Q L C Q

T :1 S , 0.5 H

D QD Dont Care Dont Care

Clk

UnknownQ

Setup Hold

Clock-to-Q


C MC M

A T :

I A MUST

Clk

.

.

.

.

.

.

.

.

.

.

.

.Combination Logic


58/73


T R C TT R C T

R

Review Karnaugh maps for prereq quiz! Use esoteric/dynamic timing methods

Pay attention to loading

One gate driving many gates is a bad idea

Avoid using a small gate to drive a long wire

Use multiple stages to drive large load

A B

CD

A B

CD

INV4x

INV4x

Clarge


H A H T ?H A H T ?

H :I NOT

T H FF


59/73


CC SS E H TE H T

T :T CLK2T CLK1

FF2 FF1 (CLK Q + S D P C S ) > H T

Clk1

Clk2 Clock Skew

Clk2 Clk1

.

.

.

.

.

.

.

.

.

.

.

.Combination Logic


SS

T

A : L D RP T T

K (KISS )

CMOS CMOS D M G C

D = I D + (L D D O L )C M T C

S A SAME

C T CLK Q + L D P + S + C S(CLK Q + S D P C S ) > H T


60/73


T G M IT G M I

A C B S A :C M L C , I VLSI S ,A W P C , O 1980.

A G LSI C D BL G & D D , T D A VLSI C , A W P C , 1985.

M . D DEC A .

A B H D IC :D H & H J , A D DI C , M G H B C , 1983.

N B : J R , D I C : A D P ,P H P , 1998.


S 8, 1999J K ( . . . / )

: :// . . . / 152/

CS152CS152C A EC A E

L 4L 4

C DC D


61/73


Year

P e r f o r m a n c e

0.1

1

10

100

1000

1965 1970 1975 1980 1985 1990 1995 2000

Microprocessors

Minicomputers

Mainframes

Supercomputers

R : P T TR : P T T

T P : 1.2 1.2 1.2 = 1.7 / F S : 10% / . => S 1.2 / . D : 1.2 / . D A : 1.2 / .

RISC ISA : S => ( 3 ) A B


R : G C/L C D MR : G C/L C D M

C C ( ) : ( > )

, , VHDL

THL(A, ) = F I D + L

L

Cout

Vout A B

X

.

.

.

CombinationalLogic Cell

Cout

Delay Va -> Vout

X X

X X

X

X

Ccritical

Internal

Delay

delay per unit load


62/73


R : C GR : C G

I F :

F (H >L, L >H, H >Z, L >Z ... .) I ( ) L ( / F)

E : 2 NAND G

Out A B

For A and B: Input Load (I.L.) = 61 fF

For either A -> Out or B -> Out:Tlh = 0.5ns Tlhf = 0.0021ns / fFThl = 0.1ns Thlf = 0.0020ns / fF

Delay A -> OutOut: Low -> High

Cout

0.5ns

Slope =0.0021ns / fF


R : T , L D DR : T , L D D

CMOS T T C : PMOS NMOS CMOS CMOS

D M G C D = I D + (L D D O L )

C M T C S

A SAME C T = CLK Q + L D P + S + CS

(CLK Q + S D P C S ) > H T


63/73


O : C DO : C D

R L L (2 ) C P (18) A M (3 ) D (27 ) B (5 ) M D (15 ) O (10 )


Defects_per_unit_area * Die_Area

}

I C CI C C

Die Cost is goes roughly with the cube of the area.

{ 1+

Die cost = Wafer costDies per Wafer * Die yield

Dies per wafer = * ( Wafer_diam / 2) 2 * Wafer_diam Test dies Wafer AreaDie Area 2 * Die Area Die Area

Die Yield = Wafer yield


64/73


D D

Raw Dice Per Wafer wafer diameter die area (mm 2 )

100 144 196 256 324 400 6/15cm 139 90 62 44 32 238/20cm 265 177 124 90 68 5210/25cm 431 290 206 153 116 90

die yield 23% 19% 16% 12% 11% 10%typical CMOS process: =2, wafer yield=90%, defect density=2/cm2, 4 test sites/wafer

Good Dice Per Wafer (Before Testing!)

6/15cm 31 16 9 5 3 28/20cm 59 32 19 11 7 510/25cm 96 53 32 20 13 9typical cost of an 8, 4 metal layers, 0.5um CMOS wafer: ~$2000


R ER E

386D 2 0.90 $900 1.0 43 360 71% $4486D 2 3 0.80 $1200 1.0 81 181 54% $12P PC 601 4 0.80 $1700 1.3 121 115 28% $53HP PA 7100 3 0 .80 $1300 1.0 196 66 27% $73DEC A 3 0.70 $1500 1.2 234 53 19% $149S SPARC 3 0.70 $1700 1.6 256 48 13% $272P 3 0.80 $1500 1.5 296 40 9% $417

F "E IC M C , L G , , A 2, 1993, . 15


65/73


IC = D + T + P F

P C : ,

O CO C

Chip Die Package Test & Total cost pins type cost Assembly

386DX $4 132 QFP $1 $4 $9486DX2 $12 168 PGA $11 $12 $35PowerPC 601 $53 304 QFP $3 $21 $77HP PA 7100 $73 504 PGA $35 $16 $124DEC Alpha $149 431 PGA $30 $23 $202SuperSPARC $272 293 PGA $20 $34 $326Pentium $417 273 PGA $19 $37 $473


S C :S C :19951995 96 96

S S % C S , 1%

P , 2%C , , 1%

(S ) (4%)M P 6%

DRAM (64MB) 36% 14%

I/O 3%P C

1%(S ) (60%)

I/O D K , 1%M 22%

H (1 GB) 7%T

(DAT) 6%(S ) (36%)


66/73


ComponentCost

componentcost

Direct Costs

componentcost

direct costs

Gross Margin

componentcost

direct costs

gross margin

AverageDiscount

list price

avg. selling price

Input:chips,displays, ...

Making it:labor, scrap,returns, ...

Overhead:R&D, rent,marketing,profits, ...

Commision:channelprofit, volumediscounts,

+33%

+25100%

+5080%

(2531%)

(3345%)

(810%)

(3314%)

(WSPC)Q: What % of company incomeon Research and Development (R&D)?

C . PC . P


C SC S

I D E ($$$) !


67/73


CC 44

AA


32

32

32

operation

result

a

b

ALU

AA

' : P ( , , ) A :

I S AA L M L

' : I A


68/73




69/73




70/73


C FC F


' MIPS S :

:lw, sw :add, sub, and, or, slt :beq, j

G I :

(PC)

A AL ? ? ? ?

T PT P :: DD && CC


71/73


. C C

?

cycle timerising edge

falling edge

S ES E


T

AA


72/73


O ( ' )

C ( ) L : , F :

( )

"logically true", could mean electrically low

A clocking methodology defines when signals can be read and written wouldn't want to read a signal at the same time it was being written

L FL F


T : (D) (C) & D

T : (Q) '

DD

Q

C

D

_ Q

D

C

Q


73/73


DD

O

QQ

_ Q

Q

_ Q

Dlatch

D

C

Dlatch

DD

C

C

D

C

Q

ceng 331 course slides chapter 5

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