ceng 342 – digital systems

CENG 342 – Digital SystemsAlgorithmic State Machine with Datapath (ASMD)

Larry Pyeatt

SDSM&T

Finite State Machine – ReviewAny Finite state machine with two inputs, two Mealy outputs, two Moore outputs, and upto four states can be expressed graphically as this:

Combinational

Logic Circuit

(Next State)

Memory

Devices

(Flip−Flops)

Combinational

Logic Circuit

(Moore Outputs)

Combinational

Logic Circuit

(Mealy Outputs)

Inputs

Moore Outputs

Mealy Outputs

FSM – Review

Finite state machines may be described in more detail using a state diagram.The state diagram is a graph, which means that it is composed of

a set of nodes and

a set of arcs.

Each node has a set of incoming arcs and a set of outgoing arcs.

Moore outputs are associated with nodes.

Mealy outputs are associated with arcs.

The following diagram shows a single node with one incoming arc and two outgoing arcs.

To other stateTo other state

MO← value

MO: Moore outputME: Mealy output

...

State_Name

Logical expression {/ ME← value {, . . . }}



FSM – Review

To other stateTo other state

MO← value

MO: Moore outputME: Mealy output

...

State_Name




Each node has a list of Moore outputs, which are asserted whenever that state is thecurrent state.

Each arc has a Logical Expression, which specifies the condition under which that arcis taken, and a set of Mealy Outputs, which are asserted whenever that conditionbecomes true in the state represented by the source node.

We often define “default” values for both Moore and Mealy outputs. If a value isnot explicitly listed, then the default value is assumed.

FSM – Review

Example from “The Designer’s Guide to VHDL.” – An FSM with both Mealy and Mooreoutputs:

S1

y1 ← 1

S2

a

ab/y0 ← 1

S0

a

a

FSM – VHDL Implementation

A methodical approach makes it much easier and less error-prone.

Use the VHDL enumerated data type to represent the states.Use three section coding method:

1 A process which updates the current state.2 A process or concurrent statement(s) to generate the next state.3 A process or concurrent statement(s) to generate the outputs.


1 library ieee;2 use ieee.std_logic_1164.all;34 entity fsm_eg is5 port(6 clk, reset: in std_logic;7 a, b : in std_logic;8 y0, y1 : out std_logic;9 );

10 end fsm_eg;1112 architecture mult_seg_arch of fsm_eg is13 type eg_state_type is (s0, s1, s2);14 signal state_reg, state_next : eg_state_type;15 begin16 -- state update17 process(clk,reset)18 begin19 if reset = ’1’ then -- asynchronous reset20 state_reg <= s0;21 elsif rising_edge(clk) then22 state_reg <= state_next;23 end if;24 end process;

S1

y1 ← 1

S2

a

ab/y0 ← 1

S0

a

a

Combinational

Logic Circuit

(Next State)

Memory

Devices

(Flip−Flops)

Combinational

Logic Circuit

(Moore Outputs)

Combinational

Logic Circuit

(Mealy Outputs)

Inputs

Moore Outputs

Mealy Outputs


26 -- next state logic27 process (state_reg, a, b)28 begin29 case state_reg is30 when s0 =>31 if a = ’1’ then32 if b = ’1’ then33 state_next <= s2;34 else35 state_next <= s1;36 end if;37 else38 state_next <= s0;39 end if;40 when s1 =>41 if a = ’1’ then42 state_next <= s0;43 else44 state_next <= s1;45 end if;46 when s2 =>47 state_next <= s0;48 end case;49 end process;

S1

y1 ← 1

S2

a

ab/y0 ← 1

S0

a

a

Combinational

Logic Circuit

(Next State)

Memory

Devices

(Flip−Flops)

Combinational

Logic Circuit

(Moore Outputs)

Combinational

Logic Circuit

(Mealy Outputs)

Inputs

Moore Outputs

Mealy Outputs


51 -- Moore output logic52 process(state_reg)53 begin54 case state_reg is55 when s0 | s2 =>56 y1 <= ’0’;57 when s1 =>58 y1 <= ’1’;59 end case;60 end process;6162 -- Mealy output logic63 process(state_reg,a,b)64 begin65 case state_reg is66 when s0 =>67 if a = ’1’ and b = ’1’ then68 y0 <= ’1’;69 else70 y0 <= ’0’;71 end if;72 when s1 | s2 =>73 y0 <= ’0’;74 end case;75 end process76 end mult_seg_arch;

S1

y1 ← 1

S2

a

ab/y0 ← 1

S0

a

a

Combinational

Logic Circuit

(Next State)

Memory

Devices

(Flip−Flops)

Combinational

Logic Circuit

(Moore Outputs)

Combinational

Logic Circuit

(Mealy Outputs)

Inputs

Moore Outputs

Mealy Outputs


Much simpler implementation of output logic:

78 -- Moore output logic79 y1 <= ’1’ when state_reg = s1 else ’0’;808182 -- Mealy output logic83 y0 <= ’1’ when (state_reg = s084 and a =’1’85 and b = ’1’) else ’0’;

S1

y1 ← 1

S2

a

ab/y0 ← 1

S0

a

a

Combinational

Logic Circuit

(Next State)

Memory

Devices

(Flip−Flops)

Combinational

Logic Circuit

(Moore Outputs)

Combinational

Logic Circuit

(Mealy Outputs)

Inputs

Moore Outputs

Mealy Outputs

Example – Edge DetectorMoore Mealy

The zero and one states

indicate that the input

signal has been 0 or 1

For a while

level

ZERO

level

ZERO

EDGE

tick← 1

level

ONE

level

ONE

levellevel

level

level

level/tick← 1 level

FSMD

Finite state machine with datapath

Uses an FSM to drive another sequential circuit

Data

Register(s)

Routing

Network

Functional

Units

Routing

Network

Data

Input Output

Data

Next State

Logic

Output

LogicRegister

StateStatus

OutputCommand

Internal Status Control Signals

Register Transfer Level

The FSMD is used to implement systems that are described at the Register TransferLevel (RTL).

An RT operation specifies data manipulation and transfer for a single destinationregister. Example:

rdest ← f (rsrc1 , rsrc2 , . . . , rsrcn )

Elementary operations are called microoperations. Some examples are:load: rx ← ry,

count: rx ← rx + C where C is a constant,

shift: rx ← lsl(rx, amt),

bitwise “or”: rx ← rx ∨ ry,

etc.

There is a fairly well established syntax for RTL operations.

You can extend the syntax, if you explain what your operations mean, and beconsistent.

Common RTL Syntax

The← symbol indicates data transfer into a register.

R1← R2

Brackets [] specify an operation on memory. The memory address goes inside thebrackets, and the memory device name precedes the brackets.

R0← M[AR]

M[AR]← R5

A comma is used to separate parallel operations.

rx ← ry, ra ← rb + rc

A colon specifies a condition under which the transfer occurs.

K1 : rx ← ry, ra ← rb + rc

ab : rx ← rx + 1

RTLIt is assumed that all RT operations are synchronized by a shared clock.The results from the operation are not stored until the next rising (or falling, if youdesign it that way) edge of the clock.The following figures show two ways to achieve the same results. The figure on theleft takes one clock cycle to get the result. The one on the right takes two clock cycles,but is more flexible. It uses a “routing network” shown previously.Can you design a circuit that can perform the unified a− b + 1 operation in one clockcycle, but is also capable of performing either the a− b or the a + 1 operationindividually?

d q

clk

d q

clk

+1

−

d q

clk

d q

clk

+1−

a← a− b + 1

a

b

a

b

a← a− ba← a + 1

Algorithmic State Machine

For designing the state machine, it is often easier to use an Algorithmic StateMachine (ASM) chart.The ASM chart is a network of ASM blocks.

State blocks represent the states and Moore outputs.

Decision blocks represent condition tests.

Conditional output blocks represent Mealy outputs.

ConditionExpressionMoore

Outputs

MealyOutputs

Conditional Output Block

Decision Block

State Block 0 1State


ASM with datapath

The clock is assumed to drive state transitions.

The ASM chart specifies operations that must be implemented by the datapath.

8

d q

clk

d q

clk

s0

s1

s2

s3

r1← 8

r1← r1 + r2

r1← r1

r1← r1<<2

r1

r2

<<2

+


It is common to use one or more multiplexers as a routing network to provide input tothe registers and/or the functional units.

The following ASM chart is equivalent to one circle in the state diagram. The dashedlines show an ASM block. The clock causes transition from one ASM block to the next.

Some decision nodes can be handled completely within the datapath.

−1

+

s0

a > b

r2← r2 + b r2← r2 + a

F T

r1

r2ab

a > b

en

en

ControlSignals

d q

d q

r1← r1− 1

ASMD Timing

The destination register(s) get updated when exiting the current ASMD block, but notwithin the block.

Each ASMD block represents one clock cycle.

There can be errors when that fact is forgotten.

s1s1

r = 0TF

r← r− 1 r← r_nextr_next := r− 1

r_next← r− 1

r_next = 0TF

r← r_next

TF

s1

The := symbol canbe used to specifya local signal that

is assigned immediatly

r_next = 0

State Diagram and ASM Equivalence

a = 1

b = 1

y0← 1

s2

a = 1

S1

y1 ← 1

S2

F

T

TF

y1← 1

s1

FT

a

ab/y0 ← 1

S0

a

a

s0

Calculating the ith Number in the Fibonacci Sequence

The Fibonacci sequence is defined as:

fib(i) =

0 if i = 0,

1 if i = 1,

fib(i− 1) + fib(i− 2) otherwise.

n← F . Load the input value into nt0← 0 . Initialize t0t1← 1 . Initialize t1repeat

if n = 0 then . Original input is zerot1← 0 . Initialize t1

else if n 6= 1 then . Skip update on last time through loopn← n− 1 . Decrement countert3← t1 + t0 . Calculate new value for t1t0← t1 . Copy t1 to t0t1← t3 . Assign value to t1

end ifResult← t1

until n < 2 . Go through the loop n times

ASM Chart

Temporary variables (registers): t0, t1

Index variable (register): nInputs:

i indicates that we want the ith

number in the Fibonacci sequence

start commands the circuit to beginthe operation

Outputs:

F is the ith number in the Fibonaccisequence (held in t1)

ready indicates that the circuit is idleand ready to take input. Default valueis 0.

done-tick is asserted for one clock cyclewhen the operation is complete.Default value is 1.

t0← 0t1← 1n← i

IDLE

ready← 1

F

T

start = 1

t1← 0n = 1

t0← t1t1← t1 + t0n← n− 1

OP

FT

T

F

n = 0

DONE

done_tick← 1

VHDL

1 -- The Fibonnaci circuit. Make sure the ready line is high, then2 -- input the index of the Fibonacci number you want on the i bus and3 -- pull the start line high for one clock cycle, then wait for it to4 -- calculate the corresponding Fibonacci number. The done_tick signal5 -- will go high for one clock cycle when the computation is done.6 library ieee;7 use ieee.std_logic_1164.all;8 use ieee.numeric_std.all;9

10 entity fib is11 port(12 clk, reset : in std_logic;13 start : in std_logic;14 i : in std_logic_vector(4 downto 0);15 ready, done_tick : out std_logic;16 F : out std_logic_vector(13 downto 0)17 );18 end fib;1920 -- It is implemented as an FSMD.21 architecture arch of fib is22 type state_t is (IDLE, OP, DONE);23 signal state, state_next : state_t;24 signal t0, t0_next, t1, t1_next: unsigned(13 downto 0);25 signal n, n_next: unsigned(4 downto 0);26 begin

VHDL

26 begin27 -- FSMD state and data registers. Everything is clocked together.28 process(clk,reset)29 begin30 if reset = ’1’ then31 state <= idle;32 t0 <= (others => ’0’);33 t1 <= (others => ’0’);34 n <= (others => ’0’);35 elsif rising_edge(clk) then36 state <= state_next;37 t0 <= t0_next;38 t1 <= t1_next;39 n <= n_next;40 end if;41 end process;

VHDL43 -- Next state and datapath logic. All mushed together.44 process(state,n,t0,t1,start,i,n_next)45 begin46 state_next <= state; -- provide defaults47 t0_next <= t0;48 t1_next <= t1;49 n_next <= n;50 case state is51 when IDLE =>52 if start = ’1’ then53 t0_next <= (others => ’0’);54 t1_next <= (0=>’1’, others => ’0’);55 n_next <= unsigned(i);56 state_next <= OP;57 end if;58 when OP =>59 if n = 0 then60 t1_next <= (others => ’0’);61 state_next <= DONE;62 elsif n = 1 then63 state_next <= DONE;64 else65 t1_next <= t1 + t0;66 t0_next <= t1;67 n_next <= n - 1;68 end if;69 when DONE => state_next <= IDLE;70 end case;

VHDL

73 -- Output logic74 F <= std_logic_vector(t1);75 done_tick <= ’1’ when state = DONE else ’0’;76 ready <= ’1’ when state = IDLE else ’0’;7778 end architecture arch;

VHDL

7980 -- Alternate next state and datapath logic. Easier to read and debug.8182 state_next <= OP when state = IDLE and start = ’1’ else83 DONE when state = OP and n < 2 else84 IDLE when state = DONE else85 state;8687 t0_next <= (others => ’0’) when state = IDLE and start = ’1’ else88 t1 when state = OP and n > 1 else89 t0;9091 t1_next <= (0=>’1’, others => ’0’) when state = IDLE and start = ’1’ else92 (others => ’0’) when state = OP and n = 0 else93 t1 + t0 when state = OP and n > 1 else94 t1;9596 n_next <= unsigned(i) when state = IDLE and start = ’1’ else97 n - 1 when state = OP and n > 1 else98 n;

VHDL Testbench1 library IEEE;2 use IEEE.STD_LOGIC_1164.ALL;34 entity Fibonacci_testbench is5 end Fibonacci_testbench;67 architecture Behavioral of Fibonacci_testbench is8 signal i: std_logic_vector(4 downto 0);9 signal f: std_logic_vector(19 downto 0);

10 signal clk, start, ready, done, reset: std_logic := ’0’;11 begin12 clk <= not clk after 10 ns;13 uut: entity work.fib(arch)14 port map( i => i, F=> f, reset => reset,15 clk => clk, start => start,16 ready => ready, done_tick => done);

17 test: process18 begin19 start <= ’0’;20 i <= "00111";21 reset <= ’1’;22 wait for 21 ns;23 reset <= ’0’;24 if ready /= ’1’ then25 wait until ready = ’1’;26 end if;

27 start <= ’1’;28 wait for 20 ns;29 start <= ’0’;30 wait until done = ’1’;31 wait;32 end process;33 end Behavioral;

ceng 342 – digital systems

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