calice ecal readout hardware status report adam baird ecal meeting 26 sept 2003 llr-ecole...
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![Page 1: Calice ECAL Readout Hardware Status report Adam Baird ECAL Meeting 26 Sept 2003 LLR-Ecole Polytechnique](https://reader038.vdocuments.us/reader038/viewer/2022110207/56649d625503460f94a43de9/html5/thumbnails/1.jpg)
Calice ECAL Readout Hardware
Status report
Adam Baird
ECAL Meeting 26 Sept 2003
LLR-Ecole Polytechnique
![Page 2: Calice ECAL Readout Hardware Status report Adam Baird ECAL Meeting 26 Sept 2003 LLR-Ecole Polytechnique](https://reader038.vdocuments.us/reader038/viewer/2022110207/56649d625503460f94a43de9/html5/thumbnails/2.jpg)
Calice - ECAL• Hardware - Readout Module
• Firmware– front FPGA (from Osman Zorba)– Trigger (from Matthew Warren)
Adam Baird
Rutherford Appleton Laboratory
![Page 3: Calice ECAL Readout Hardware Status report Adam Baird ECAL Meeting 26 Sept 2003 LLR-Ecole Polytechnique](https://reader038.vdocuments.us/reader038/viewer/2022110207/56649d625503460f94a43de9/html5/thumbnails/3.jpg)
Adam Baird
Rutherford Appleton Laboratory
![Page 4: Calice ECAL Readout Hardware Status report Adam Baird ECAL Meeting 26 Sept 2003 LLR-Ecole Polytechnique](https://reader038.vdocuments.us/reader038/viewer/2022110207/56649d625503460f94a43de9/html5/thumbnails/4.jpg)
Adam Baird
Rutherford Appleton Laboratory
![Page 5: Calice ECAL Readout Hardware Status report Adam Baird ECAL Meeting 26 Sept 2003 LLR-Ecole Polytechnique](https://reader038.vdocuments.us/reader038/viewer/2022110207/56649d625503460f94a43de9/html5/thumbnails/5.jpg)
Adam Baird
Rutherford Appleton Laboratory
![Page 6: Calice ECAL Readout Hardware Status report Adam Baird ECAL Meeting 26 Sept 2003 LLR-Ecole Polytechnique](https://reader038.vdocuments.us/reader038/viewer/2022110207/56649d625503460f94a43de9/html5/thumbnails/6.jpg)
Adam Baird
Rutherford Appleton Laboratory
![Page 7: Calice ECAL Readout Hardware Status report Adam Baird ECAL Meeting 26 Sept 2003 LLR-Ecole Polytechnique](https://reader038.vdocuments.us/reader038/viewer/2022110207/56649d625503460f94a43de9/html5/thumbnails/7.jpg)
Adam Baird
Rutherford Appleton Laboratory
Analogue - Front panel96 (8x2x6) Differential Analogue inputs (max), 16 bits 500KHz16 (8x2x1) Differential Analogue outputs (max), 16 bits 1MHz
Digital - Front panel544 (8x2x34) bi-directional busLVDS pairs (max), Peak data rate @ 100MHz = 54.4G bits/s
Processing Power - 12M Xilinx Virtex-II gates (max).
Readout - Back panel - 64 bit VME interface, plus 48 LVDS pairs
Calice ECAL - Readout Module
![Page 8: Calice ECAL Readout Hardware Status report Adam Baird ECAL Meeting 26 Sept 2003 LLR-Ecole Polytechnique](https://reader038.vdocuments.us/reader038/viewer/2022110207/56649d625503460f94a43de9/html5/thumbnails/8.jpg)
CMS Final Front End driver
Adam Baird
Rutherford Appleton Laboratory
![Page 9: Calice ECAL Readout Hardware Status report Adam Baird ECAL Meeting 26 Sept 2003 LLR-Ecole Polytechnique](https://reader038.vdocuments.us/reader038/viewer/2022110207/56649d625503460f94a43de9/html5/thumbnails/9.jpg)
CMS Final Front End driver
Adam Baird
Rutherford Appleton Laboratory
![Page 10: Calice ECAL Readout Hardware Status report Adam Baird ECAL Meeting 26 Sept 2003 LLR-Ecole Polytechnique](https://reader038.vdocuments.us/reader038/viewer/2022110207/56649d625503460f94a43de9/html5/thumbnails/10.jpg)
Timescales
Adam Baird
Rutherford Appleton Laboratory
Completion 2wks (from today)PCB Fabrication, 3wksPCB assembly, 1wkJTAG test, 1wk (mid Nov)VFE test (Jan 2003 ???)3 Months test3 Months production (30 June 2003)
![Page 11: Calice ECAL Readout Hardware Status report Adam Baird ECAL Meeting 26 Sept 2003 LLR-Ecole Polytechnique](https://reader038.vdocuments.us/reader038/viewer/2022110207/56649d625503460f94a43de9/html5/thumbnails/11.jpg)
Adam Baird
Rutherford Appleton Laboratory
Calice ECAL Firmware
Front FPGAADC data captureVFE control
Back FPGAData managementTrigger control
VME FPGA