beyond immersion patterning enablers for the next...

Beyond Immersion – Patterning Enablers for the Next Decade Colin Brodsky Manager and Senior Technical Staff Member Patterning Process Development IBM Semiconductor Research & Development Center Hopewell Junction, NY Semicon Europa

October 2011

Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12, 2011 2

Lithography: Rayleigh vs. Moore

Rayleigh: Minimum half-pitch feature = 2 k1 l / NA

Moore: Density halves every 2 years

To keep up with Moore, Rayleigh must decrease k1, l or increase NA:

Numerical Aperture: NA Immersion High Index Immersion

Wavelength: l EUV (NA: 0.25 0.33 0.4x?)

Complexity of Imaging Solution: k1 Aggressive Resolution Enhancement & Double Patterning

• Resolution Enhancement Techniques (RETs) allow driving k1 toward physical limit (0.25) by aggressive manipulation of optical wavefront

• Co-optimization with design and computationally solved conditions drive to most cost effective solutions

• Double / Multi Patterning allows extension of optical below k1 < 0.25, but has cost implications: increased process steps and mask count

Unprecedented material and process innovations will be required to close the gap to EUV readiness


Technology Innovation Pipeline

Fundamental Research

New materials, processes, &

devices

IBM Almaden & Yorktown

Advanced Semiconductor

R&D

Innovation in process & packaging

technology

Process Element & Device Exploration (Pre-T0 Alliance)

Adv. Packaging Center / 3Di

Equipment Dev. Center (EDC)

Sematech

Albany Nanotech Center

Technology Development

High Perf SOI Technology Alliance Foundry Bulk Technology Alliance Packaging Development Alliances

Multi-company co-located joint

development

IBM East Fishkill IBM Bromont

Si Nanowires

Low Dimensional Carbon Electronics

Phase Change Memory (PCM)

Silicon Nanophotonics


Developing a world class high technology work force for New York, IBM and the world.

No corollary exists in the industry for collaboration between academia, State government and industry

Albany Nanotech Research Facility

A unique partnership between New York State, IBM, College of Nanoscale Science & Engineering (CNSE), SEMATECH and leading edge semiconductor manufacturers and suppliers from around the globe on a state of the art pilot line.

.


Collaborative Innovation Ecosystem in Albany

http://www.novellus.com/


East Fishkill Technology Development

Co-exists with state of the art manufacturing

facility spanning many technology nodes

Uniquely flexible manufacturing and tooling

capabilities

Deep library of yield-proven “building blocks”

Diverse and flexible toolsets

An ideal environment to test the yield limits of

new process elements

Power7 Watson


Collaboration brings together system-level, circuit design, process,

packaging, & manufacturing skills

Why Collaborate?

Industry Realities:

Technology advancements have shifted

from scaling to innovation

Process development costs escalating

Benefits of Collaboration:

Shared cost of R&D

Greater R&D resources

Shared learning

Synergistic engineering skills

Manufacturing sourcing flexibility for

leverage & risk mitigation

Collaborate on design enablement IP

(i.e., design kits, libraries, DFM, &

design services)

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Gain by Traditional Scaling Gain by Innovation

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IBM Transistor Performance Improvement

Process Development Cost by Node

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($M

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Lithography Solutions: Historical Perspective

Lithography Research

Tool

Prototype

Tool

First Full

Chip

Production

KrF (248nm) 1984 1984 1988 1992

ArF (193nm) 1989 1993 1996 2002

Immersion ArF 1997 Nov. 2003 Nov. 2004 2007

EUV (13nm) 1992 2006 2008 2015-16

• Implementation of new lithography solutions required long term development programs with industry-wide cooperation • EUV presents an extraordinary challenge even in this historical context


Immersion (ArFi) Development Timeline at IBM

• Industry moves away

157 nm (F2)

• IBM initiates ASML

partnership on ArFi

2003

• 1150i Prototype in

Holland

• 1150i shipped to ANT;

1st images in Oct.

• IBM demos industry 1st

chip with ArFi in Dec.

2004 2005

• Collaboration on

industry standards with

ASML & SEMATECH

• Collaboration on

materials solutions with

resist vendors &

academia

2006

• 1400i for ArFi

implementation in dev

Bridge Tool

• 45 nm development

• Defectivity Learning

2007

• 1700i (1.2 NA) in NY

Manufacturing Tool

• 45 nm qualification

2008

• 45 nm manufacturing

with multiple

critical levels of ArFi

• Enabled P7 ramp

http://upload.wikimedia.org/wikipedia/commons/b/b5/Immersion_lithography_illustration.svg

http://upload.wikimedia.org/wikipedia/commons/b/b5/Immersion_lithography_illustration.svg


Challenges of Introducing a New Litho Wavelength

Immersion (ArFi) EUV

Water in Scanner High Vacuum

Materials Interactions New Wavelength (13.5nm)

Hyper-NA (>1) Reflective Optics

Same Wavelength New Mask

Same Masks No Pellicle

Same Resists New Resists

• Immersion presented many challenges, but many elements ported for dry ArF

• EUV is a significantly more challenging endeavor, requiring more innovative

comprehensive solutions


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50

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ADT NXE 3100 NXE 3300

Po

we

r (W

)Primary EUV Technology Challenges

Resist

LER Sensitivity

Resolution

Image Placement (to Match Fleet)

Collapse

DEFECTIVITY:

WAFER

MASK

SCANNER

Source Power & Reliability


Cost Effective Lithography ?

For any solution, the cost of scaling must make economic sense

Cost per what? Wafer? Chip? Transistor?

CoO models are specific to each fab, market segment

Different answer for each market segment: memory, consumer, MPU, server…

Different answer for each product / part number: wafers/mask

EUV: Throughput, reliability, yield, mask cost Availability

DPL: Throughput, reliability, yield, mask cost

For any solution to be economically feasible it must be:

Available

Free of cost prohibitive processing

• How many masks per level ?

Proven robust for manufacturing


193 nm Lithography Extension: Continuous Innovation

2008 2010 2012 2014 2016

45 nm 32 nm 22 nm 14 nm 10 nm

Immersion

(ArFi)

2nd Generation

Immersion

3rd Gen ArFi w/

Source Mask

Optimization

(SMO)

4th Gen ArFi w/

SMO & Double

Patterning

(DPL)

EUV (or MPL)

• 2 Year Cycles to Enable 50% Area Shrink Node-to-Node

• Advancements in tooling, RETs, materials, controls…


Double Patterning Techniques

Many strategies under consideration:

Litho-Etch-Litho-Etch (LELE, aka DE2 – Double Exposure, Double Etch)

Litho-Litho-Etch (LLE, aka DETO – Double Expose Track Only)

Sidewall Image Transfer (SIT, aka SADP – Self Aligned Double Patterning )


Positive Tone vs Negative Tone Dissolution

Aqueous Developer

Organic Solvent

Developer

Expose PEB & Develop Post Develop Structure

• Organic solvent developer with “positive tone like” resists, results in a negative tone process

Positive Tone Develop Process

Negative Tone Develop Process


Double Patterning of Line / Space: Negative vs Positive Tone Development

The use of bright field mask in combination with NTD process gives wider process window than a standard process using dark field imaging and positive tone TMAH developer.

Bright field imaging of contacts, vias, metals: key enabler for extending optical lithography via single or double patterning

NTD PTD

EL max

(%)

17.7 11

DoF @

5% EL

(nm)

130 120

MEEF 1.9 2.4

LER (nm) 3.2 5.3

Process window for trenches printed 36nm at

pitch 128nm for NTD LELE


Tone-Inversion Sequence

Overcoat

Resist

Extraction &

Amplification

Etch for Trench

Control

Overburden

Etch

Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12, 2011 18 18

Tone Inversion vs Negative Tone LELE: Post Etch M2

18 10/26/2011

Tone Inversion Pitch Split (LLE) Negative Tone Develop Pitch Split (LELE)

Colin Brodsky Semicon Europa 2011 Dresden, Germany Oct 12, 2011 19 19

M1

M2

M3

Electrical

Test

Electrical

Yield

Opens 97%

Shorts 100%

Isolated Via 100%

3 Metal Build Patterned by Tone Inversion Pitch Split


The Defect Challenge

Lack of a mature EUV solution will drive ingenuity in extending 193 nm immersion lithography to fill the void

Many of these solutions will introduce new materials and processes not yet exercised in manufacturing

Negative tone solvent-based developer

“Freeze” develops

193 immersion lithography over severe topography

Resist extractions

Multi-patterning solutions require exceptional defect learning rates

Must achieve composite D0 consistent with D0 roadmap for a single pattern level

More than ever before, we need aggressive defect learning early in the technology cycle


Increasing role for electrical learning vehicles

Dedicated yield learning masks and

process routes are increasingly common in

wafer fabs

Single level and integrated module builds

Eliminates optical capture rate concerns

Optical inspections continue to have value

Fast, non-destructive testing for controls

Good pre-requisite for screening, but limited

capture rate for many failure modes

Electrical learning vehicles remain a relatively untapped opportunity for vendors

Important proving ground

More data transparency can provide credibility and help align industry momentum around successful candidates

Requires a new level of collaboration

Defect Detection Method

Optical/SEM Electrical

Time to

detect Hours Days

Cost $$-$$$ / wafer $$$-$$$$ / wafer

Vendor

access

On site,

via consortia,

IDMs/Foundries

IDMs/Foundries

Capability Necessary but

not sufficient The final arbiter


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y polarized

1% ceiling value

Reflections on Trilayer

Trilayer enabled 193 nm extension to high-NA immersion lithography

High NA reflectivity challenges solved with familiar track-based processes

Now a proven manufacturing solution for multiple technology nodes

This did not come for free – many process challenges solved

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nsinq (NA)

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polarized

y polarized

1% ceiling value

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nsinq (NA)

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y x polarized

50-50 x&y

polarized

y polarized

1% ceiling value

Conventional Single-Layer BARC Spin-on Trilayer Solution

1.2 NA 1.2 NA


Reflections on Trilayer

Consider a common 32 nm patterning stack:

4 spin-cast layers

Twice the defect opportunity as compared to typical 65 nm stack

Twice the opportunity for inducing micro-bridging

Two layers are not immediately imaged

Defects revealed only after a destructive substrate etch/strip process

Requiring destructive evaluations erodes many advantages of optical inspection

Wafer and processing cost increases

Time to process increases

Electrical learning vehicles become increasingly attractive

Do we want any doubts about the results after making these investments?

Substrate

Planarization and

Transfer Layer

Spin-on Si Hardmask

Photoresist

Topcoat

One type of defect –

but many root causes


Making Trilayer Successful

Photochemical filtration and dispense recognized as a critical

element

Accelerated defect learning key to maintaining composite D0 roadmap

Motivated new partnerships with deeper level of collaboration

Access to electrical learning vehicles

Access to state of the art optical inspection tools

Opportunity to prove process candidates over extended trials in a true

manufacturing environment


Resist filtration improvements

Dual-membrane filtration

reduces variability and

improves yield

Data collected on specialized

yield learning vehicle

Test capability can discriminate

single-line bridges versus larger

multi-line bridges

Optical inspection unable to

reveal these differences


Transfer Layer Improvements

Buried transfer layers increase the

detection challenge

Signals not visible in post-photo optical

monitoring

Low capture rate after etch / metallization

Often chasing low-level and variable

signals

Electrical test quickly points towards

improved solutions

100 % capture rate with strong signal

strength

Comparing two solvent prewets

for a buried transfer layer

0%

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100%

Electrically Extracted D0

Cu

mu

lati

ve

Po

pu

lati

on

Solvent 1

Solvent 2


Photochemical Solvent Purity

PPB levels of metallic contaminants

can drive patterning failures

Commonly observed as microbridged

lines or silicon spikes after pattern

transfer

Not detected in photo sector with

optical defect monitors

Must tradeoff cost of purification

versus photochemical savings

No photochemical

prewet

Single level of

photochemical

prewet

Two levels of

photochemical

prewet

Ele

ctr

ica

lly e

xtr

acte

d D

0Data from early 32 nm process highlighted

critical defect mode not detectable with

conventional monitoring


What can we expect with negative tone developer?

Dramatically increased exposure to similar

solvents

Aggressive purification specs will drive more

photochemical expense

A 1 ppb incoming supply spec is estimated to

drive $0.25/wafer pass for negative tone develop

solvent

Solvent prewet experience suggests part-per-

trillion specs will be required

Key opportunity for proven fab-level and point

of use purification solutions

Total Dispense

(mL)

Residence time

on wafer

(seconds)

Solvent PrewetSolvent Develop


Summary

EUV is inevitable but delayed

Field remains wide open for creative 193 nm process-oriented

extensions

Strong collaborative alliances create the necessary climate to achieve

proof of concept demonstrations

Creativity must be married to disciplined defect learning

Deeper collaboration models extending into wafer fabs will be

required to meet the challenge

beyond immersion patterning enablers for the next...

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