balsaopt a tool for balsa synthesis
DESCRIPTION
Francisco Fernández-Nogueira, UPC (Spain) Josep Carmona, UPC (Spain). BalsaOpt a tool for Balsa Synthesis. Contents. Logic Synthesis into the Balsa flow Design flow Structural methods to fight the state explosion Structural Clustering based on Petri nets composition Experimental Results. - PowerPoint PPT PresentationTRANSCRIPT
1
BalsaOpt a tool for Balsa Synthesis
Francisco Fernández-Nogueira, UPC (Spain)
Josep Carmona, UPC (Spain)
2
Contents Logic Synthesis into the Balsa flow
Design flow Structural methods to fight the state
explosion Structural Clustering based on Petri nets
composition Experimental Results
3
Logic Synthesisinto the Balsa System
4
Design flow
Cluster HCs
5
Describe Behavior
Design flow
| | | |
;
6
Compose STGs
Design flow
| |
| |
;
| |
;
| |
7
Hide Internals
Design flow
8
State Explosion Problem
Enumerate States
Design flow
PETRI NET
STATE GRAPH
9
Contents Logic Synthesis into the Balsa flow
Design flow Structural methods to fight the state
explosion Structural Clustering based on Petri nets
composition Experimental Results
10
Structural Methods
Solve CSC (Moebius [Carmona et al. 2006])
MILP formulation:MILP “s=0 implicit” MILP “s=1 implicit”
#(σ1,s+) = #(σ1,s-) +
1#(σ2,s-) = #(σ2,s+) +
1M0[s=0] + M0[s=1] = 1
11
Structural Methods
Project into Signal Support (Moebius [Carmona et al. 2006]) + Delete Dummies
12
Enumerate States
Structural Methods
PETRI NET STATE GRAPH
13
Synthesize (Petrify [Cortadella et al. 1996])
Structural Methods
ack_16 = csc_2' csc_3' csc_1'
LOGIC EQUATION (ack_16)
14
Contents Logic Synthesis into the Balsa flow
Design flow Structural methods to fight the state
explosion Structural Clustering based on Petri
nets composition Experimental Results
15
Clustering Techniques
Cluster HCs
16
Clustering Techniques
Cluster HCs
17
Describe Behavior
Clustering TechniquesComplex STG
18
Structural Clustering Techniques
• Well-structured Petri net subclasses: State machine (SM), Marked Graph (MG), Free-choice (FC) and Asymmetric choice (AC)
• Idea: well-structured STGs will be obtained if the growth of cluster is bounded by one of these subclasses
startnode
MG
SM
SM
MG
FC
MG SM
AC
FC
MG
MG
FC
AC
19
Structural Clustering Techniques
PN Class of Synchronization Area
20
Structural Clustering Techniques
PN Class of HC Connection
21
Clustering Techniques
Cluster HCs
22
Clustering Techniques
Cluster HCs
23
Clustering Techniques
Describe Behavior
24
Experimental Results
25
Conclusions
Structural Clustering Techniques
To Avoid complex STGsTo Fulfill Structural Properties
Safe Logic Synthesis
Balsa [Edwards et al. 2002]
Moebius [Carmona et al. 2006]
Petrify [Cortadella et al. 1996]
Structural Clustering Techniques[Fernández-Nogueira et al. 2008]
Logic Synthesisinto the Balsa System
+
+
+
26
Conclusions The design of async circuits cannot be
faced without the help of CAD tools. This work is an example where the theory
of Petri nets helps for optimizing async circuits. Advocate for interdisciplinary research.
Future Work: Other optimization goals: energy
consumption. Specification of more HCs
Paper at PATMOS’08
27
Thank You!
Are There Any Questions?
28
Solve CSC (Petrify [Cortadella et al. 1996])
Logic Synthesis of async controllers
29
Project into Signal Support (Moebius [Carmona et al. 2006])
+ Structural Methods
30
+ Structural Methods
Enumerate States
State Explosion Problem
31
+ Structural Methods
Enumerate States
State Explosion Problem
32
Project into Signal Support (Moebius [Carmona et al. 2006]) + Delete Dummies
+ Structural Methods
TRASH SLIDES
34
Introduction: asynchronous
D1 D2 DN
in out...
...clock
t1 t2 tN-1
L1 L2 LNin out
...
C
1
C
2
C
N
...
t1 t2 tN-1
Asynchronous Advantages:
High Performance
Low Power Dissipation
Low Noise and Low Electromagnetic Emission
A Good Match with Heterogeneous System Timing
......
35
Structural Methods
Solve CSC (Moebius [Carmona et al. 2006])
MILP formulation:MILP “s=0 implicit”
MILP “s=1 implicit”
#(σ1,s+) = #(σ1,s-) + 1
#(σ2,s-) = #(σ2,s+) + 1
M0[s=0] + M0[s=1] = 1
36
Related Work
Assassin [Ykman-Couvreur et al. 1994]
Minimalist [Fuhrer et al. 1999]
Petrify [Cortadella et al. 1996]
Moebius [Carmona et al. 2006]
Tangram [van Berkel et al. 1999]
Balsa [Edwards et al. 2002]
Tangram+Assassin[Kolks et al. 1996]
Balsa+Minimalist[Chelcea et al. 2002]
Tangram+Petrify[Peña et al. 1996]
Balsa+Moebius+Petrify[Fernández-Nogueira et al. 2008]
Signal Transition Graphs
Handshake Components
State Based Methods
Structural Methods
CLP [Khomenko et al. 2002]
Burst-mode Finite-state Machines
Unfolding Methods
DesiJ [Schaefer & Vogler. 2007]
CSAT [Khomenko et al. 2003]
37
Introduction
Moore's Law System on a Chip
38
Delete Dummies
Design flow
39Synchronization Area
Structural Clustering Techniques
40PN Class of Synchronization Area
Structural Clustering Techniques
Introduction
“As it becomes impossible toAs it becomes impossible tomove signal across a largemove signal across a largedie within one clock cycle,die within one clock cycle,the likely result is a shift tothe likely result is a shift toasynchronous design styleasynchronous design style”.
International TechnologyInternational TechnologyRoadmap for SemiconductorsRoadmap for Semiconductors(ITRS 2001)(ITRS 2001)
Intel Pentium IV (47M transistors)
42
Summary of problems for shifting to asynchronous
1. Asynchronous circuits are difficult to design, need for CAD tools.
2. Most of the dominant CAD tools for asynchronous synthesis suffer from the state explosion problem.
3. If asynchronous HDLs are used, the derived circuits are unoptimized, in terms of area and speed.
43
Contents Introduction Synthesis of async circuits
VLSI programming Logic synthesis
Logic Synthesis into the Balsa flow Design flow Structural methods to fight the state explosion Structural Clustering based on Petri nets
composition Experimental Results
44
Asynchronous Hardware Description Languages
(a?byte & b!byte)begin
x0: var byte | forever do
a?x0 ; b!x0od
end
Buffer
*
xa bT
;
T
a b
passive port
active port
Data pathEach circle mapped to a netlist
FFx not x
li
lo ri
ro
45Syntax-directed Translation
procedure buffer2 (input i1,i2 : byte;
output o1,o2 : byte;) isvariable x1,x2 : byte;begin loop i1 -> x1 || i2 -> x2 ; o1 <- x1 || o2 <- x2 endend
Balsa [Edwards et al. 2002]
Asynchronous Hardware Description Languages
46
Contents Introduction Synthesis of async circuits
VLSI programming Logic synthesis
Logic Synthesis into the Balsa flow Design flow Structural methods to fight the state explosion Structural Clustering based on Petri nets
composition Experimental Results
47
Logic Synthesis of async controllers
DSr
LDTACK
LDS
DTACK
D
VME BusController
Device
DSw
DataTransceiver
Bus
Describe Behavior
PETRI NET
48
Enumerate States
Complete State Coding Conflicts
Logic Synthesis of async controllers
PETRI NETSTATE GRAPH
49
Logic Synthesis of async controllers
Solve CSC (Petrify [Cortadella et al. 1996])
50
Synthesize (Petrify [Cortadella et al. 1996])
lds = csc0 + dd = ldtack csc0dtack = dcsc0 = dsr (csc0 + ldtack')
Logic Synthesis of async controllers
LOGIC EQUATIONS