Case Study:Xilinx Synthesis Tool (XST)

Arrays & Records

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Multi-Dimensional Arrays

No restriction on the number of dimensions− Previously: up to 3 dimensions.

Indexes can be variable. Array > one-dimension:

− Not accepted as ports Supports array aggregate Can be:

− Signals− Constants− variables

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Multi-Dimensional Arrays

• Allowed operations with arrays:AssignmentsArithmetic operationsPass multi-dimensional arrays to functionsUse them in instantiations

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Multi-Dimensional Arrays

Array must be fully constrained in all dimensions

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subtype WORD8 is STD_LOGIC_VECTOR (7 downto 0);type TAB12 is array (11 downto 0) of WORD8;type TAB03 is array (2 downto 0) of TAB12;

subtype TAB13 is array (7 downto 0,4 downto 0) of STD_LOGIC_VECTOR (8 downto 0);

Records

XST supports record typesA field of a record type can also be of type record.Supports aggregate assignments to record

signals.Constants can be record types.

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Data Types

• Integer, natural and positive: Implemented on 32 bits by default.

• Real: for calculations only,

− such as the calculation of generic values• Boolean, bit, bit_vector, unsigned, signed

Fully supported

• Unconstrained ports: Ports can be constrained or unconstrained.

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Data Types

• Std_logic, std_ulogic, X01, X01Z, UX01, UX01Z:

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Tri-State Buffers

• VHDL Coding for tri-state buffers: Concurrent:O <= I when T = '0' else (others => 'Z'); Process:

process (T, I)begin if (T = '0') then O <= I; else O <= 'Z'; end if;end process;

•  

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Tri-State Buffers

Inferred tristate buffers are implemented with different device primitives when driving an:

− Internal bus (BUFT)− External pin of the circuit (OBUFT)

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Tri-State Buffers

• Buffer ports: Xilinx recommends: Do not use buffer port mode.

− Is a potential source of errors during synthesis.− Complicates validation of post-synthesis results through

simulation.

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Tri-State Buffers

Converting tristate buffers to logic:− Some devices do not support internal tristates. − XST replaces the internal tristates of those devices

with equivalent logic using the Convert Tristates to Logic (TRISTATE2LOGIC) constraint.

− generally increases area. If your optimization goal is area, set this

constraint to no.

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Recursion

• Recursive Instantiation: XST supports VHDL recursive component

instantiation.− To prevent endless recursive calls, the number of

recursions is limited by defaultto 64.− Use -recursion_iteration_limit to specify the

number of allowed recursive calls.

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Recursion Example

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Recursion

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Configuration

• Configuration XST supports component configuration in the declarative part of the

architecture. Supported only with the all clause for instances list.

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for instantiation_list : component_name use LibName.entity_Name(Architecture_Name);entity FULLADDER is. . .end FULLADDER;

architecture STRUCT of FULLADDER is

for MODULE1: HALFADDER use entity work.HALFADDER (RTL);for MODULE2: HALFADDER use entity work.HALFADDER (RTL); begin….end STRUCT;

Generic

• Generic:XST supports all types for generics including:

− integer− boolean− string− real− std_logic_vector

Declare a generic with a default value.

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Concurrent Signal Assignments

• Unsupported:after clause, transport or guarded options,waveforms

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Generate

• for-generateSupported for constant bounds only

• if-generate Supported for static conditions only

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If-then-else, case-when

• if statement:Supports nested if statement

• case statement:Supports case statement

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Loops

• for-loop:

Supports for-loops for:− Constant bounds

for I in 7 downto 0 loop

• Next and Exit: Supported

• while loop: Supported

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Process

• Combinational Process: sensitivity list must contain:

− All signals in conditions (for example, if and case).− All signals on the right-hand side of an assignment.

For missing signals in the sensitivity list:− XST issues a warning message.− XST adds the missing signals to the sensitivity list.

To avoid problems during simulation:− Explicitly add all missing signals in the HDL source code.

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Process

• Sequential Process with sensitivity list:A sensitivity list containing:

− clock signal− optional signal controlling the sequential

element asynchronously(asynchronous set/reset).

− if statement that models the clock event.− If clk’event and clk = ‘1’ then− If clk’event and clk = ‘0’ then− If rising_edge(clk) then− If falling_edge(clk) then

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Process

• Sequential Process with wait: Allows only one wait statement:

− The wait statement is the first statement.− The condition in the wait statement describes the

sequential logic clock. Describing clock enable (type 1):

processbegin wait until rising_edge(clk) and clken = '1';q <= d;end process;

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Process

• Sequential Process with wait: Describing clock enable (type 2):

processbegin wait until rising_edge(clk); if clken = '1' then q <= d; end if;end process;

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Process

• Sequential Process with wait: Describing Synchronous Control Logic(sync. set/reset):

− You cannot describe a sequential element with asynchronous control logic using a process without a sensitivity list.

XST does not allow the description of a Latch based on a wait statement.

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Subprograms• Functions and Procedures:

Supported

• Resolution functions: Not supported except the function defined in the

IEEEstd_logic_1164 package

• Recursive functions: Supported

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function my_func(x : integer) return integer isbegin

if x = 1 then return x;else return (x*my_func(x-1));end if;

end function my_func;

Packages

• Supported packages and types: numeric_std unsigned, signed std_logic_arith unsigned, signed std_logic_unsigned, std_logic_signed std_logic_vector

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Operator

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References

• [XST12] XST User Guide for Virtex-6,• Spartan-6, and 7 Series Devices, UG687 (v 14.1) April,

2012.

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