backside illumination technology for soifor soi- … workshops/2009 workshop... · •1 iisw2009...

• 1

IISW2009 Symposium B. Pain 1

Backside Illumination Technology Backside Illumination Technology

For SOIFor SOI--CMOS Image SensorsCMOS Image Sensors

Bedabrata Pain

Edict Inc

[email protected]

310-666-6749

2009 IISW Symposium on

Backside Illumination of Solid-State Image Sensors

June 25th 2009

Bergen, Norway


ACKNOWLEDGMENT

My ex-colleagues at JPL, specially Tom Cunningham, Chao Sun, Chris Wrigley, Suresh Seshadri, Xinyu Zheng, Victor White, Risaku Toda

Magnachip Semiconductor

Avago Technologies

Tom Joy

Homayoon Haddad

Prof. Durga Misra at New Jersey Institute of Technology

Indian Institute of Technology, Kharagpur

• 2


PROBLEMS of SMALL PIXELPROBLEMS of SMALL PIXEL


PIXEL SCALING TRENDS

Continuous Technology “Breakthrough” Needed to Keep up with the Scaling Trend

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0 1 2 3 4 5 6 7 8 9Pitch (um)

Tech. Node (um) Score (e/V)

[ ])m(Pitch)V(V

)m(Tech)e(FW Metric

dd

Ve

µ⋅µ⋅

=

ISSCC (1997-2007)

• 3


ANGULAR RESPONSE

ColorColor--crosstalkcrosstalk

StackStack--height + Obscurationheight + Obscuration

Sensitivity loss

Vignetting

Color X-talk

Spatial variation of x-talk

Poor angle response

0

20

40

60

80

100

120

-30 -20 -10 0 10 20 30Degrees

Relative Response

Numerical apertureNumerical aperture

-800 -600 -400 -200 0 200 400 600 800

Pixels

Cro

ss-t

alk

TelecentricityTelecentricity


0

10

20

30

40

50

60

70

80

90

100

1E+0 1E+1 1E+2 1E+3 1E+4 1E+5

Photons/pixel

dQE

QE 0.9 RN 2 alfa 0

QE 0.9 RN 2 alfa 0.2

QE 0.9 RN 10 alfa 0QE 0.5 RN 2 alfa 0

QE 0.5 RN 10 alfa 0.2

DETECTIVE QE (MODIFIED)

Increase QE (QE >= 100)

Reduce Noise (NR=0)

Eliminate X-talk (αααα=0)

( )( )[ ]

( )

( )

+α+α−

α−⋅=

==

⋅′

+α′+α−⋅α−⋅

PQE

N

PP

2

NP1PQE

P1QE

2in

2out

2R

2R

222

1

1QE

PSNR

SNRdQE

PhotonsPhotons

How well does it How well does it transfer power?transfer power?

Noise+XTNoise+XT

OutputOutput

[1, 2]

• 4


FRONT-SIDE ILD MODIFICATION

Difficulties in material selection

Process Complexities

Basic Problems remain

LIGHTPIPE APPROACHTHINNER FRONT-END[3]

[4]


BACKBACK--ILLUMINATIONILLUMINATION

• 5


•High Sensitivity and quantum

efficiency100 % fill-factor

•Excellent X-talk and Angular

Response“Canyon” effect eliminated

No obscuration

Spurious reflections eliminated

•Efficient microlens and anti-

reflection coatingPlanar surface

•Advanced pixel processingDynamic range expansion

Global shutter

Gain ranging

Low noise

•Compatibility with next generation

dielectrics and metals

BACK-ILLUMINATION: A SOLUTION

FRONT BACK

Light Absorption Point

ILD7 µm

Microlens

CFA

Bonded

Silicon

Substrate

500 µm

epi-Si

PD

5 µmILD

7 µm

Microlens

CFA

Silicon

Substrate

500 µm

epi-Si

PD

5 µm


CROSS-SECTION

•Collection much closer to microlens

•No Obscuration

•Supports larger numerical aperture

e

e[5]

• 6


BACK TO MAXWELL

Plenty of optical energy leakage due to pixel dimension, wave-effects, CFA

RG G

BG G

FDTD simulation of energy coupling


OPTICAL ADVANTAGE

Almost 3x improvement at F 2.0

21% 20% 78% 74%

Optical Coupling into Silicon for 1.75 µµµµm pixel

Front lllumination (TE/TM) Back lllumination (TE/TM)

• 7


QE & OPTICAL CROSS-TALK

0

10

20

30

40

50

60

70

80

90

100

0 1 2 3 4 5 6 7 8Pixel Pitch (um)

QE (%)

0

5

10

15

20

25

30

35

40

45

50

X-ta

lk (%

)OE-BI

OE-FI

X-talk-FI

X-talk-BI

F/1.8 Optics

•QE goes down and Cross-talk goes up

•QE loss due energy spread via E-M field propagation

•Front-side QE also limited by imperfect AR coating


BACK-THINNING ISSUES

• Accurately thinning 700 µµµµm substrate with <50 A0 surface roughness

Appropriate etch-stop

• Backside passivation

Hold exposed surface in accumulation

• Device support (during and after thinning)

Attachment of support wafers – must allow post-processing

• Packaging

Where do pads come out from? Wire-bond or CSP?

• AR coating, Color, Microlens

Alignment key

Stack issues

• Diffusion Cross-talk Control

Field-shaping implants

Back-surface gradients

Manufacturable + Wafer-level Processing + Good device performance

• 8


PASSIVATION OF EXPOSED SURFACE

PASSIVATION PROBLEM:PASSIVATION PROBLEM:

•Exposed Si-SiO2 interface quality is poor

– high trap density, potential pocket due to band-bending

– loss of blue QE and high dark current

Potential pocket due to Potential pocket due to positive charge in positive charge in native oxide + interface native oxide + interface trapstraps

Surface accumulation

Ev

Ec

Si

SiOx

Band Diagram


BACKSIDE TREATMENT

• Implant + RTA Anneal

– Cannot be used due to the presence of metals

• Implant + Laser Anneal [6, 7]

– PRNU, Dark current

•Delta-doping: few monolayers of boron added by MBE

to the back surface [8]

– Excellent results, but non-standard process

•Flash gate: deposited oxide + UV flooding [9, 10]

– Outgassing, Long-term stability

•Back-gate: deposited oxide + Silver capping [11]

– Non-desirable metal; AR coating issues

•Back-gate: deposited oxide + ITO gate

– Process Control; AR coating issues

• 9


FABRICATION STEPSFABRICATION STEPS


SOI TO THE RESCUE

Thin silicon layer: 200 nmThin silicon layer: 200 nm

BOX: 200 nmBOX: 200 nm

Thick Silicon SubstrateThick Silicon Substrate

NIR enhanced Imager

Thick silicon layer: 3Thick silicon layer: 3--10 10 µµµµµµµµmm

BOXBOX

Silicon SubstrateSilicon Substrate

Small Pixels

Thick silicon layer: 2Thick silicon layer: 2--10 10 µµµµµµµµmm

BOXBOX

CMOS readout/ADC

Pixels in handle wafer

Metal

interconnectsPixels

[12]

[13]

• 10


SOI IMAGER FABRICATION

• SOI wafer with thick device layer (~ 2-10 µµµµm)

• Imager-compatible bulk-CMOS process

600 µµµµm p-Si (0.1 ΩΩΩΩ-cm)

p-Si (50 ΩΩΩΩ-cm)

SiO2

6 µµµµm

6 µµµµm

600 µµµµm

5 µµµµm

p-Si (0.1 ΩΩΩΩ-cm)

80 µµµµm


SiO2

Deposited oxide

Deposited oxide/nitride Metal trace (0.7 µµµµm thick)

Planarized oxide

Implanted wells (devices)

80 µµµµm

[13, 14]


Silicon wafer Low Temperature bonding

SOI IMAGER FABRICATION

6 µµµµm

600 µµµµm

5 µµµµm


80 µµµµm80 µµµµm


SiO2

Deposited oxide


Planarized oxide


Starting Wafer

Bulk-CMOS process

Support wafer

attachment

Wafer thinning

Backside coating

Pad Opening

• Provides mechanical support

• Bonding process/material must be back-end compatible

[15]

• 11


THINNING

THINNING

• Wafer-level thinning

• Natural high-selectivity (Si-SiO2) etch-stop

PASSIVATION

• Buried oxide made by thermal oxidation

• Pre-implanted region for passivation

• Self-passivation: surface never exposed



SiO2

Deposited oxide


Planarized oxide

Silicon wafer


Chemical Etch

• Hot KOH/TMAH wet-etch

• RIE with SF6

• XeF2 vapor-phase

<200A

<20 A

KOH

<20A<500ALocal

<403000AGlobal

XeF2SF6

<200A

<20 A

KOH

<20A<500ALocal

<403000AGlobal

XeF2SF6


BACK-to-FRONT ALIGNMENT



Deposited oxide


Planarized oxide

Silicon wafer

ARC

80 µµµµm


Deposited oxide


Planarized oxide

Silicon wafer

Liner nitride

80 µµµµm

ARC

Exposed metal holds alignment keys

• 12


PAD OPENING

80 µµµµm

p-Si

Deposited oxide


Planarized oxide

Glass wafer

80 µµµµm

Back metal: Min. 300 Back metal: Min. 300 µµµµµµµµm widem wide

Bonding PadsBonding Pads

80 µµµµm


Deposited oxide

Deposited oxide/nitride

Planarized oxide

Silicon wafer

Opened PadsOpened Pads

SeeSee--through through

glass waferglass wafer


Handle Silicon

Device Silicon: 3.3 µµµµm

BOX

ILDILD

M0M0

600 µµµµm

0.2 µµµµm

10 µµµµm

5 µµµµm


80 µµµµm80 µµµµm2 µµµµm


SiO2

Deposited oxide


Planarized oxide

Glass wafer


600 µµµµm

0.2 µµµµm

10 µµµµm

5 µµµµm


80 µµµµm80 µµµµm2 µµµµm


SiO2

Deposited oxide


Planarized oxide

Glass wafer


THE CROSS-SECTION

SiO2

Front Silicon Glass Wafer

Cross-section after thinning[14, 17]

• 13


ALTERNATE INTEGRATION SCHEME

•Through silicon via is formed at the first metalization step

•Liner oxide for isolation

•Serves as alignment key for CFA/ML

Si

M4

M3

M2

M1

Oxide

Si

M4

M3

M2

M1

Oxide

ILD

Buried Oxide

ILD

Buried Oxide

Silicon Handle Wafer

Oxide

STI


Oxide

STI

Deep silicon via formation

Finish metallization

Support Wafer + Thinning

[17, 18]


ALTERNATE INTEGRATION SCHEME

Final Cross-section


BOXPassivation

• 14


POSSIBLE EVOLUTION

e p i

S T I

I L D

M 3

M 2

M 1

S i

H a n d l e W a f e r

h ?

B O X

P a s s i v a t i o n / A R c o a t i n g

B o n d e d i n t e r f a c e

M 4

e p i

S T I

I L D

M 3

M 2

M 1

S i


h ?h ?

B O X

P a s s i v a t i o n / A R c o a t i n g


M 4M 4

pixel arrayISP ISP

e p i

S T I

IL D

M 3

M 2

M 1

S i


h ?

B O X

P a s s i v a t i o n / A R c o a t in g


M 4

e p i

S T I

IL D

M 3

M 2

M 1

S i


h ?h ?

B O X



M 4M 4

e p i

S T I

IL D

M 3

M 2

M 1

S i

H a n d le W a fe r

h ?

B O X

P a s s i v a t io n / A R c o a t in g

B o n d e d in te rf a c e

M 4

e p i

S T I

IL D

M 3

M 2

M 1

S i

H a n d le W a fe r

h ?h ?

B O X



M 4M 4

Handle wafer with through vias and Cu or Al bumps

Image sensor only (no ISP)

Test pad

e p i

S T I

IL D

M 3

M 2

M 1

S i


h ?

B O X



M 4

e p i

S T I

IL D

M 3

M 2

M 1

S i


h ?h ?

B O X



M 4M 4

e p i

S T I

IL D

M 3

M 2

M 1

S i

H a n d le W a fe r

h ?

B O X



M 4

e p i

S T I

IL D

M 3

M 2

M 1

S i

H a n d le W a fe r

h ?h ?

B O X



M 4M 4


Image sensor only (no ISP)

Test pad

2nd Generation

Higher Dynamic Range – In-pixel Cap

Better Z-height - WLCSP

1st Generation

Through Silicon Contacts for wirebonds

Pixel optimization

3rd Generation

Only pixel in wafer – best peformance

SOC integration


Test pad

epi

STI

ILD

M3

M2

M1

Si

Handle Wafer

BOXPassivation /AR coating

Bonded interface

M4

epi

ILD


epi

STI

ILD

M3

M2

M1

Si

Handle Wafer

h?

BOX

Passivation/AR coating

epi

STI

ILD

M3

M2

M1

Si

h?h

BOX


Bonded

interface

Pixel transistors, analog and/or some ISP

Top die: Photodiode

and transfer

gate

Bottom die:

Pixel

Xistors and addressing

Interface

connection


Test pad

epi

STI

ILD

M3

M2

M1

Si

Handle Wafer


Bonded interface

M4

epi

ILD


epi

STI

ILD

M3

M2

M1

Si

Handle Wafer

h?

BOX


epi

STI

ILD

M3

M2

M1

Si

h?h

BOX


Bonded

interface

Pixel transistors, analog and/or some ISP

Top die: Photodiode

and transfer

gate

Bottom die:

Pixel

Xistors and addressing

Interface

connection

[16]


PERFORMANCEPERFORMANCE

• 15


COLOR BIS IMAGER

BackBack--illuminated 1.75 illuminated 1.75 µµµµµµµµm Color Picture m Color Picture [17]


PERFORMANCE IMPROVEMENT

2.5x increase in Sensitivity for 2.2 µµµµm pixel

Dark current & Full-well about the same

Angular response improves by 5x

Electrical cross-talk worse4 micron pixel

Median luminance = 3 lux

Median luminance = 690 lux for D65

• 16


QUANTUM EFFICIENCY

• Surface Boron is an effective tool to improve QE

• Blue QE affected by boron content at the surface

• For color Imager: 20% loss going through CFA and OCL

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

400 500 600 700 800 900

Wavelength (nm)

QE

No B No AR

light B no AR

Medium B no AR

Medium B AR

[14]


WELL BEHAVED DARK CURRENT

1

10

100

1000

10000

100000

1000000

0 100 200 300 400 500 600 700 800 900

Dark Current (pA/cm^2)

Frequency

Front IlluminatedFront Illuminated Nitride coverNitride cover 53

Back surface Boron Nitride + H2 anneal Dark Current (e/sec)

Minimum None 8000

Small None 419

Small Yes 133

Medium Yes 57

High Yes 76

4 µµµµm @ 45C

[14]

• 17


ANGULAR RESPONSE

0

20

40

60

80

100

120

-30 -20 -10 0 10 20 30Degrees

Relative Response

Slight increase in relative angular response is due to optical path difference


BACK FIELD

Distance from back surface (a.u.)

Doping (a.u.)

Electric

Field (a

.u.)

N(x)

E(x) [V/cm]

• Simulated Nominal Back doping gradient and electric field

• Back-field drives minority carriers towards front

• Back-field suppresses Cross-talk

• Proper doping gradient is extremely important

dx

dN

N

1

q

kTE d

dx ⋅=

1

10

100

1000

N1 N2 N3 N4 N5 N6 N7

Doping (cm^-3)

Dark rate (a.u.)

0

0.5

1

1.5

2

2.5

XT and QE (%

) relativ

e

DR

QE

XT

Doping Trade-offs

• 18


RTS NOISE REDUCTION

1E+0

1E+1

1E+2

1E+3

1E+4

0 10 20 30 40 50 60Noise (electrons)

Counts

L=0.8 um

L=0.3 um

• Source follower as the main source of RTS

• Both modal noise and noise spread is reduced by length increase

CSH = 1.5 pF; Gcp ~ 45 µµµµV/e; Ibias = 3 µµµµA

ΦΦΦΦΦΦΦΦrstrst

VDDVDD COL

PD

Mrst

Msf

Msel

ΦΦΦΦΦΦΦΦsampsamp

ΦΦΦΦΦΦΦΦselsel

VVLNLN CCSHSH

CCss(Cd)

Mln

ΦΦΦΦΦΦΦΦrstrst

VDDVDD COL

PD

Mrst

Msf

Msel

ΦΦΦΦΦΦΦΦsampsamp

ΦΦΦΦΦΦΦΦselsel

VVLNLN CCSHSH

CCss(Cd)

Mln


MANUFACTURABILITYMANUFACTURABILITY

ISSUESISSUES

• 19


SUPPORT WAFER BONDING

Acoustic micrograph of low-temperature oxide-oxide bondedsupport wafer (courtesy Ziptronix, Inc.): No voids

Passes die-level thermo-mechanical tests (thermal shocks andtemperature cycles)

Alternate schemes?[17]


“PEEL OFF”

Sawing Process optimization toprevent delamination

DELAMINATIONDELAMINATION EDGE EXCLUSIONEDGE EXCLUSION

Optimization of bonding and grindingprocess to eliminate edge-crackingduring subsequent processing

• 20


THE THREE THINGS …

Back illumination

Front illumination

Back illumination

Front illumination

Back illumination

Front illumination

Electrical Cross-talk

•Separated generation and collection area

•Back surface field

•Deeper Junction

QE

•Integration of AR stack on the BOX

Dark Current

•Back surface passivation with integrated AR stack


AR STACK OPTIMIZATION

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

400 450 500 550 600 650 700

Wavelength (nm)

Transmission

H-L normal

H-L 30

L-L normal

L-L 30

•Excellent AR stack can be achieved with SiN/SiO layers

•Need to ensure that angular response is acceptable

•BOX not the ideal-choice for 1st AR layer

• 21


DARK CURRENT with AR STACK

BOX etching does not increase dark current, if done right!

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

10 100 1000Dark Count (LSB)

Frequency

BSI

Dry etch

Wet etch


1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75

1E15

1E16

1E17

1E18

Bo

ron

co

nc.(

/cm

3)

depth (um)

sinlge STI ox.

double STI ox.

RTO 1050C 30sec

1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75

1E15

1E16

1E17

1E18

Bo

ron

co

nc.(

/cm

3)

depth (um)

sinlge STI ox.

double STI ox.

RTO 1050C 30sec

CROSS-TALK

•Boron needed to passivate interface states

•Boron gradient needs to be optimized

•Boron segregation is the source of problems

•N-type substrate is preferable

Problem areaProblem area

Correct gradient: Correct gradient: sharper the bettersharper the better

Simulated Current flow

• 22


CROSS-TALK TRADE-OFF

• 20%

• Diode doping profile engineering for deeper field penetration

• Optimize silicon thickness

• “Clean-up” back surface: Boron segregation could be a problem

• Modify CFA?

• Modify microlens

• Optimize AR stack

0

5

10

15

20

25

30

35

40

45

50

400 450 500 550 600 650 700

Wavelength (um)

QE

B

G

R60%

0

10

20

30

40

50

60

70

400 450 500 550 600 650 700

Wavelength (um)

QE

B

G

R25%

0

10

20

30

40

50

60

70

80

90

400 450 500 550 600 650 700

Wavelength (um)

QE

B

G

R

10% Simulated


Cost Cost -- how low can you go?how low can you go?Special SOI wafer needed?Will SOI wafer become cheaper and have shorter turn-around time?Where are the yield and reliability “gotchas”?

PerformanceSOI wafer quality? Will lack of gettering be an issue?

Alternate Support Wafer AttachmentNeed for an alternative to LT-bonding? Alternate support materials?

Appropriate Optical StackWhat materials for AR stack? Alternate CFA?

Improving Cross-talkBoron segregation - N-type material?Alternate diode profiles and barrier implants? Deep trenches?Alternate dielectric for improved passivation? ITO?

PackagingChip-on-board (COB) or Chip-scale-packaging (CSP) or wafer scale (WSP)?

MOVING FORWARD (in lieu of conclusion)

• 23


REFERENCES

1. A. Rose, J. Soc. Motion Picture Engrs. 47 (1946) 273.

2. G. Zanella, R. Zannoni, “The role of the quantum efficiency on the DQE of an imaging detector”, Nuclear Instruments and

Methods in Physics Research A 381, 157-160, 1996.

3. Y-C Kim et al., “1/2 inch 7.2 Mega-Pixel CMOS Image Sensor with 2.25µm Pixels using 4-Shared Pixel Structure for Pixel-Level

Summation”, Proc. ISSCC 2006, paper 27.2, San Francisco, CA, USA, 2006.

4. J. Gambino et al. “CMOS Imager with Copper Wiring and Lightpipe,” Proc. IEEE IEDM, pp. 131-134, San Francisco, CA, USA,

2006.

5. S. Iwabuchi, et al, “A Back-Illuminated High-Sensitivity Small-Pixel Color CMOS Image Sensor with Flexible Layout of Metal

Wiring”, Proc. ISSCC 2006, paper 16.8, San Francisco, CA, USA, 2006.

6. B. Burke et al., “640x480 Back-Illuminated CCD Imager with Improved Blooming Control for Night Vision,” Proc. IEEE IEDM, pp.

33-36, San Francisco, CA, USA, 1998.

7. C. Huang et al., “A New Process for Thinned, Back-Illuminated CCD Image Devices,” Proc. IEEE VLSI Technology Systems and

Applications, pp. 98-101, Taipei, Taiwan, 1989.

8. S. Nikzad et al., “Delta-doped CCDs: High QE with long-term stability at 1W and visible wavelengths” Proc. SPIE 2198, pp. 907-

916, 1994.

9. J. Janesick, et al., "Flash Technology for Charge-Coupled Device Imaging in the Ultraviolet", Optical Engineering, vol. 26, pp

852-861, 1987.

10. B. Burke et al., “CCD Soft-X-Ray Detectors With Improved High- and Low-Energy Performance,” IEEE Trans. Nuclear Science,

vol. 51, pp. 2322-2327, vol. 51, 2004.

11. M. Lesser, “Improving CCD Quantum Efficiency,” Proc. SPIE 2198, pp. 782-791, 1994.

12. B. Pain, et al, “SOI-based Monolithic Imaging for Scientific Applications,” Proc. International Image Sensor Workshop 2007, pp.

192-195, Ogunquit, ME, USA, 2007.

13. B. Pain et al, “Wafer-Level Thinned CMOS Imagers Implemented in a Bulk-CMOS Technology,” Proc. International Image

Sensor Workshop 2007, pp. 158-161, Ogunquit, ME, USA, 2007.

14. B. Pain, “Fabrication and Initial Results for a Back-illuminated Monolithic APS in a mixed SOI/Bulk CMOS Technology”, Proc.

IEEE CCD/AIS Workshop, 2005, Nagano, Japan, 2005.

15. J. A. Burns et al., “A Wafer-Scale 3-D Circuit Integration Technology,” IEEE Trans. Elect. Dev., vol. 53, pp. 2507-2516, 2006.

16. V. Suntharalingam et al., “Megapixel CMOS Image Sensor Fabricated in Three-Dimensional Integrated Circuit Technology,”

Proc. ISSCC, pp. 356-357, San Francisco, CA, 2005.

17. T. Joy et al, “Development of Production-Ready, Back-Illuminated CMOS Image Sensor with Small Pixels,” Proc. IEEE IEDM,

pp. 1007-1010, Washington DC, USA, 2007.

18. J. Prima et al., “A 3 Mega-pixel Back-Illuminated Image Sensor with 1T5 Architecture with 1.45 µm Pixel Pitch,” Proc.

International Image Sensor Workshop 2007, pp. 5-8, Ogunquit, ME, USA, 2007.

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