av02-2211en an_5442 mga-17516 07apr2011,0.pdf
TRANSCRIPT
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
1/24
LNA Design with the MGA-17516
Matched Pair, Low Noise Amplier
Application Note 5442
Introduction
Most base stations (BTS) can transmit a signal to a mobile
device further and stronger than they can receive the
signals coming back from it. This is known as link imbalance
and is made worse by the feeder loss between the base
station and the antennas.[1]The low noise amplier (LNA)
in a communications system is the rst level of amplica-
tion of the incoming signal at the system antennas.
Lo noise amplies are found in almost all RF and micro-
wave receivers in commercial and military applications. In
commercial applications, LNA designs aim towards high
integration, low voltage and current bias. They are usually
placed at the front-end receiver system, immediately
following the antenna. An LNA must amplify extremely
low signals without adding noise, thus preserving required
system signal-to-noise ratio at extremely low power levels.
The complex signals in todays digital communication
systems also require an LNA designer to carefully consider
stability and noise gure per formance.
MGA-17516 base station applications
The MGA-17516 is an ideal choice for a wireless infrastruc-
ture base station application, particularly in the tower
mounted amplier (TMA), front end LNA, multi-carrier
power amplier (MCPA) and radio cards as illustrated by
the shaded triangles in the base station architecture in
Figure 1. In this application note, MGA-17516 application
circuits for the frequency band of 1.7 GHz to 2.0 GHz are
discussed in detail.
Figure 1. Typical base station architecture and MGA-175 16 applications
Balanced LNA
Tower MountedAmplifier/LNA
Diversity LNA
Main LNA
Multi-CarrierPA (MCPA)
Diversity LNA
Radio Cards
Main
Single-Ended (SE)
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
2/24
2
Table 1. Frequency Allocation in MHz
System Uplink (reverse) Downlink (forward)
CDMA 1900 18501910 19301990
WCDMA 19201980 21102170
GSM 1800e 17101785 18051880
GSM 1900 18501910 19301990
TDMA 1800 17101785 18051880
iDEN 806821 851866
Spectrum Allocation
With the complexity of the electromagnetic spectrum, it is
useful to review the major mobile station and base station
frequency allocations. Table 1 shows the bands suitable
for the MGA-17516.
The uplink is dened as transmission from mobile station (MS)
to base station (BTS), and the downlink is dened as transmis-
sion from base station to mobile station.
The MGA-17516 is an economical, identical pair, low noise,
GaAs MMIC amplier with a compact 16 mm2footprint
and 0.85 mm height. Its low noise, high gain and high
linearity are ideal for 1.7 GHz to 2 GHz band cellular in-
frastructure applications. The device can be used in both
single and balanced mode circuits.
MGA-17516 LNA Overview
MGA-17516 is housed in a miniature 4.0 x 4.0 x 0.85 mm,
16-pin Quad-Flat-Non-Lead (QFN) package.
The MGA-17516 is specied at Vdd = 5 V and biased at Vgg= 0.57 V, which will typically set drain current, Id, to 50 mA.
This bias condition delivers an exceptionally low noisegure of 0.52 dB, a high gain of 17.2 dB, an IIP3 of 13.7
dBm and a P1dBof about +21.5 dBm at 1.85 GHz.
Typical applications for the MGA-17516 are cellular base
station transceiver radio cards, tower mounted ampliers,
combiners, repeaters and remote/digital radio heads. The
footprint and pin congurations is shown in Figure 2.
Pin Usage Description
5 RFin 1 RF input or gate of FET 1
8 RFin 2 RF input or gate of FET 2
13 RFout 1 RF output or drain of FET 1
16 RFout 2 RF output or drain of FET 2
GND Ground Device ground
Others Not used Can be left unconnected
Figure 2. MGA-17516 footprint and pin conguration
EAXXXRE16AZZZZ
Pin
8
Pin
7
Pin
6
Pin
5
Pin13
Pin14
Pin15
Pin16
Pin 12
Pin 11Pin 10Pin 9
Pin 1
Pin 2Pin 3Pin 4
GND
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
3/24
3
Figure 3. MGA-17516 balanced amplier demonstration board
PCB structure
The MGA-17516 demonstration board is a three-layer
PCB with a 10-mil top layer and a 52-mil bottom layer.
The rst layer uses Rogers RO4350 material with a dielec-
tric constant of 3.48. The second layer, which is used for
mechanical rigidity, is FR4 with a dielectric constant of 4.2.
The metal layers use 0.5-oz. copper.
The unpopulated demonstration board is shown in Figure
3. The stacking structure of the PCB is illustrated in Figure
4. The total thickness of the board is 62 mils. SMA connec-
tors (EF Johnson 142-0701-851) can be attached at the
board edges. DC pin headers are soldered at the top edge
of the top layer.
Figure 4. Stacking structure of the demonstration board PCB
Demonstration board modication for single-end operation
The demonstration board can also be used as a single-
ended application board by cutting off the coupler section
on both the right and left sides of the board. The SMA
connectors are then soldered at the input and output
transmission lines directly. As shown in Figure 5, a cut
approximately 6 mm in from each edge must be made to
remove the coupler sections.
Populated demonstration boards for single-ended and
balanced amplier congurations are shown in Figure 6
and 7 respectively. In Figure 6 note where the coupler PCB
area has been removed.
MGA-17516 Balanced Amplier Demonstration Board Design
Figure 5. Modication of the balanced amplier demonstration PCB for single-ended operation
Figure 6. MGA-17516 single-ended amplier demonstration board Figure 7. MGA-17516 balanced amplier demonstration board
1483.001 (mils)
936.013(mils)
~ 6 mm~ 6 mm
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
4/24
4
MGA-17516 DC Biasing Circuits and Design
Passive bias
Biasing the Avago MGA-17516 is accomplished by the
use of a voltage divider circuit that consists of R2 and
R3, as illustrated in Figure 8. The voltage for the divider
is derived from the drain voltage that provides a form of
voltage feedback to help keep drain current constant. The
purpose of R1 is to enhance low frequency stability of the
device by providing a resistive termination at low frequen-
cies. Capacitor C5 provides a low frequency bypass for R1.
Capacitor C3 provides a high frequency bypass.
VgsR2 = Equation 1
IBB
(Vds Vgs) R2R3 = Equation 2
Vgs
Where:
IBB is the desired current owing through the R2/R3
voltage divider network.
Figure 8. Single-ended MGA-17516 amplier with a passive bias circuit
Here is a simple example based on choosing an IBBof 0.44
mA, a VDDof 5 V and a VDSof 5 V:
0.57 V
R2 = = 1.3 k 0.44 mA
(5.0 V 0.57 V) (1.3 k)R3 = = 10.1 k
0.57 V
With a Vgsof 0.57 V, drain current, Id, will be approximately
50 mA.
Figure 8 shows the complete passive bias schematic for
a low noise amplier design using the MGA-17516. The
repeatability of the biasing depends on device-to-device
variation of Vgs. For better bias setting repeatability, an
active bias circuit is recommended.
R6
L2
C2
R2
R3R5
C5
C6
L1
R1C3
C4
C1
RF Input RF Output
Vd=+5.0 V
+
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
5/24
5
Active bias
The main advantage of an active bias scheme is the ability
to hold the drain-to-source current constant with temper-
ature variations and device Vgs variation. A very inexpen-
sive method of accomplishing this uses two PNP bipolar
transistors arranged in a current mirror conguration, as
shown in Figure 9. Due to resistors Ra and Rc this circuitis not acting as a true current mirror, but if the voltage
drops across Ra and Rc are kept identical then the circuit
does display some of the more useful characteristics of a
current mirror.
For example, transistor Q1 is congured with its base and
collector tied together. This acts as a simple PN junction,
which helps temperature compensate the emitter-base
junction of Q2. To calculate the values of Ra, Rb, Rc, and Rd
the following parameters must be known or chosen rst:
1. Ids, the device drain-to-source current
2. IR, the reference current for active bias
3. Vdd, the power supply voltage
4. Vds, the device drain-to-source voltage
5. Vgg, the typical gate bias voltage
6. Vbe1, the typical base-emitter turn on voltage for Q1
and Q2
Resistor Rc, which sets the desired device drain current, is
calculated as follows:
Vdd VdsRc = Equation 3
Ids+ Ic2
Figure 9. MGA-17516 1.85 GHz LNA active bias circuit
For stability IC2is chosen to be ten times the typical gate
current. IC2 is also equal to the reference current, IR.
The next three equations are used to calculate the
remaining bias resistors.
Vdd VdsRa = Equation 4
IR
Note that the voltage drop across Ra must be set equal to
the voltage drop across Rc, but with a current of IR.
Vds Vbe1Rb = Equation 5
IR
Resistor Rb sets the bias current through Q1.
Vg
Rd = Equation 6 Ic2
Resistor Rd sets the MGA-17516 gate voltage.
By forcing the emitter voltage (VE) of transistor Q1 equal
to Vds, this circuit regulates the drain current much like
a current mirror. As long as Q2 operates in the forward
active mode, this holds true. In other words, the collector-
base junction of Q2 must be kept reverse biased.
Q1
Q2
Rb Ra
Rd Rc
C4
C3
C6
C5R1 R3
R4
R5C1 C2
L1 L2
RF OutputRF Input
Vdd
+
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
6/24
6
Stability Analysis
Circuit stability is also one of the important parameters
in amplier design. Unless a circuit is actually oscillating
on the bench, it may be difficult to predict instabilities
without actually presenting various VSWR loads at various
phase angles to the amplier.
Unconditional stability means that with any load
presented to the input our output of device, the circuit
will not become unstable. Instabilities are usually caused
by three phenomena: internal feedback of the transis-
tor, external feedback around the transistor caused by
external circuit or an excess of gain at frequencies outside
of the band of operation[2]. S-parameter les (S2P) which
are available from http://www/avagotech.com will aid in
stability analysis. Calculating Rollett stability factor, K, and
generating stability circles are two methods made consid-
erably easier with software simulations. An amplier will
be unconditionally stable if the following necessary and
sufficient conditions are met:
1 S112 S222+ D2K = > 1,
2S12 S21
D< 1
When the K stability factor is greater than unity, the
circuit will be unconditionally stable for any combination
of source and load impedance. If K is less than unity, the
circuit is potentially unstable, and oscillation may occur
with a certain combination of source or load impedance
presented to the amplier.
The K stability plots only address the performance near
the desired operating frequency. It is still important to
analyze out-of-band performance in regards to abnormal
gain peaks, positive return loss and instability. A simu-
lation tool is of great help when trying to optimize an
amplier for stability.
An MGA-17516T stability factor plot made with ADS
software is shown in Figure 10. It is evident that the
stability of the MGA-17516 is good across the frequency
(f < 20 GHz). The instability at lower frequency (f < 1.5 GHz)
can be xed by the input matching and low frequency
bypass capacitors, which will be shown in the later part of
this application note.
Figure 10. MGA-17516 stability factor, K, over frequency
2 4 6 8 10 12 14 16 180 20
2
3
4
1
0
5
freq, GHz
StabilityFactor(K)
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
7/24
7
MGA-17516 Amplier Design Process
Design goals
The MGA-17516 operates as a normal FET requiring both
input and output matching as well as DC biasing, but
unlike a depletion mode transistor, the enhancement
mode FET requires a single positive power supply. This
means a positive voltage is placed on the drain and the
gate in order for the transistor to turn on.
In this paper, three designs will be covered:
1. Single-ended, low noise amplier with the best noise
gure
2. Single-ended amplier with the best input return Loss
3. Balanced low noise amplier with the best noise gure
A successful LNA design presents considerable challenges
due to simultaneous requirement for high gain, low noise
gure, good input and output matching and unconditional
stability across the frequency band.The primary goals for an RF amplier design are:
1. Low noise gure / Best return Loss
2. Adequate gain
3. Stability, K > 1
4. High linearity, relatively high IIP3 and P1dB at the
frequency of operation
5. DC bias
Design goals for two different types of amplier were
chosen for the MGA-17516, as shown in Table 2.
Table 2. MGA-17516 Amplier Design Goals
Parameter at 1.85 GHz Low Noise Amplier Best IRL Amplier
Gain 17-18 dB > 18 dB
Noise Figure, NF < 0.55 dB
Input 3rdOrder Intercept Point, IIP3 > 9 dBm
Output P1dBCompression, OP1dB
Input return loss, IRL >10 dB
Output return loss, ORL >10 dB
Supply current, Vdd/ Idd 5 V / 50 mA 5 V / 50 mA
Frequency 1.85 GHz 1.85 GHz
Linear analysis and CPWG transmission line design
For a linear analysis of the amplier circuit shown in Figure
9, the transistor can be represented with two-port S-pa-
rameters using the Touchstone format. The S2P le can
be downloaded from Avago Technologies wireless design
center web site, http://www.avagotechwireless.com. The
circuit components can then be added to the simula-
tion circuit. The more detailed the simulation, the more
accurate the results will be. An accurate circuit simulation
is the rst step in a successful amplier design.
Proper transmission line design is important for a success-
ful amplier design. In this design, all microstrip sections
use a 10-mil thick PCB layer of RO4350 dielectric material.
The board has a coplanar waveguide (CPWG) transmission
line with a characteristic impedance of 50 at the 1.85
GHz design frequency. With the free AppCAD simulation
software available from Avago (http://www/avagotech.
com/docs/6001), the CPWG dimensions are easilycalculated. The AppCAD CPWG design screen is shown in
Figure 11.
Figure 11. CPWG design using the Avago AppCAD software
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
8/24
8
Low Noise Amplier Design for Best NF
Noise circle and gain circle analysis
In order to minimize the amplier noise gure, the input
matching circuit of this demonstration board amplier is
tuned to present optto the input of the MGA-17516. In
the ADS simulation, microstrip transmission lines are used
in place of CPWG lines. Microstrip and CPWG lines are
very similar in terms of length and dimension; therefore,
microstrip lines are used to ease the simulation process.
Figure 12 shows the complete simulation circuit model of
the MGA-17516 and microstrip transmission lines.
Figure 13 shows the location of opt, the noise circle and
the gain circle for the MGA-17516. Noise circles refer to
the contours of constant noise gure for a two-port when
plotted in the complex plane of the input admittance of
the two-port. The minimum noise gure is presented by
a dot, while for any given noise gure higher than the
minimum, a circle can be drawn[2]. Gain circles also refer
to the contours of constant gain for a two-port when
plotted in the complex plane of the input admittance of
the two-port. The maximum gain is presented by a dot,
while any given gain which is lower than the maximum
gain is drawn as a circle.
Figure 12. ADS schematic simulation setup
VIA GND
V3
VIA GND
V4
MLIN
TL3
Term
Term1
Z=50 OhmNum=1
MLIN
TL1
GRM18C9
Part Number=GRM1885C 2A150JA01
MLIN
TL2
R
R1R=15 Ohm
MLIN
TL21
MLINTL24
MLIN
TL16
MLINTL20
MLINTL22
CC I_0603CSSNP2
GRM15C7
Part Number=GRM155L81E 103KA 01
GRM18C11
Part Number=GRM1885C 1H300JA01
VIA GND
V2
VIA GND
V1
MCORN
Corn1
MTEE_ADSTee2
MTEE_ADSTee1
MLIN
TL7 TermTerm2
Z=50 Ohm
Num=2
MLIN
TL13
GRM18
C10
Part Number=GRM1885C1 H3R3C Z01
MLIN
TL15
R
R7
R=120 Ohm
MTEE_ADSTee6
MLINTL9
MTEE_ADSTee5
GRM18C12
Part Number=GRM1885C 2A100JA01
GRM15C8
Part Number=GRM155L81E 103KA 01
LQG18
L9
Part Number=LQG 18HN1 5NJ00
MLINTL23
MCORN
Corn2
MLINTL18
MLINTL17
MLINTL25
MLIN
TL19
R
R3R=6.8 Ohm
MLIN
TL8
R
R4R=0 Ohm
S2P
SNP1File="C:\users\2008_Folder\Rapala_E_prj\data\Data_Form_RnD\Jan_12\MGA_16516_5V 52mA_09112.S2P"
21Ref
MLIN
TL14
TDK_ML_DK_Include
TDK_ML_DK_Include
N E T L I S T I N C L U D E
MSUB
MSub1
Rough=0 mil
TanD=0
T=1.4 mil
Hu=3.9e + 03 4 mil
Cond=1.0E + 50
Mur=1
Er=3.48
H=10 mil
M S u b
MURATA Include
muRata
m u R a t a
S_Param
SP1
Step=50 MHz
Stop=20 GHz
Start=50 MHz
S - P A R A M E T E R S
Options
Options1
Max Warnings=10
Give AII Warnings=yes
I_AbsTol=
I_RelTol=
V_AbsTol=
V_RelTol=
Tnom=25
Temp=25
O P T I O N S
Mu
Mu1
Mu1=mu (S)
Mu
MuPrime
MuPrime1
MuPrime=mu_prime (S)
MuPrime
Stab Fact
Stab Fact1
Stab Fact1=stab_fact (S)
Stab Fact
S_Stab Circle
S_Stab Cicle 1
S_Stable Circle 1=1_stab_circle (S, 51)
SStab Circle
L_Stab Circle
L_Stab Cicle 1
L_Stable Circle 1=1_stab_circle (S, 51)
LStab Circle
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
9/24
9
Figure 13. Positions of OPT, noise circles, and gain circles at 1.85 GHz
Matching for Best NF
The input impedance matching movement towards opt is clearly shown in Figure 14. From the chart, a shunt inductor
and a series capacitor are needed to transform the 50 port to a point closer to opt. In real circuits with practical
inductors, the effects of the microstrip line that connects the inductor and the input pin of the device must be taken into
consideration when designing the input matching network.
Figure 14. Input matching for the Fmin point
GAcircles
Noise_
circles
Noise_
circleMin
conj_S11
S11*
Gain Circle { 19, 20, 21 } dB
NF Circle { 0.52, 0.62, 0.72 } dB
OPT
Noise_
circles
Noise_
circleMin
Series Capacitor (C1)
Shunt Inductor (L1)
OPT
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
10/24
10
Bill of material: Single-ended amplier
Each FET amplier is biased at a Vdsof 5 V and an Id of 50 mA. Typical Vgs is 0.57 V. The complete populated singled ended
amplier is shown in Figure 6. Component placement is shown in Figure 15, and the bill of materials is shown in Table 3.
The complete single-ended amplier schematic is shown in Figure 16.
Figure 15. Component placement for the single-ended amplier demonstration board
Table 3. Component Part List for the MGA-17516 Single-ended Amplier
Components Value Type Size PurposeC1 1000 pF Murata 0402 DC block and input matching
C2 1000 pF Murata 0402 DC block and output matching
C3 4.7 F Murata 0402 Bypass capacitor
C5 4.7 F Murata 0402 Bypass capacitor
C4, C6 9 nF Murata 0402 Low frequency bypass capacitor
L1 9 nH Coilcraft 0402 Input matching for low noise gure (High Q Factor)
L2 8.2 nH Toko 0402 Output matching
R1 15 Rohm 0402 Low frequency stability
R2 1.3 k Rohm 0402 Voltage divider for biasing
R3 10 k Rohm 0402 Voltage divider for biasing
R4 0 Rohm 0402 Jumper
R5 9.1 Rohm 0402 Low frequency stability
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
11/24
11
Figure 16. Single-ended, LNA design schematic
Measured performance: Single-ended LNA
The measured noise gure and gain of the completed amplier are shown in Figures 17 and 18. Noise gure is less than
0.55 dB from 1.7 GHz to 2 GHz. Gain is typically 16.9 dB at 1.85 GHz. The simulated noise gure was slightly better than the
measured noise gure of the circuit for in-band performance because of the secondary noise losses, such as connector
loss.
Figure 17. Single-ended LNA amplier: Measured and simulated noise gure
over frequency
Figure 18. Single-ended LNA amplier: Measured and simulated gain over
frequency
R4
L2
C2
R2
R3
R5C5
C6
L1
R1C3
C4
C1
Vd=+5.0V
RF Input RF Output
+
0.3
0.4
0.5
0.6
0.7
1500 1600 1700 1800 1900 2000 2100
Frequency (MHz)
N.F
igure(dB)
Measured NFSimulated NF
5
10
15
20
25
1500 1600 1700 1800 1900 2000 2100
Frequency (MHz)
Gain(dB)
Measured GainSimulated Gain
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
12/24
12
-15
-10
-5
0
1500 1600 1700 1800 1900 2000 2100
Frequency (MHz)
IRL(dB)
Measured IRLSimulated IRL
-25
-20
-15
-10
-5
0
1500 1600 1700 1800 1900 2000 2100
Frequency (MHz)
ORL(dB)
Measured ORLSimulated ORL
-60
-40
-20
0
1500 1600 1700 1800 1900 2000 2100
Frequency (MHz)
Isolation(dB)
Measured IsolationSimulated Isolation
0
1
2
3
4
5
0 5000 10000 15000 20000
Frequency (MHz)
Stability,
K
Measured Stability KSimulated Stability K
Measured input return loss and output return loss are shown in Figure 19 and Figure 20 respectively. The input return
loss at 1.85 GHz is 6.6 dB with a corresponding output return loss of 14.7 dB. From both gures, it is evident that both
simulated and measured IRL and ORL graphs are very similar.
Figure 21 shows both measured and simulated isolation.
The stability factor, both simulated and measured, is shown in Figure 22. The simulated curve beyond 6 GHz is inaccurate
due to the limited maximum frequency performance of the SMT components used in the simulation setup.The amplier input intercept point (IIP3) was measured at a nominal +17.7 dBm at a DC Vdsbias of 5.0 V and an Iddof 50
mA, as shown in Figure 23. Output P1dB was measured at +20.5 dBm at 1.85 GHz, as shown Figure 24.
Figure 19. Single-ended LNA amplier: Measured and simulated IRL over
frequency
Figure 20. Single-ended LNA amplier: Measured and simulated ORL over
frequency
Figure 21. Single-ended LNA amplier: Measured and simulated isolation
over frequency
Figure 22. Single-ended LNA amplier: Measured and simulated stability
factor, K, over frequency
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
13/24
13
14
16
18
20
1700 1750 1800 1850 1900 1950 2000
Frequency (MHz)
IIP
3(dBm)
Measured IIP3
18
20
22
24
1700 1750 1800 1850 1900 1950 2000
Frequency (MHz)
OP1dB(dBm)
Measured OP1dB
Figure 23. Single-ended LNA amplier: Measured IIP3 over frequency
Figure 24. Single-ended LNA amplier: Measured OP1dB over frequency
Single-ended Amplier Designed for Best Return Loss
(conjugate match)
Gamma in (in) analysis
The MGA-17516 was designed for the best input return
loss by terminating the device input with a conjugate of
in
. The amplier was designed for a Vds
of 5 volts and an
Ids of 50 mA.
In conjugate matching, we make an assumption that the
in is equivalent to S11. According to Equation 7, if S12is
very small, then in approximately equals S11.
CSS12S21Cin= S11+ Equation 7
1 S22CL
As shown in Figure 13, optand S11* are far apart from
each other on the Smith Chart. As discussed in the
preceding design, the low NF design did not give optimum
input return loss. In applications where the amplier NF
is not the most important parameter, a simultaneousconjugate match can be implemented to yield maximum
possible gain.
Conjugate match for best return loss
A simultaneous conjugate match also gives a very good
return loss at both input and output ports. The movement
towards the input conjugate match point is shown in
Figure 25. Simulations using the s2p data show that a
shunt inductor of 6.2 nH and 20 pF series capacitor at the
input is needed to move the 50 impedance towards the
S11* point.
After the input is matched to the S11*, the same methodis used to match to the S22* point for optimum output
return loss performance. With the help of an ADS simula-
tion, a 33 nH shunt inductor and 30 pF series capacitor was
needed to match the output circuit. However, to achieve
the matching condition on the demonstration board, a
slight modication / tuning was needed.
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
14/24
14
Figure 25. Input matching for conjugate matching method
Bill of material: Conjugate match amplier
Each FET amplier is biased at a Vdsof 5 V and an Id of 50 mA. Typical Vgs is 0.57 V. The complete populated amplier is
shown in Figure 6. The component placements are identical with the low noise amplier design as shown in Figure 15.
The bill of materials is shown in Table 4. The complete schematic is shown in Figure 26.
Table 4. Component Part List for MGA-17516 (Conjugate Match Amplier)
Components Value Type Size Purpose
C1 20 pF Murata 0402 DC block and input matching
C2 33 pF Murata 0402 DC block and output matching
C3 10 pF Murata 0402 Bypass capacitor
C5 9 pF Murata 0402 Bypass capacitor
C4, C6 4.7 nF Murata 0402 Low frequency bypass capacitor
L1 3.6 nH Toko 0402 Input matching for best input RL
L2 39 nH Toko 0402 Output matching for best output RL
R1 12 Rohm 0402 Low frequency stability
R2 1.3 k Rohm 0402 Voltage divider for biasing
R3 10 k Rohm 0402 Voltage divider for biasing
R4 0 Rohm 0402
R5 120 Rohm 0402 Improve stability, K factor
R6 9.1 Rohm 0402 Low frequency stability
conj_S11
Shunt Inductor (L1)
Series Capacitor (C1)
Conjugate match point
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
15/24
15
-25
-20
-15
-10
-5
0
1500 1600 1700 1800 1900 2000 2100
Frequency (MHz)
IRL(dB)
Measured IRLSimulated IRL
-25
-20
-15
-10
-5
0
1500 1600 1700 1800 1900 2000 2100
Frequency (MHz)
ORL(dB)
Measured ORLSimulated ORL
10
15
20
25
1500 1600 1700 1800 1900 2000 2100
Frequency (MHz)
Gain(dB)
Measured GainSimulated Gain
-60
-40
-20
0
1500 1600 1700 1800 1900 2000 2100
Frequency (MHz)
Isolation
(dB)
Measured IsolationSimulated Isolation
Figure 26. Schematic for single-ended, conjugate match amplier
Measured performance: Single-ended, conjugate matched LNA
The measured IRL and ORL for the conjugate matched LNA are shown in Figure 27 and Figure 28. Measured at 1.85 GHz,the IRL is 11 dB and the ORL is 13 dB.
As shown in Figure 29, the gain for the complete amplier is about 17.9 dB at 1.85 GHz. The isolation for the amplier is
more than 20 dB at 1.85 GHz, as shown in Figure 30.
Figure 27. Measured and simulated IRL for the conjugate matched LNA Figure 28. Measured and simulated ORL for the conjugate matched LNA
Figure 29. Measured and simulated gain for the conjugate matched LNA Figure 30. Measured and simulated isolation for the conjugate matched LNA
R4
L2
C2
R2
R3
R5C5
C6
L1
R1C3
C4
C1
RF Input RF Output
Vd=+5.0V
+
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
16/24
16
Measured Stability KSimulation Stability K
0
1
2
3
4
5
0 5000 10000 15000 20000
Frequency (MHz)
Stability,
K
0.4
0.6
0.8
1.0
1.2
1.4
1500 1600 1700 1800 1900 2000 2100
Frequency (MHz)
N.F
igure(dB)
Measured N.FigureSimulated N.Figure
12
13
14
15
16
1700 1750 1800 1850 1900 1950 2000
Frequency (MHz)
IIP3(dBm)
Measured IIP3
18
19
20
21
22
1700 1750 1800 1850 1900 1950 2000
Frequency (MHz)
OP1dB(dBm)
Measured OP1dB
Figure 31 shows the K stability factor for both simulated and measured performance across a 20 GHz frequency.
Figure 32 shows noise gure performance at 1.85 GHz is around 0.7 dB.
Figure 33 and Figure 34 show linearity measurements for the conjugate match amplier. Measured at 1.85 GHz, IIP3 is
around +14.4 dBm and OP1dB is around +21 dBm.
Figure 31. Measured and simulated stability factor, K, for the conjugate
matched LNA
Figure 32. Measured and simulated noise gure for the conjugate matched
LNA
Figure 33. Measured IIP3 for the conjugate matched LNA Figure 34. Measured P1dB for the conjugate matched LNA
Table 5 shows the comparison between the low noise amplier design and the conjugate matched amplier just
discussed. Measurements were made from 1.7 GHz to 2.0 GHz.
Table 5. Measured Parameters on LNA and Conjugate Matching Amplier
Parameter Low Noise Amplier Conjugate Matched AmplierFrequency GHz 1.7 1.8 1.9 2.0 1.7 1.8 1.9 2.0
Idd mA 50 50 50 50 50 50 50 50
Input RL dB 6.4 6.6 6.6 6.7 13.9 12.1 10.9 10
Output RL dB 13.6 14.2 15.1 16 10.3 12.1 14 16.1
Gain dB 17.7 17.1 16.7 16.2 18.7 18.1 17.7 17.3
N. Figure dB 0.5 0.52 0.54 0.56 0.79 0.72 0.63 0.6
IIP3 dBm 16.5 17.5 17.9 18.8 13.7 14.3 14.4 14.2
OP1dB dBm 20.6 20.6 20.5 20.7 20.7 20.9 21.1 21.3
K (Up to 20 GHz) > 1 > 1 > 1 > 1 > 1 > 1 > 1 > 1
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
17/24
17
Balanced Low Noise Amplier Design
Introduction to balanced ampliers
For cellular tower-mounted applications, a high intercept
point, 5 V supply operation and low current consumption
are required. Figure 35 shows the top level schematic of
the balanced LNA. The balanced topology has several
important features and advantages over the single-ended
amplier, such as:
1. Intercept point is 3 dB higher than a single stage
2. 50 input and output match
3. Redundancy which minimizes a hard failure
A balanced conguration ensures a good input and
output match and helps ensure stability. However, the
splitter/combiner network must be low loss, physically
small, and have good phase and amplitude matching
over the bandwidth of interest. Finally, the bandwidth
should be high enough to include the uplink frequencies
(mobile device to base station) for cellular standardsaround 1800 MHz.
Figure 35. Balanced amplier conguration
Splitter/Combiner selection
An important consideration for a balanced amplier is the
splitting and combining of RF signal. Power dividing and
power combining are generally accomplished by using
a power divider or a hybrid coupler. Power dividers and
hybrid couplers are passive microwave components that
can be printed on a substrate (in microstrip form) or can
be obtained in surface mount package.
When designing the splitter network for a balanced LNA, it
is important to minimize the insertion loss and return loss
while providing equal power to each of the two ampliers.
Although power dividers are used in balanced amplier
design, low loss hybrid couplers are proven to be superior
for several reasons.
Hybrid couplers are four-port devices characterized
by good matching, isolation and a xed 90 phase shift
between the output ports. Two popular hybrids are thebranch-line and broadside-coupled hybrid. The bandwidth
of a branch-line hybrid is limited to 10-20%, but a single
section broadside coupler can have bandwidth as large
as an octave. A broadside coupler also requires only half
the amount of line used in a branch line hybrid, and can
therefore be smaller in size. Reected power from each of
the two identical LNA inputs recombines at the isolated
port of the hybrid coupler and is dissipated in the resistive
termination.
This feature of the hybrid coupler allows Avago to design
each LNA for optimum noise gure performance, without
actually worrying about return loss from each of the two
LNAs. Usually, if a hybrid coupler is used on the input
side then an identical hybrid coupler can be used on the
output side to recombine the signals. Nevertheless, the
selection of the coupler is mainly due to the application
of the ampliers. Table 6 shows some guidelines to help
select the couplers.
In LNA applications, the insertion loss of the coupler at
the input port greatly inuences the overall NF of the
LNA. Thus, a low-insertion-loss coupler is necessary for a
LNA that has extremely good NF performance like MGA-
17516.
To demonstrate the MGA-17516 as a balanced LNA, theAnaren/Xinger XC1900L-03S surface mount coupler was
chosen for its low 0.20 dB maximum insertion loss and
tight amplitude performance.
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
18/24
18
Table 7. Anaren/Xinger XC-1900L-03S Hybrid Coupler
Specication
Test Parameter Specication
Bandwidth 1.7 2.0 GHz
Insertion loss 0.12 dB (max)
Isolation 23 dB (min)
VWSR 1.17 (max)
Amplitude balance 0.13 dB (max)
Phase 90 2.0
Power rating 120 W (CW) (average)
Dimension 650 x 480 x 69 mil
jc 36C/W
Operating temperature -55 C to +95 C
Figure 36. Balanced board terminated with 50 (size 0603) resistor Figure 37. Measured return loss of Anaren/Xinger XC-1900L-ES coupler on the
balanced amplier board
Table 6. Coupler Selection Guidelines
Applications Input Coupler Output Coupler
LNA Very good insertion loss Moderate insertion loss
Power amplier Moderate insertion loss Good power handling capability
RF amplier Moderate insertion loss Moderate insertion loss
To obtain the best performance from the hybrid coupler,
CPWG or microstrip lines must be designed carefully. A
good recommendation on the coupler PCB design can be
found at http://www.anaren.com. The balanced demon-
stration board was veried by measuring the return loss at
the SMA connector with both ends of the lines terminated
with 50 , as shown in Figure 36.
As shown in Figure 37, the balanced demonstration boardwith an Anaren XC-1900L-ES coupler had a measured
return loss of more than 15 dB at 1.85 GHz on both the
input and output ports.
-30
-25
-20
-15
-10
-5
0
0 500 1000 1500 2000 2500 3000
Frequency (MHz)
ReturnLoss(dB)
Coupler (Input Side)Coupler (Output Side)
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
19/24
19
Figure 38. Schematic for the balanced amplier design
Balanced amplier bill of material
As discussed previously, the single-ended amplier was designed for a Vdsof 5 V and an Ids of 50 mA. For a balanced
amplier, Idsmust be doubled to 100 mA. The populated board is shown in Figure 7. The schematic for the balanced
amplier board is shown in Figure 38. Component placement is shown in Figure 39, and the bill of materials is shown in
Table 8.
The board gives the designer several design options for the RF circuitry. The evaluation board was designed so that the
input and output impedance matching networks can be adjusted to optimize performance, particularly for noise gureover the 1.7 GHz to 2 GHz frequency range.
For a LNA RF layout, the main constraint is that the circuit must maintain a balanced conguration; the path lengths in
each arm of the amplier must be equal. The effect of uneven path lengths will result in out-of-phase summing of the
signals and lower output power and worse linearity than expected.
Figure 39. Component placement for the balanced amplier demonstration board
R4
L2
C2
R2
R3R5
C5
C6
L1
R1C3
C4
C1
Vd=+5.0 V
R10
L4
C8
R8
R9R11
C11
C12
L3
R7C9
C10
C7
Vd=+5.0 V
RF Output
R13
R14AnarenCoupler
RF Input
R11
R12
AnarenCoupler
+
+
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
20/24
20
Table 8. Component Part List for the MGA-17516 Balanced LNA Design
Components Value Type Size Purpose
C1, C7 1000 pF Murata 0402 DC block and input matching
C2, C8 1000 pF Murata 0402 DC block and output matching
C3, C9 9 pF Murata 0402 Bypass capacitor
C5, C11 9 pF Murata 0402 Bypass capacitor
C4, C6, C10, C12 4.7 nF Murata 0402 Low frequency bypass capacitor
L1, L3 9 nH Coilcraft 0402 Input matching for low noise gure (High Q Factor)
L2, L4 8.2 nH Toko 0402 Output matching
R1, R7 15 Rohm 0402 Low frequency stability
R2, R8 1.3 k Rohm 0402 Voltage divider for biasing
R3, R9 10 k Rohm 0402 Voltage divider for biasing
R4, R10 0 Rohm 0402 Low frequency stability (if needed)
R5, R11 9.1 Rohm 0402 Low frequency stability
Measured performance: Balanced amplier
As measured on the single-ended and balanced demonstration boards, MGA-17516 performance can be seen in the
following graphs. All these measurements included the loss from the SMA connectors, board traces and hybrid couplers
(for the balanced amplier). As shown in Figures 40 and 41, the input and output return losses of the balanced amplier
were far better than 20 dB over 1.7 GHz to 2 GHz.
Figure 40. Measured IRL for balanced and single-ended ampliers over
frequency
Figure 41. Measured ORL for balanced and single-ended ampliers over
frequency
-40
-30
-20
-10
0
1500 1600 1700 1800 1900 2000 2100
Frequency (MHz)
IRL(dB)
Balanced AmpSingle-Ended Amp
-40
-30
-20
-10
0
1500 1600 1700 1800 1900 2000 2100
Frequency (MHz)
ORL(dB)
Balanced AmpSingle-Ended Amp
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
21/24
21
14
16
18
20
1500 1600 1700 1800 1900 2000 2100
Frequency (MHz)
Gain(dB)
Balanced AmpSingle-Ended Amp
0.2
0.4
0.6
0.8
1
1500 1600 1700 1800 1900 2000
Frequency (MHz)
N.F
igure(dB)
-40
-30
-20
-10
1000 1500 2000 2500
Frequency (MHz)
Isolation(dB)
0
1
2
3
4
5
0 5000 10000 15000 20000
Frequency (MHz)
Stability,
K
Balanced AmpSingle-Ended Amp
Balanced AmpSingle-Ended Amp
Balanced AmpSingle-Ended Amp
The gain of the balanced amplier was very similar to the gain of the single-ended amplier, as shown in Figure 42.
The gain on the single-ended board was slightly higher than the gain of the balanced board. This was caused by the
insertion loss of the input and output couplers. The gain was more than 16.5 dB for both congurations at 1.85 GHz.
The noise gure performance for the single-ended amplier is around 0.10 dB better if compared to the balanced
amplier. This is due to the insertion loss of the input coupler on the balanced board. As shown in Figure 43, at 1.85 GHz
the noise gure for single-ended amplier is about 0.5 dB and for the balanced amplier it is about 0.6 dB.
The reverse isolation of the single-ended board and balanced ampliers, as shown in Figure 44, was more than 25 dB
between 1.5 GHz and 2.5GHz. The stability factor, K, for both balanced and single-ended LNA designs is shown in
Figure 45.
Figure 42. Measured gain for the balanced and single-ended ampliers over
frequency
Figure 43. Measured noise gure for the balanced and single-ended
ampliers over frequency
Figure 44. Measured isolation for balanced and single-ended ampliers over
frequency
Figure 45. Measured stability factor (K) for balanced and single-ended
ampliers over frequency
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
22/24
22
Measured wideband characteristics are shown in Figures 46 and 47 for both balanced and single-ended ampliers
respectively.
Figure 4 6. Wideband measurem ent: Balanced amplier Figure 4 7. Wideband measurement: S ingle- ended amplier
Table 9 summarizes MGA-17516 measured performance on both single-ended and balanced demonstration boards.
Measurements were made with a Vddof 5 V and Vgsof 0.57 V.
Table 9. Measured Performance Comparison
Parameter Single-ended Board Balanced Board
Frequency GHz 1.7 1.8 1.9 2.0 1.7 1.8 1.9 2.0
Idd mA 50 50 50 50 100 100 100 100
Gain dB 17.7 17.1 16.7 16.6 17.5 17.0 16.5 16.5
Input RL dB 6.4 6.5 6.6 6.7 22.8 20.4 18.8 18.5
Output RL dB 13.5 14.3 15.1 16 28.3 24.3 21.7 20.8
NF dB 0.5 0.52 0.54 0.55 0.6 0.63 0.64 0.64
P1dB dBm 20.6 20.6 20.5 20.7 23.6 23.7 23.6 23.5
IIP3 dBm 16.5 17.5 17.9 18.9 18 18.6 19 19.4
Gain
IRLORL
-80
-40
0
40
0 1000 2000 3000 4000 5000 6000
Frequency (MHz)
Gain,
IRL,
ORL,
Isolation(dB)
-80
-40
0
40
0 1000 2000 3000 4000 5000 6000
Frequency (MHz)
Gain,
IRL,
ORL,
Isolation(
dB)
Isolation
Gain
IRL
ORL
Isolation
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
23/24
23
MGA-17516 channel isolation
The isolation was measured with both channels being powered as shown in Figure 48. The isolation is dened by the
difference of two measurements using a two-port network analyzer.
To illustrate, the rst measurement was made between input and output of the top channel and is called S21. The
second measurement was between the input of the top channel and the output of the bottom channel and is called S41.
During this second measurement, all unused ports must be terminated with 50 to ensure accuracy.
Figure 48. Test setup for isolation between top and bottom channels
The isolation is calculated by subtracting S4, denoted by
the dashed line in Figure 48, from S21, denoted by the
solid line in Figure 48.
The dashed line is the isolation from the bottom channel
to the top channel. As measured on the single-ended
board, MGA-17516 isolation was -37 dB at 1.85 GHz.
Figure 49. Isolation between the MGA-17516 top and bottom channels
In1
In2
S21
S41
Out1
Out2
Vgs= 0.57 V Vdd= 5.0 V
Vgs= 0.57 V Vdd= 5.0 V
-60
-50
-40
-30
-20
1500 1700 1900 2100 2300 2500
Frequency (MHz)
Isolation(dB)
Top Channel IsolationBottom Channel Isolation
-
8/13/2019 AV02-2211EN AN_5442 MGA-17516 07Apr2011,0.pdf
24/24
For product information and a complete list of distributors, please go to our web s ite: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright 2005-2011 Avago Technologies. All rights reserved.
Summary and Conclusion
The Avago Technologies MGA-17516 LNA offers a very
high performance, power efficient and cost effective
solution for low noise amplier designs.
This application note has described two types of designs:
a 1.85GHz LNA design and a 1.85GHz conjugate matchedamplier design. RF designers can design an MGA-17516
based amplier optimized for noise gure or as a conjugate
matched amplier.
Avago sales offices offer demonstration boards, and
AppCAD simulation software is available from the web at
http://www.avagotech.com/docs/6001. S2P parameters
(MGA-17516 S2P) can be downloaded from: the www.
avagotechwireless.com also.
References
1. Design of Class-E Radio Frequency Power Amplier
Al-Shahrani, Saad Mohammed
2. RF and Microwave Handbook Mike Golio (CRC Press)
3. Applications Note AN-1222: A Low Noise High Intercept
Point Amplier for 1930 to 1990 MHz using theATF-54143 PHEMT A.J. Ward
4. Application Note AN-1320: Low Noise and High
Linearity Applications using the Avago ATF-531P8
Saul Espino
5. Application Note AN-1281: A High IIP3 Balanced Low
Noise Amplier for Cellular Base Station Applications
Using Enhancement Mode PHEMT ATF-54143 Transistor
and Anaren Pico Xinger 3 dB Hybrid Couplers