ARAB ACADEMY FOR ScIENCE, TEcHNoLOGY AND MARITIME TRANSPORT

College of Engineering and Technology- Cairo

Design and implementation of soft Decision Low Density Parity check decoder (LDPC) on Field Programmable Gate Array (FPGA)

by

Eng. Sherry Heshmat Hareth Korisa

A dissertation submitted to AASTMT in partial

fulfillment ofthe requirements for the award of the degree of

MASTER of SCIENCE

In

Electronics and Communications Engineering

Supervisor Supervisor Prof. Dr. Khaled A. Shehata Dr. Banady Bussien

~~J--~fX\

Supervisor

-:~:.~ Examiner

Prof. Dr. Abd EI Hamid Gafar

_____ ~ 1 ~

l

Examiner Prof. Dr. Bassan EI Ghitany

______ ~J_~-----------~----

Abstract

The Low-Density Parity-Check (LDPe) codes are among the most powerful forward

error correcting codes. LDPC codes enable performance close to the Shannon limit.

This advantage combined with their relatively simple decoding algorithm makes these

codes very attractive for the second digital transmission system generations. It is al­

ready the case for the next digital satellite broadcasting standard (DVB-S2).

Thesis proposes two different LDPC algorithms named Log-BP and MS. Both of them

are software implemented using Matlab m-files. They are analysed to compare be­

tween their performance. The analysis is performed on two different channels named

AWGN and Rayleigh fading channels. The choice for this channels to study the per­

formance of LDPC decoders in different emironments as AWGN channel is considered

to be an ideal while the Rayleigh fading channel considered to be practical channel

in daily environment.

The MS LDPC decoder is fully parallel implemented on LabVIEW which is a semi

Hardware simulation tooL Afterwards using the same MS LDPC decoder but using

partially parallel architecture implemented on VHDL hardware simulation tooL The

used EDA tools is Mentor Graphics FPGA adv. prog.8.2. The partial parallel archi­

tecture is used to enhance the performance of the design while saving hardware area.

It is a compromise between speed and area performance. The implemented decoder

results are verified by a successful comparison with the simulated one. The decoder

ii

is then synthesized proving hardware realization.

iii

Acknowledgements

I am grateful to my parents, sister and my husband for always being there for me and

for being the cause for everything, I have accomplished until this day. All my success

is the answer for there prayers.

My deepest appreciation goes to my supervisors Prof. Khaled Shehata, Dr. Hanady

Hussein and Dr. Mohamed Kheder. I would like to thank them all for their continuous

guidance, support and active contribution in refining my research work.

iv

List of Abbreviations

ARR

ASIC

AWGN

BEC

BER

BN

BP

BSC

CDMA

CN

CRC

DMC

DTH

DVB-S2

EDA

FEC

FPGA

lID

lIDTV

Automatic Repeat Request

Application Specific Integrated Circuit

Additive White Gaussian Noise

Binary Erasure Channel

Bit Error Rate

Bit Nodes

Belief Propagation

Binary Symmetrical. Channel

Code Division Multiple Access

Check Nodes

Cyclic Redundancy Checks

Discrete Memoryless Channel

Direct-To-Home

Digital Video Broadcasting second generation

Electronic Design Automation tools

Forward error-correction

Field Programmable Gate Array

Hard Decision

High Definition Television

v

HW

IRDS

LDPC

LLR

Log-BP

LabVIEW

MFSK

ML

MPA

MS

QC-LDPC

SDTV

SNR

VHDL

WiMAX

Hardware

Integrated receivers jDecoders

Low Density Parity Check

Log-likelihood ratio

Log Belief Propagation

Laboratory Virtual Instrument Engineering Workbench

M-ary Frequency Shift Keying

Maximum Likelihood Ratio

Message Passing Algorithm

Minimum sum product

Quasi-Cyclic Low Density Parity Check

Standard Detention Television

Signal to Noise Ratio

Very High Speed Integrated Circuit Hardware Descriptive Language

Worldwide Interoperability for fvlicrowave Access

vi

Table of Contents

Abstract

Acknowledgments

List

Table of Contents

List of Figures

List of Tables

1 Communication Systems

1.1 Introduction....

1.2 Problem Definition

1.3 Thesis Outline. . .

2 Forward Error Correction codes

2.1 Digital Communication System

2.2 Standard channel models .....

2.2.1 Binary Erasure Channel (BEC)

2.2.2 Binary Symmetrical Channel (BSC) . .

vii

ii

iv

v

x

xiv

xv

1

1

2

3

4

4

5

5

6

2.2.3 Additive White Gaussian Noise (AWGN) channel

2.2.4 Fading Channel ........ .

2.2.4.1 Flat Fading channels .

2.2.4.2 Fast Rayleigh Fading channel

7

7

8

8

2.3 Types of Errors . . . . . . . . . . . . . . . 9

2.4 Claude Elwood Shannon capacity theorem 10

2.5 Channel coding . . . . . . 12

2.5.1 Waveform Coding. 12

2.5.2 Structured Sequence Technique 15

3 Low Density Parity Check (LOP C) Codes 20

3.1 Introduction on LDPC codes. 20

3.2 LDPC Encoder . . . . . . . . 22

3.3 Graphical representation of LDPC . 25

3.4 Construction of LDPC codes . . 26

3.5 LDPC Decoding Algorithms . . 29

3.5.1 Bit-flipping decoding Algorithm 30

3.5.2 Sum Product Decoding (SPD) . 31

3.5.3 Minimum Sum (MS) LDPC . . 32

4 Proposed LDPC Decoders Evaluation Performance 34

4.1 DVB-S2 LDPC Decoder . . . . . . . . . . . . . . . . . . . . . . 34

4.2 Performance analysis of LDPC decoder for DYE-S2 application 36

4.2.1 Performance analysis of LDPC decoder with AWGN channel 37

4.2.2 Performance analysis of LDPC decoder with Rayleigh fading

channel .............................. 38

viii

4.2.3 Comparing between the performance of Log-BP on AWGN chan-

nel and Rayleigh fading channel ................ 39

4.3 Performance Evaluation for both Log-BP LDPC and MS LDPC decoders 40

4.4 WiMAX Low Density Parity Check Codes . . . . . . . . . . 43

4.4.1 Properties of Mobile WiMAX IEE802.16e 44

4.4.2 Design of WiMAX Parity Check Matrix . 44

4.4.3 Performances of the (288,576) regular (3, 6) quasi-cyclic LDPC

codes on AWGN channel

4.5 LabVIEW Implementation of (3,6) regular QC LDPC for WiMAX Ap-

plication ...................... .

4.5.1 Overall architecture of an LDPC decoder.

4.5.2 Bit Node Unit . .

4.5.3 Check Node Unit

5 FPGA Implementation of MS QC LDPC For WiMAX

5.1 Introduction.................

5.2 Hardware architecture MS LDPC decoder

5.2.1 Control Unit ....

5.2.2 Channel Registers .

5.2.3 Bit Node Unit . . .

5.2.4 Bit Node to Check Node Registers

5.2.5 Check Node Unit . . .

5.2.6 Check Node Registers

5.2.7 Check Node to Bit Node connection.

5.2.8 Hard Decision Block

5.3 System Integration . . .

5.3.1 Synthesis Results

ix

46

47

47

48

51

54

54

56

58

61

63

65

67

70

72

73

77

78

5.3.2 Post Routing simulation .

5.3.3 Comments on the Results

6 Conclusions and Future Work

6.1 Conclusions .

6.2 Future Work.

LIST OF PUBLICATIONS

x

79

80

81

81

82

83

List of Figures

2.1 Digital communication system model

2.2 The Binary Erasure Channel. .

2.3 The Binary Symmetric Channel

2.4 Additive white Gaussian Noise.

2.5 Flat Fading case when (fo > W) .

2.6 Normalized channel capacity VS. channel SNR .

2.7 Channel coding techniques of FEC .

2.8 Antipodal code vector representation

2.9 Antipodal wave form representation of S1 (t)

2.10 Antipodal wave form representation of S2(t)

2.11 Orthogonal wave form representation S1 (t)

2.12 Orthogonal wave form representation S2(t)

2.13 Orthogonal code vector representation

2.14 (N,k) block code ..

2.15 convolution encoder.

2.16 soft input/soft output decoder for a systematic code

3.1 linear time encoding (approximate lower triangular form) for LDPC

codes ............ .

3.2 Tanner graph representation

xi

4

6

6

7

8

11

13

13

13

13

15

15

15

16

18

18

23

25

3.3 Parity Check Matrix construction summary

3.4 Identity matrix with right shift with p steps

27

29

3.5 Tanner graph showing message passing from BN to CN . . . . . . 30

3.6 Tanner graph showing message passing from CN to BN .

3.7 ¢(x) = -log(tanh(~)) function ............. .

4.1 Matlab implementation architecture. . . .

4.2 BER Vs Eb/No for DVE-S2 (N=64800) with different rates on AWGN

30

33

37

channel using Log-BP LDPC decoder . . . . . . . . . . . . . . . . .. 38

4.3 BER Vs Eb/No for DYE-S2 (N=64800) with different rates on AWGN

channel using Log-BP LDPC decoder. . . . . . . . . . . . . . . . .. 38

4.4 BER Vs Eb/No for DVE-S2 (N=64800) with different rates on Rayleigh

Fading channel using Log-BP LDPC decoder. . . . . . . . . . . . .. 39

4.5 BER Vs Eb/No for DYE-S2 (N=64800) for different rates on both chan-

nels Rayleigh channel and AWGN channel using Log-BP LDPC decoder 40

4.6 BER Vs Eb/No for DYE-S2 (4050,8100) comparing between Log-BP

LDPC and MS LDPC decoding. . . . . . . . . . . . . . . . . . . .. 41

4.7 BER Vs Eb/No for DVB-S2 (4050,8100) of MS LDPC on AWGN and

Rayleigh channel . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 42

4.8 BER Vs Eb/No for DYE-S2 (8100,4050) MS LDPC decoding Vvith dif-

ferent iterations

4.9 BER Vs Eb/No for DYE-S2 (8100,4050) of MS and Log-Bp LDPC on

AWGN and Rayleigh fading channel with number of iteration equal to

2 and 25

42

43

4.10 (288,576) parity check matrix of a regular (3,6) quasi-cyclic LDPC code 45

4.11 BER vs. Eb/No of (288,576) regular (3, 6) quasi-cyclic LDPC codes

over AWGN channel .. . . . 46

xii

4.12 Overall Lab VIEW architecture. . . . . . . . . . . . . . . 48

4.13 Architecture of (3,6 QC LDPC decoder using LabVIEW) 49

4.14 Bit Node unit in Labview 49

4.15 Bit Node unit in Labview 50

4.16 Bit Node unit output from Labview . 50

4.17 Bit Node unit output from Matlab 50

4.18 CN unit in Labview. . . . . . . . . 51

4.19 CN unit inner structure in Labview 52

4.20 CN unit from Labview 53

4.21 CN unit from matlab . 53

5.1 Quantized data for VHDL decoder implementation 56

5.2 LDPC Block Diagram ................ 57

5.3 Quasi-cyclic Parity check matrix for partially parallel implementation 58

5.4 control unit flow chart . . . . . . . . . . . . . 59

5.5 System control unit on Mentor Graphics tools 60

5.6 Control Unit simulation result . . . . . . . . . 60

5.7 Control Unit simulation result sho~ing the stopping condition 61

5.8 Channel Registers inner structure block diagram. . . . . . . 62

5.9 Channel Register Block Diagram on Mentor Graphics tools. 62

5.10 Channel Registers simulation result 63

5.11 Bit Node unit block diagram . . . . 64

5.12 Bit Node unit on Mentor Graphics tools 64

5.13 Inner structure of Bit Node unit on Mentor Graphics tools 65

5.14 Bit Node unite inner structure . 66

5.15 BN unit simulation result ... 66

5.16 Bit Node to Check Node Data Register block diagram. 67

xiii

5.17 Bit Node to Check Node Data Register on Mentor Graphics tools 67

5.18 BN to CN register simulation result . 68

5.19 CN unit on Mentor Graphics tools . 68

5.20 CN unit lower integrated blocks using Mentor Graphics tools. 69

5.21 Inner structure for implementing {3ji in CN equation. 70

5.22 CN unit simulation result ...... 71

5.23 Check Node Register block diagram. 71

5.24 Check Node Register block on Mentor Garlics tools 72

5.25 Simulation result of CN Register block 72

5.26 CN to BN connection block Diagram . 73

5.27 CN to BN connection block diagram using Mentor Graphics tools 73

5.28 Hard Decision block Diagram .. . . . . . . . . . . . . . . . . . . 74

5.29 Comparator of the first Hard Decision block diagram on Mentor Graph-

ics tools . . . . . . . . . . . . . . . . . . . . . 74

5.30 Simulation result of the HD comparator block 75

5.31 Hard Decision Register Block diagram using Mentor Graphics tools 75

5.32 Hard Decision Register simulation result 76

5.33 Syndrome step one block Diagram ... 77

5.34 Top level of system Integration on Mentor Graphics tools . 77

5.35 Hardware output codeword on Mentor Graphics tools compared with

Matlab and Lab VIEW output codeword for system verification . 78

5.36 timing simulation for control unit 79

5.37 timing simulation for BN unit 80

5.38 timing simulation for CN unit 80

xiv

List of Tables

3.1 Comparison between Structure and Random or Pseudo Random LDPC

codes ................ . 27

4.1 Comparison among DVB standers . . . . . . . . . . . . . . 35

4.2 FEC Rates applicable to Various Modulation Formats [32] 36

4.3 WiMaX services [44] . . . . . . . . . ............ 44

5.1 Different implementation designs .. 55

5.2 Device Utilization for EP4CGX150DF31C 79

xv

LIST OF PUBLICATIONS

Hanady Hussien, khaled Ali Shehata, Mohamed Khedr, Sherry Hareth,"Pedormance

study on implementation of DVB-S2 Low Density Parity Check Codes on Additive

White Gaussian Noise channel and Rayleigh fading channel," IEEE International

Conference on Electronics Design, Systems and Applications (ICED SA) , pp.179 -

182,2012.

83

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Abstract

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