application of local common mode feedback techniques cmos...
TRANSCRIPT
APPLICATION OF LOCAL COMMON MODE FEEDBACK TECHNIQUES
TO ENHANCE SLEW RATE AND GAIN-BANDWIDTH OF
CMOS OPERATIONAL AMPLIFIERS
BY MICHAEL LEIGH HOLMES, BSEE
A thesis submitted to the Graduate School in partial fulfillment of the requirements for the degree Master of Science
Major Subject: Electrical Engineering New Mexico State University Las Cruces, New Mexico December 2002
"Application of Local Common Mode Feedback Techniques to Enhance Slew Rate and Gain-Bandwidth of CMOS Operational Amplifiers," a thesis prepared by Michael
Leigh Holmes in partial fulfillment of the requirements for the degree, Master of
Science in Electrical Engineering, has been approved and accepted by the following:
Linda Lacey Dean of the Graduate School
Jaime Ramirez-Angulo Chair of the Examining Committee Date Committee in charge:
Dr. Jaime Ramirez-Angulo, Chair
Dr. Paul M. Furth Dr. Stuart H. Munson-McGee
ii
ACKNOWLEDGEMENTS
First, I have to thank my advisor, Dr. Jaime Ramirez-Angulo, for recognizing
my commitment as an undergraduate and honoring me with this graduate position and
research assistantship; for his guidance, support, and patience, in mentoring me
towards the completion of this research and the largest project of my life. His work
ethic, humor, and emphasis on the little things in life, will not be forgotten.
Second, acknowledgment of the support and commitment I have received
from Dr. Paul Furth throughout the duration of my educational experience. His
dedication to family and his students is a source of admiration.
To my dad, who pushes me to succeed through his interest in my work. My
mom, who, through her determination for me to succeed, has been a source of
financial support, real world ethics, and hard nosed encouragement.
To my loving wife, Brooke, for her constant drive, encouragement, and
optimism, which is in constant harmony with my pessimistic nature; for taking care of
me and pushing me when the walls seemed too high to scale.
To my friends, who won’t let me take “no” for an answer and insist that I push
on to make my mark. To the friends I have made in the research lab, which have
been there on the good and bad days and have pushed me to succeed.
To anyone who contributed directly or indirectly to the completion of this
thesis, and my committee members for taking the time to help me finish.
iii
VITA
May 6, 1978 Born in Great Bend, Kansas 1996 Graduated, Farmington High School, Farmington, New
Mexico 1999 CO-OP NASA, Johnson Space Center, Houston, Texas 2000 Graduated, B.S.E.E, New Mexico State University, Las
Cruces, New Mexico 2000-2002 Research Assistant, Department of Electrical and
Computer Engineering, New Mexico State University PROFESSIONAL AND HONORARY SOCIETIES Institute of Electrical and Electronics Engineers (IEEE) PUBLICATIONS 1. J. Ramirez-Angulo and M. Holmes, “A Simple Technique to Significantly
Enhance Slew Rate and Bandwidth of One-Stage CMOS Operational Amplifiers.” Proceedings of the 2002 International Symposium on Circuits and Systems, Phoenix, Arizona, May 2002.
2. M. Holmes, J. Ramirez-Angulo, and R.G. Carvajal, “New Architectures of Class
AB CMOS and BICMOS Operational Amplifiers with Local Common Mode Feedback” Proceedings of the 2002 Midwest Symposium on Circuits and Systems, Tulsa, Oklahoma, August 2002.
3. J. Ramirez-Angulo and M. Holmes, “Simple Technique Using Local Common
Mode Feedback To Enhance Slew Rate and Bandwidth of One-Stage CMOS Op-Amps.” Electronics Letters, vol. 38 (19), (in print), October 2002.
FIELD OF STUDY Major Field: Electrical Engineering Mixed Signal Microelectronics
iv
ABSTRACT
APPLICATION OF LOCAL COMMON MODE FEEDBACK TECHNIQUES
TO ENHANCE SLEW RATE AND GAIN-BANDWIDTH
CMOS OPERATIONAL AMPLIFIERS
BY
MICHAEL LEIGH HOLMES, STUDENT, B.S.
Master of Science, Electrical Engineering
New Mexico State University
Las Cruces, New Mexico, 2002
Dr. Jaime Ramirez-Angulo, Chair
Industry is continuously researching techniques to reduce power requirements,
while increasing speed, to meet the demands of today’s low (battery) powered
wireless systems. The operational transconductance amplifier (OTA) is a
fundamental building block in analog (mixed-signal) design and its performance
characteristics are the foundation of system level characteristics. Improving the
performance of the fundamental amplifier structure, while avoiding costly silicon area
and static power increases, is critical to improving system performance. The
application of Local Common Mode Feedback (LCMFB) [1-3] to the conventional
v
OTA structure provides significant increases in gain-bandwidth and slew rate
performance without an increase in static power and limited additional silicon area.
Both single ended and fully differential amplifier architectures are used in industry
for modern design. Fully differential amplifiers are used to provide additional signal
swing and reduce harmonic distortion characteristics. In the presented research, local
common mode feedback techniques are applied to both single ended and fully
differential operational transconductance amplifiers. LCMFB provides wide-range
programming of amplifier characteristics and increases the versatility of the amplifier
structure. A comparative analysis of LCMFB versus conventional structures via
theoretical calculation, simulation, and experimentation, emphasizes the benefits of
LCMFB in both single ended and fully differential structures. Results indicate gain-
bandwidth increases of a factor greater than 2 and slew rate increases at a factor close
to 4, with equal static power dissipation, and a minimal 15% increase in silicon area.
vi
TABLE OF CONTENTS Page
LIST OF TABLES............................................................................................ xii LIST OF FIGURES .......................................................................................... xiii 1 INTRODUCTION ...................................................................................... 1
1.1 The Operational Transconductance Amplifier......................................... 1
1.2 Local Common Mode Feedback.............................................................. 3
1.3 Characterization Parameters .................................................................... 5
1.4 Research Focus ........................................................................................ 5
2 THE CONVENTIONAL TRANSCONDUCTANCE AMPLIFIER.......... 7
2.1 Introduction.............................................................................................. 7
2.2 Operation.................................................................................................. 8
2.3 Signal Analysis ........................................................................................ 9
2.3.1 Open Loop Gain.................................................................................... 9
2.3.2 AC Analysis .......................................................................................... 10
2.3.3 Gain Bandwidth .................................................................................... 12
2.3.4 Maximum Output Current..................................................................... 12
2.3.5 Slew Rate .............................................................................................. 12
2.4 DC Analysis ............................................................................................. 13
2.4.1 Input Common Mode Range................................................................. 13
2.4.1.1 Minimum Input Voltage .................................................................... 13
2.4.1.2 Maximum Input Voltage.................................................................... 14
2.4.2 Output Voltage Range........................................................................... 15
vii
2.4.3 Static Power Dissipation ....................................................................... 16
2.5 Characterization ....................................................................................... 16
2.5.1 Gain and Phase Margins ....................................................................... 16
2.5.2 Input Offset Voltage ............................................................................. 17
2.5.2.1 Random Offset ................................................................................... 17
2.5.2.2 Systematic Offset ............................................................................... 17
2.5.3 Total Harmonic Distortion.................................................................... 18
2.5.4 Noise ..................................................................................................... 19
2.5.4.1 MOSFET Noise Models .................................................................... 19
2.5.4.2 Cascode Stage Noise.......................................................................... 21
2.5.4.3 Noise Analysis ................................................................................... 22
2.6 Fully Differential Implementation ........................................................... 23
2.6.1 Structure................................................................................................ 23
2.6.2 Common Mode Feedback ..................................................................... 25
2.6.3 Stability ................................................................................................. 27
2.7 Conclusions.............................................................................................. 27
3 THE PROPOSED TRANSCONDUCTANCE AMPLIFIER..................... 29
3.1 Introduction.............................................................................................. 29
3.2 Operation.................................................................................................. 30
3.3 Signal Analysis ........................................................................................ 32
3.3.1 Open Loop Gain.................................................................................... 32
3.3.1.1 Differential Input ............................................................................... 33
viii
3.3.1.2 Common Source Output Shell ........................................................... 34
3.3.1.3 Collective Open Loop Gain ............................................................... 35
3.3.2 AC Analysis .......................................................................................... 36
3.3.3 Gain Bandwidth .................................................................................... 38
3.3.4 Maximum Output Current..................................................................... 38
3.3.5 Slew Rate .............................................................................................. 39
3.4 DC Analysis ............................................................................................. 39
3.4.1 Input Common Mode Range................................................................. 39
3.4.2 Output Voltage Range........................................................................... 40
3.4.3 Static Power Dissipation ....................................................................... 40
3.5 Characterization ....................................................................................... 40
3.5.1 Gain and Phase Margins ....................................................................... 40
3.5.2 Input Offset Voltage ............................................................................. 41
3.5.3 Total Harmonic Distortion.................................................................... 41
3.5.4 Noise ..................................................................................................... 41
3.5.4.1 MOSFET Noise Models .................................................................... 41
3.5.4.2 Cascode Stage Noise.......................................................................... 42
3.5.4.3 Noise Analysis ................................................................................... 42
3.6 Fully Differential Implementation ........................................................... 43
3.6.1 Structure................................................................................................ 43
3.6.2 Common Mode Feedback ..................................................................... 44
3.6.3 Stability ................................................................................................. 45
ix
3.7 Conclusions.............................................................................................. 46
4 ANALYSIS................................................................................................. 47
4.1 Introduction.............................................................................................. 47
4.2 Design ...................................................................................................... 48
4.2.1 Design Specifications and Parameters .................................................. 48
4.2.2 Single Ended Conventional OTA ......................................................... 49
4.2.2.1 Theoretical Design ............................................................................. 49
4.2.2.2 Final Design ....................................................................................... 51
4.2.3 Single Ended LCMFB OTA ................................................................. 51
4.2.4 Fully Differential Conventional OTA................................................... 55
4.2.5 Fully Differential LCMFB OTA........................................................... 56
4.3 Calculation-Simulation-Experimentation ................................................ 57
4.3.1 Parameters............................................................................................. 58
4.3.2 Results and Analysis ............................................................................. 59
4.3.2.1 Open Loop Gain................................................................................. 59
4.3.2.2 Gain Bandwidth ................................................................................. 60
4.3.2.3 Maximum Output Current.................................................................. 62
4.3.2.4 Slew Rate ........................................................................................... 63
4.3.2.5 Static Power Dissipation .................................................................... 64
4.3.2.6 Gain and Phase Margin...................................................................... 65
4.3.2.7 Input Offset Voltage .......................................................................... 65
4.3.2.8 Harmonic Distortion .......................................................................... 66
x
4.3.2.9 Noise .................................................................................................. 67
4.3.2.10 Common Mode Feedback Characterization..................................... 68
4.3.2.11 Silicon Area ..................................................................................... 69
4.4 Conclusions.............................................................................................. 70
5 APPLICATIONS ........................................................................................ 72
5.1 Fully Differential Charge Scaling Digital-Analog Converter.................. 72
5.1.1 Simulation Specifications and Parameters............................................ 73
5.1.2 Results and Analysis ............................................................................. 74
5.2 Proposed Applications ............................................................................. 77
Appendices A. DESIGN CALCULATIONS ...................................................................... 79
B. THEORETICAL ANALYSIS CALCULATIONS..................................... 81 C. MICROGRAPHS........................................................................................ 90 D. INTERNET LINKS .................................................................................... 93 REFERENCES ................................................................................................. 95
xi
LIST OF TABLES
Table Page
4.1 Design Specifications and Parameters. ....................................................... 48
4.2 Conventional OTA Theoretical Design Transistor Sizes............................ 50
4.3 Conventional OTA Final Design Transistor Sizes...................................... 51
4.4 SE-LCMFB MR1,2 Design Transistor Sizes.............................................. 54
4.5 Fully Differential Conventional OTA Shell Transistor Sizes..................... 55
4.6 Fully Differential Conventional OTA CMFB Transistor Sizes.................. 56
4.7 FD-LCMFB MR1,2 Design Transistor Sizes. ............................................ 57
4.8 Simulation Parameters. ............................................................................... 58
4.9 Open Loop Gain Results............................................................................. 60
4.10 Gain Bandwidth Results. .......................................................................... 61
4.11 Maximum Output Current Results............................................................ 62
4.12 Slew Rate Results. .................................................................................... 64
4.13 Static Power Dissipation Results. ............................................................. 64
4.14 Gain and Phase Margin Simulation Results.............................................. 65
4.15 Offset Voltage Simulation Results............................................................ 65
4.16 Harmonic Distortion Simulation Results. ................................................. 66
4.17 Total Input Noise at 10MHz. .................................................................... 68
4.18 Common Mode Feedback Circuit Simulation Results.............................. 69
4.19 Analysis Summary Results. ...................................................................... 70
5.1 Fully Differential Charge Scaling DAC Design Parameters ...................... 73
5.2 Simulated DAC Specifications Summary................................................... 76
xii
LIST OF FIGURES
Figure Page
1.1 OTA Symbol and Equivalent Circuit.......................................................... 1
1.2 Conventional One Stage Operational Transconductance Amplifier........... 2
1.3 OTA Structure with Local Common Mode Feedback Resistors: R1,R2.... 3 1.4 OTA with Local Common Mode Feedback Transistors MR1,2................. 4
2.1 Conventional One Stage Operational Transconductance Amplifier........... 7
2.2 Conventional One Stage OTA Open Loop Gain Schematic....................... 9
2.3 Conventional One Stage OTA AC Analysis Schematic. ............................ 10
2.4 Input Differential Pair With Diode Connected Load.................................. 13
2.5 Conventional OTA Cascoded Output. ........................................................ 15
2.6 MOSFET With Thermal (iTH2(f)) and Flicker (iFL
2(f)) Noise Sources. ...... 19
2.7 Simplified MOSFET Noise Model. ............................................................ 20
2.8 Cascode Output Stage With Cascode Transistor Noise Sources (Vn2). ...... 21
2.9 Conventional OTA with MOSFET Noise Sources..................................... 22
2.10 Fully Differential Conventional OTA and Common Mode Feedback Circuit. ...................................................................................................... 23 2.11 Implemented Dual Shell Fully Differential Conventional OTA............... 24
3.1 OTA With Local Common Mode Feedback............................................... 29
3.2 LCMFB OTA With MOS Transistors MR1,MR2...................................... 30
3.3 LCMFB OTA Differential Input Stage....................................................... 33
3.4 (a) Input Stage Simplified Gain Analysis Schematic (b) Small Signal Equivalent Circuit (c) Simplified Small Signal Equivalent Circuit........... 33
xiii
3.5 LCMFB OTA Common Source Output Shell. ........................................... 35
3.6 LCMFB One Stage OTA AC Analysis Schematic. .................................... 36
3.7 LCMFB OTA Maximum Output Current Schematic. ................................ 38
3.8 LCMFB OTA with MOSFET Noise Sources............................................. 42
3.9 Fully Differential LCMFB OTA And Common Mode Feedback Circuit. ........................................................................................ 44 4.1 Diagrams: (a) SE-CONV (b) SE-LCMFB (c) FD-CONV (d) FD-LCMFB........................................................................................... 47 4.2 Conventional One Stage Operational Transconductance Amplifier........... 49
4.3 Single Ended OTA with Local Common Mode Feedback. ........................ 52
4.4 SE-LCMFB OTA MR1,2 Design Schematic.............................................. 53
4.5 Fully Differential, Dual Shell, Conventional OTA..................................... 55
4.6 Fully Differential OTA with Local Common Mode Feedback. ................. 56
4.7 Open-Loop Simulation Circuit Configurations: (a) SE (b) FD. ................. 59
4.8 Gain-Bandwidth Test Circuit Configurations: (a) SE (b) FD..................... 60
4.9 Maximum Output Current Test Circuit Configurations: (a) SE (b) FD...... 62
4.10 Slew Rate Test Circuit Configurations: (a) SE (b) FD. ............................ 63
4.11 OTA Total Input Noise Simulation Plots (a) SE (b) FD........................... 67
4.12 CMFB Open Loop Characterization Simulation Circuit Configuration. ........................................................................................... 68 4.13 Layout (a) SE-CONV (b) SE-LCMFB (c) FD-CONV (d) FD-LCMFB......................................................................................... 69 5.1 Fully Differential Charge Scaling Analog-Digital Converter..................... 72
5.2 FD-CONV DAC Analysis Plots (a) DNL (b) INL. .................................... 74
xiv
5.3 FD-LCMFB DAC Analysis Plots (a) DNL (b) INL. .................................. 75
5.4 Transient, Full Scale Settling Time Response. ........................................... 76
Figure C.1 Micrograph of Fabricated SE-CONV Structure (11880µm2) .............. 91
Figure C.2.2 Micrograph of Fabricated SE-LCMFB Structure (14421µm2) ........ 91 Figure C.3 Micrograph of Fabricated FD-CONV Structure (32340µm2).............. 91 Figure C.4.4 Micrograph of Fabricated FD-LCMFB Structure (36822µm2) ....... 91 Figure C.5.5 Micrograph of Fabricated 0.5um CMOS Test Chip .................... 92
xv
1 INTRODUCTION
1.1 The Operational Transconductance Amplifier
The schematic symbol and equivalent circuit model for an Operational
Transconductance Amplifier (OTA) are shown in Figure 1.1(a),(b) respectively.
+_
VI(+)
VI(-)VO
(a)
Gmvi RO vo
+_
vi
+_
Ri
io
(b)
Figure 1.1 OTA Symbol and Equivalent Circuit.
The OTA converts an input voltage to an output current relative to a transconductance
gain parameter Gm=io/vi. Ideally the input and output resistances are infinite
(Ri=Ro=∞) such that ii=iRo=0 and the output current is absorbed solely by the load.
The conventional OTA is classified as a class A amplifier and is capable of
generating maximum output currents equal to the bias current applied. The
equivalent circuit model indicates the transconductance amplifier generates an output
current (io) proportional to an input voltage (vi) based on the transconductance gain
Gm. The open circuit voltage gain of the conventional OTA model in Figure 1.1 (b) is
given by A=GmRo.
A conventional, one stage, CMOS, Operational Transconductance Amplifier
(OTA) configuration is shown in Figure 1.2.
1
M5
M7
Vdd
Vi(-) Vi(+)
Vcasp
Vcasn
Vss
Ibias
M3 M4
M1 M2
MB1 MB2
M6
M10
M9
M8
Vout
1:KK:1
Figure 1.2 Conventional One Stage Operational Transconductance Amplifier.
The OTA employs a differential input pair and three current mirrors. The differential
input pair is comprised of transistors M1,2. The differential pair is biased by MB1,2.
Mirrors formed by M3,5 and M4,6 reflect currents generated in the differential pair to
the output shell. The current generated by the mirror of M3,5 is then reflected to the
output via the mirror formed by M7,8. The mirror gain factor, K, indicates the gain in
mirrors formed by M3,5 and M4,6 with the following relations: β5=Kβ3, β6=Kβ4
where β=(KP/2)(W/L). Cascoding transistors M9,10 are biased by Vcasn/Vcasp and
provide increased gain via increased (cascoded) output resistance.
The conventional OTA is differentiated from other amplifiers by the fact that its
only high impedance node is located at the output terminal. The conventional OTA
does not employ an output buffer and is therefore, only capable of driving capacitive
loads. The gain of the OTA (GmRo) is dependent on the large output resistance of the
2
shell (M5-M10) and is decreased to GmRo//RL≈GmRL if a parallel resistive load RL is
applied. A detailed analysis of the conventional OTA is presented in Chapter 2.
1.2 Local Common Mode Feedback 1.2 Local Common Mode Feedback
Industry is researching techniques to reduce power requirements, while
increasing speed, to meet the demands of low (battery) powered wireless systems.
These systems require amplifiers with low bias currents, capable of producing large
dynamic currents. Application of Local Common Mode Feedback (LCMFB) [1-3]
techniques to the conventional OTA architecture produces an efficient class AB
amplifier with enhanced gain-bandwidth and slew rate. An OTA structure, with local
common mode feedback, provided by R1,R2, is shown in Figure 1.3.
Industry is researching techniques to reduce power requirements, while
increasing speed, to meet the demands of low (battery) powered wireless systems.
These systems require amplifiers with low bias currents, capable of producing large
dynamic currents. Application of Local Common Mode Feedback (LCMFB) [1-3]
techniques to the conventional OTA architecture produces an efficient class AB
amplifier with enhanced gain-bandwidth and slew rate. An OTA structure, with local
common mode feedback, provided by R1,R2, is shown in Figure 1.3.
Vdd
Vi(-) Vi(+)
Vcasp
Vcasn
Vss
Ibias
M3 M4
M1 M2
MB1 MB2
M5 M6
M10
M9
M8M7
IR
Id1 Id2
Id3 Id4
R1 R2
Vout
K:1 1:K
B
C
A
Figure 1.3 OTA Structure with Local Common Mode Feedback Resistors: R1,R2. Figure 1.3 OTA Structure with Local Common Mode Feedback Resistors: R1,R2.
3
The active load transistors M3,4 are reconnected to have a common gate (node C) and
matched resistors R1, R2 are used to connect the gate and drain terminals of M3, M4.
Resistors R1,R2 can be implemented with PMOS transistors MR1,2 operating in the
triode region as shown in Figure 1.4 below.
VR
MR1 MR2
Vdd
Vi(-) Vi(+)
Vcasp
Vcasn
Vss
M3 M4
M1 M2
M5 M6
M10
M9
M8M7
Vout
B
C
A
Ibias
MB1 MB2
Figure 1.4 OTA with Local Common Mode Feedback Transistors: MR1,2.
Control of the gate voltage of MR1,2 (VR) provides control of the triode resistance
generated. This variable resistance (voltage) allows programmability of the OTA and
provides increased gain-bandwidth and slew rate via a tradeoff in gain and phase
margin. A detailed analysis of the LCMFB OTA is presented in Chapter 3.
4
1.3 Characterization Parameters
Several common characterization methods are used to classify the
functionality of OTA structures. These performance measurement techniques will be
used to analyze designed structures via theoretical calculation, simulation, and
experimentation throughout the documentation presented in the following chapters.
A list of the measured characteristics is provided below. Detailed definitions and
derivations are provided in Chapter 2.
1. Open Loop Gain (AOL)
2. Gain Bandwidth(GB)
3. Maximum Output Current (IOUTMAX)
4. Slew Rate (SR)
5. Static Power Dissipation (PSTATIC)
6. Gain/Phase Margin (GM/PM)
7. Offset Voltage (VOS)
8. Harmonic Distortion (THD)
9. Noise (i2ni)
1.4 Research Focus
Four OTA structures were designed, simulated, fabricated, and tested
experimentally as follows:
1. Single Ended Conventional (SE-CONV)
2. Single Ended with Local Common Mode Feedback (SE-LCMFB)
3. Fully Differential Conventional (FD-CONV)
4. Fully Differential with Local Common Mode Feedback (FD-LCMFB)
5
The focus of the research presented will be a detailed comparison and analysis of
performance characteristics of the designed single ended and fully differential OTA
structures. Chapter 2 will provide a detailed, theoretical analysis of the single ended
and fully differential conventional OTA structures. Likewise, Chapter 3 will provide
a detailed, theoretical analysis of the modified single ended and fully differential
OTA structures with local common mode feedback. Chapter 4 will present a
comparative summary of performance characteristics (outlined in Section 1.3) of all
four OTA structures via theoretical calculation, simulation, and experimental results.
An outline of applications, including implementation of a fully differential, charge
scaling, digital to analog converter will be discussed in Chapter 5.
6
2 THE CONVENTIONAL TRANSCONDUCTANCE AMPLIFIER
2.1 Introduction
A conventional, one stage, Operational Transconductance Amplifier (OTA)
configuration is shown in Figure 2.1.
M5
M7
Vdd
Vi(-) Vi(+)
Vcasp
Vcasn
Vss
Ibias
M3 M4
M1 M2
MB1 MB2
M6
M10
M9
M8
Vout
1:KK:1
Figure 2.1 Conventional One Stage Operational Transconductance Amplifier.
The OTA employs a differential input pair and three current mirrors. The differential
input pair is comprised of transistors M1,2. The differential pair is biased by MB1,2.
Mirrors formed by M3,5 and M4,6 reflect currents generated in the differential pair to
the output shell. The current generated by the mirror of M3,5 is then reflected to the
output via the mirror formed by M7,8. The mirror gain factor, K, indicates the gain in
mirrors formed by M3,5 and M4,6 with the following relations: β5=Kβ3, β6=Kβ4
where β=KP/2(W/L). In the following analysis, it will be shown that an increase in K
will increase the slew rate and gain bandwidth of the conventional OTA at the cost of
7
increased area/static power dissipation and a decrease in phase margin. Cascoding
transistors M9,10 are biased by Vcasn/Vcasp and provide increased gain via increased
(cascoded) output resistance.
2.2 Operation
The conventional OTA (Figure 2.1) uses a differential pair in conjunction with
three current mirrors to convert an input voltage into an output current. Common
mode signals (Vi(+)=Vi(-)) are, ideally, rejected. For a common mode input voltage,
the currents are constant and will be: id1=id2=IBIAS/2, and iout=0. A differential input
signal will generate an output current proportional to the applied differential voltage
based on the transconductance of the differential pair. Although the output stage is a
push-pull structure, the conventional OTA is only capable of producing an output
current with a maximum amplitude equal to the bias current in the output shell
(K*IBIAS,OS). For this reason, the conventional OTA is a referenced as a class A
structure capable of producing maximum signal currents equal to that of the bias
current applied. Slew rate (SR) is directly proportional to the maximum output
current and is defined as the maximum rate of change of the output voltage. For a
single stage amplifier, the slew rate is the output current divided by the total load
capacitance. The conventional OTA therefore suffers the consequence that high
speed requires large bias currents which translates to large static power dissipation.
Wireless and battery powered systems require high slew rate and gain bandwidth
values with low static power dissipation. These requirements are difficult to achieve
with class A structures such as the conventional OTA. The proposed class AB
8
structure with Local Common Mode Feedback (LCMFB), presented in Chapter 3, can
meet these requirements [2].
2.3 Signal Analysis
2.3.1 Open Loop Gain
Figure 2.2
Figure 2.2 Conventional One Stage OTA Open Loop Gain Schematic.
will be referenced to determine the open loop gain.
M5
M7
Vdd
Vi(-) Vi(+)
Vcasp
Vcasn
Vss
Ibias
M3 M4
M1 M2
M6
M10
M9
M8
1:KK:1
Iout
Id1 Id2
Rout
Id2Id1
Id1
The output current, in terms of the mirror gain factor (K), is given by:
12 ddout KiKii −= (2.1)
where:
)(),( 2211 +=−= VigmiVigmi dd (2.2)
Assuming: gm1=gm2, and substituting (2.2) into (2.1):
))()((2,1 −−+= ViViKgmouti (2.3)
9
This indicates the transconductance gain of the OTA is given by:
2,1KgmGm = (2.4)
The output resistance is a cascode resistance and is given by:
89961010 // ooooOUT rrgmrrgmR = (2.5)
Combining (2.3) and (2.5), the output voltage is then given by:
)//))(()(( 899610102,1 oooooutoutout rrgmrrgmViViKgmRiv −−+== (2.6)
and the open loop gain is:
)//( 899610102,1 ooooin
outOL rrgmrrgmKgm
vvA == (2.7)
2.3.2 AC Analysis
Figure 2.3 will be referenced for AC analysis.
M5
M7
Vdd
Vi(-) Vi(+)
Vcasp
Vcasn
Vss
Ibias
M3 M4
M1 M2
M6
M10
M9
M8
1:KK:1
Iout
Id1
A B
OUT
CL
Cgs4Cgs5 Cgs3
Cdb1 Cdb2
Cdb3 Cdb4
Cgd2
Cgd5
Cgd1
Cgd6
Cgs6
Cdb10
Cdb9
Cgd10
Cgd9
Figure 2.3 Conventional One Stage OTA AC Analysis Schematic.
10
The gain bandwidth of the conventional one stage OTA is limited mainly by the low
impedance, high frequency, poles at nodes A/B, in conjunction with the high
impedance, low frequency pole at the output node [2].
The following analysis will define the high frequency pole and will assume
nodes A and B are equivalent nodes in terms of resistance and parasitic capacitance
(M1=M2, M3=M4, and M5=M6). The resistance at nodes A/B is dominated by the
diode connected resistance (1/gm) of M3,4 and is given by:
4,3
2,14,3
,1//1
gmr
gmR oBA ≈= (2.8)
The parasitic capacitance at A/B is given by:
6,54,36,56,54,34,32,12,1, gsgsgsgdgsdbdbgdBA CCCCCCCCC +≈+++++= (2.9)
Combining (2.8), (2.9), and the relation Cgs5,6=KCgs3,4 the pole at A/B is:
)1(22
1
4,3
4,3
,,, +
==KC
gmRC
fgsBABA
BpA ππ (2.10)
The output node capacitance is dominated by the load capacitance (CL) and is:
LLdbdgdbdgOUT CCCCCCC ≈++++= 101099 (2.11)
Combining (2.5) and (2.11), the dominant pole/bandwidth of the OTA is given by:
dBooooLOUTOUT
pOUT frrgmrrgmCRC
f 389961010 )//(2
12
1===
ππ (2.12)
11
This analysis indicates the relation between the phase margin and the mirror
gain factor (K). Equation (2.10) indicates the high frequency pole fpA,B is inversely
proportional to K. An increase in K will result in a decrease in fpA,B and consequently
a decrease in phase margin. The bandwidth of the conventional OTA is given in
Equation (2.12) and is inversely proportional to the load capacitance (CL).
2.3.3 Gain Bandwidth
Equations (2.7) and (2.12) are combined for the gain bandwidth (GB) product:
LC
Kgmπ2
2,1=GB (2.13)
This relation indicates that the GB is directly proportional to K.
2.3.4 Maximum Output Current
The maximum output current of the conventional OTA is limited by the
mirror gain factor (K) and the bias current and is given by:
(2.14) BIASMAXOUT KII =
2.3.5 Slew Rate
The slew rate (SR) is given by:
L
BIAS
L
MAXOUT
CKI
CI
==SR (2.15)
The slew rate therefore, increases linearly with K.
12
2.4 DC Analysis
2.4.1 Input Common Mode Range
The common mode range (CMR) is defined as the range of voltage
(V ) for which the input differential pair will remain in saturation. This
range is determined by the amplifier structure, transistor sizes, and bias current. For
the differential input stage with diode connected loads, the minimum and maximum
input voltages can be found by analysis of Figure 2.4.
MININ
MAXIN V,
Vdd
M3 M4
M1 M2 Vi+
IbiasMB2 Vbias
Vss
Vgs1
Vds1
Vsg3
VdsMB2
Figure 2.4 Input Differential Pair With Diode Connected Load.
2.4.1.1 Minimum Input Voltage
The minimum input voltage can be expressed as:
V (2.16) 11212 THNSAT
DSSAT
DSMBSSQ
GSSAT
DSMBSSMIN
IN VVVVVVV +++=++=
and substituting:
13
WKP
LIDDS
2V SAT = (2.17)
The minimum input voltage becomes:
11
1
2
22THN
N
BIAS
NMB
MBBIASSS
MININ V
KPWLI
KPWLIV +++=V (2.18)
where VTHN1 is body effected and may be larger than the zero bias threshold voltage.
The minimum input voltage is therefore limited by the VDS,SAT drop requirements
across M1,MB2 and a threshold drop across M1. The minimum input voltage is
inversely proportional to the widths of transistors M1,MB2 and directly proportional
to the bias current. To reduce V the bias current must be reduced or the widths of
the input transistors must be increased.
MININ
2.4.1.2 Maximum Input Voltage
The maximum input voltage ( ) and can be expressed: Figure 2.4
V (2.19) 13113 THNQ
SGDDGSSAT
DSQ
SGDDMAX
IN VVVVVVV +−=+−−=
and with substitution of (2.17):
133
3THNTHP
P
BIASDD
MAXIN VV
KPWLIV +
+−=V (2.20)
Again, VTHN1 is body effected and will be larger than anticipated. In this case, the
body effect actually increases input range by contributing toV . These results
indicate the bias current must be reduced and the width of M3 must be increased to
MAXIN
14
increase V . The maximum input voltage is, therefore, only limited by a VMAXIN GS drop
across M3. For this reason, the input voltage range is typically limited by V . The
common mode range of the NMOS differential pair is capable of swinging further in
the positive direction than the negative direction.
MININ
2.4.2 Output Voltage Range
The output voltage range is defined as V , V which represents the
maximum output swing available. The output range of the conventional OTA is
reduced due to cascoding at the output shown in Figure 2.5.
MAXOUT
MINOUT
Vdd
Vcasp
Vcasn
Vss
M6
M10
M9
M8
Iout
Vi+
Vi-
Figure 2.5 Conventional OTA Cascoded Output.
The output voltage range is given as:
V (2.21) 10,6, SATDSSATDSDDMAX
OUT VVV −−=
15
V (2.22) 9,8, SATDSSATDSSSMIN
OUT VVV ++=
2.4.3 Static Power Dissipation
The static power dissipation (PSTATIC) is the product of the sum of the currents
flowing through the current sources or sinks with the power supply voltages and is
given by [3]:
])[( 1,6,5,2,1, MBDMDMDMDMDSSDDSTATIC IIIIIVVP ++++−= (2.23)
and in terms of IBIAS and K (Figure 2.1):
)2(I)( KVVP BIASSSDDSTATIC +−= (2.24)
An increase in the mirror gain factor (K) will increase the SR and GB of the
conventional OTA at the cost of increased area and static power dissipation and a
decrease in phase margin.
2.5 Characterization
2.5.1 Gain and Phase Margins
The application of negative feedback requires analysis of the open loop gain.
Some circuits will cause a phase shift in the input signal large enough that the
feedback becomes positive (adds to the input), resulting in an unstable system [4].
Stability requires a phase shift in the feedback signal less than 180° for open loop
gain values larger than 0dB. This requirement necessitates the definition of two
measures of stability: gain margin (GM) and phase margin (PM). Gain and phase
margin parameters can be measured via analysis of the open loop AC response
simulation. The gain margin is defined as the difference (in dB) in the gain at a phase 16
of -180° and unity gain. Design guidelines typically specify a GM greater than 10dB.
The phase margin is defined as the difference (in degrees) in the phase at unity gain
and -180°. The phase margin should be greater than 45° with an optimum, critically
damped, value of 60° [5]. For PM values less than 60° the system is under-damped,
and the transient response will indicate increased slew rate at the cost of rise and fall
peaking. For PM values greater than 60° the system is over-damped, and the
transient response will indicate decreased slew rate. Phase margin depends on the
relative position of the high frequency pole fpA ( ) and the gain bandwidth
(unity gain frequency). The position of the high frequency pole location is therefore
directly related to the phase margin.
Figure 2.3
2.5.2 Input Offset Voltage
Ideally, if both inputs of the OTA are grounded, the output voltage should be
zero [4]. Practically, a nonzero output voltage (offset) will be present and is due to
random and systematic errors.
2.5.2.1 Random Offset
Random errors are due to mismatches in the input stage as a result of
fabrication including (but not limited to): threshold voltage differences and geometric
differences. Random errors can be estimated via Monte Carlo simulations [4].
2.5.2.2 Systematic Offset
Systematic errors are inherent to the design. Systematic errors can be the
result of non-symmetries in the OTA design, creating voltage and current
mismatches. The systematic offset can be determined via simulation and will be
17
evident in the DC sweep simulation as the offset from the zero-zero intercept where
the input voltage and output voltage should both equal zero.
2.5.3 Total Harmonic Distortion
Ideally, the output of an amplifier is a replica of the input signal scaled by the
gain A. The gain for large signal inputs is dependent on the input signal amplitude
[4]. For a purely sinusoidal input signal:
V )sin()( tVt Min ω= (2.25)
The non-ideal output signal of an amplifier can be expressed as:
V )sin(.......)2sin()sin()( 21 tnVatVatVat MnMMout ωωω +++= (2.26)
where the desired output is the fundamental a1VMsin(ωt) and ideally, a2 through an are
zero [3]. The nth term harmonic distortion is then given by:
1,1
>= naaHD n
n (2.27)
and the total harmonic distortion (THD) of the amplifier is given by:
21
224
23
22 ....
aaaaa n++++
=THD (2.28)
The THD provides a measure of the ratio of the magnitude of output signal harmonics
to the desired fundamental output.
18
2.5.4 Noise
2.5.4.1 MOSFET Noise Models
The dominant sources of noise in MOS transistors are thermal and flicker
noise [6]. These noise parameters must be modeled for circuit noise analysis.
Figure 2.6
Figure 2.6 MOSFET With Thermal (iTH2(f)) and Flicker (iFL
2(f)) Noise Sources.
Figure 2.6
shows a schematic of a transistor with both thermal and flicker noise
sources.
iTH2(f) iFL
2(f)
Thermal noise is due to thermal excitation of charge carriers in a conductor
[5]. It is proportional to temperature. Thermal noise can be modeled as a current
source iTH2(f) ( ) in parallel with the transistor. The thermal noise (current
source) can be approximately modeled with the following relation:
fgmkTfTH ∆= )32(4)(2i (2.29)
where k is Boltzmann’s constant (1.38*10-23 JK-1), T is the temperature in Kelvin, gm
is the transconductance of the transistor, and ∆f is the bandwidth in hertz [6].
19
Flicker noise is present under DC conditions and is the result of electron
trapping (delayed release) due to silicon imperfections in the transistor [5]. Flicker
noise is inversely proportional to frequency and is commonly referred to as 1/f noise.
The flicker noise can be modeled with a current source iFL2(f) (Figure 2.6) in parallel
with the transistor.
The current source is modeled with the following equation:
ff
IKfi D
FL ∆=α
)(2 (2.30)
where K is the (technology dependent) flicker noise constant, ID is the drain/bias
current, α is a constant (0.5> α <2), and f is the frequency in hertz [6].
A simplified model for transistor noise is shown in Figure 2.7:
Figure 2.7 Simplified MOSFET Noise Model.
in2(f)
The single current noise source can be modeled with the following equation:
ff
IKfgmkTTfi D
n ∆+∆=α
)32(4),(2 (2.31)
20
This equivalent noise source expression is a combination of the thermal (2.29) and
flicker (2.30) noise source equations. This model is accurate for long channel devices
(>1µm). For short channel devices, the thermal noise (first term in Equation 2.31)
may be 2 to 5 times larger than shown [6]. The equivalent noise current source (in2)
can also be represented as a voltage source (vn2) in series with the gate of the
transistor based on the relation vn2=in
2/gm2 [6].
2.5.4.2 Cascode Stage Noise
The noise contribution of the output stage cascoding transistors (M9,10)
shown in Figure 2.8 is negligible [7].
Figure 2.8 Cascode Output Stage With Cascode Transistor Noise Sources (Vn2).
Vdd
Vss
M6
M10
M9
M8
Iout
Vi+
Vi-
vn,M92
vn,M102
X
Y
Cascode transistor noise sources, modeled as voltage sources v2n,M9 and v2
n,M10,
introduce a small voltage differential at the gate of transistors M9,10 respectively.
21
This small voltage differential is coupled to nodes X and Y (drains of M6,9) through
M9,10. Transistors M6,9 are operating in saturation and their drain current is
therefore insensitive to small changes in their VDS voltages. Thus, cascode transistors
contribute virtually no noise to the circuit.
2.5.4.3 Noise Analysis
Figure 2.9
Figure 2.9 Conventional OTA with MOSFET Noise Sources.
shows the conventional OTA structure with MOSFET noise
sources.
Vout
M5
M7
Vdd
Vi(-) Vi(+)
Vcp
Vcn
Vss
M3 M4
M1 M2
M6
M10
M9
M8
2in,M1
2in,M4 2in,M6
2in,M10
2in,M9
in,M8
2in,M2
2in,M32in,M5
2in,M7
Ibias
2
K:1 1:K
Assuming matching (M1=M2, KM3=KM4=M5=M6, M7=M8), neglecting the noise
introduced by cascoding transistors M9, M10, and neglecting common mode noise
introduced by the biasing transistors (the output is taken as a difference, eliminating
22
common mode noise), the input referred noise can be derived (in terms of K and in2)
as follows.
)](1[2 22222 iiiii +++= (2.32)7,5,23,1,, MnMnMnMnOTAni K
2
23
Figure 2.10 FD Conventional OTA and Common Mode Feedback Circuit.
Vo(+)
Vi(-) Vi(+)
Vcasp
Vcasn
Vss
M1 M2
M8
M10
M13
Vcasp
Vcasn
Vo(-)
M7
M9
M11 M12 Vbiasn Vbiasn Vcm
Vcm
M16 M17 M18 M19
M21M20
Vss
M14 M15 Vbiasp
Vcmref
Vo(+) Vo(-)
Fully Differential Conventional OTA Common Mode Feedback Circuit
K/2:1 1:K/2
BA
For unity mirror gain (K=1) the equivalent noise is just the summation of transistor
noise sources M1-M8. The noise in transistors M5-M8 decreases with a factor 1/K ,
A conventional, fully differential (FD), implementation of the one stage OTA
e feedback circuitry is shown in Figure 2.10. Advantages of the
fully di
M5
indicating a decrease in noise with an increase in current.
2.6 Fully Differential Implementation
2.6.1 Structure
with common mod
fferential structure include: improved output voltage swing, less susceptibility
to common mode noise, and cancellation of even-order nonlinearities [6].
Vdd
M3 M4M6
K:1 1:KVdd
The architecture of the fully differential OTA is similar to that of its single
nded counterpart (Figure 2.1) with the following exceptions. First, the mirror in the
single ended architecture, formed by transistors M7-8, has been replaced with
cascoded current mirrors, biased by Vbiasn, and formed by M9,11 / M10,13. Second, a
common mode feedback circuit formed by transistors M14-21 has been implemented
to control the common mode output voltage. Lastly, the bias current for the
differential pair is now controlled actively by the common mode feedback circuit via
the control voltage Vcm. This design lacks current mirroring capability generated by
M7,8 (Figure 2.1) for the single ended structure and is therefore only capable of a
maximum output current at each output equal to half the bias current.
the
e
In order to achieve output currents equal to the bias current at each output,
dual shell structure shown in Figure 2.11 was implemented.
24
Figure 2.11 Implemented Dual Shell Fully Differential Conventional OTA.
Vi(-) Vi(+)
Vcasn
Ibias
M1 M2
M9
M8M7
iD1 ID2
Vo(+)
Vcasn
Vss
M15
M14 M13
Vo(-)
Fully Differential Conventional OTA Common Mode Feedback Circuit
ICM
E
ICM
D M28M27
ICMICM
M23 M24 M25 M26
M29
Vss
Vbiasp
Vcmref Vo(+) Vo(-)
M30
M22M21 Vcasp
Vdd
M3 MM5
iD3 iD4
M12114
M6
Vcasp M10BA
Vcasp
M
M16 M17 M18 M20
Vdd
M19
This fully differential OTA maintains mirroring capability via mirrors formed by
M7,8 and M13,14 and is capable of generating maximum output currents equal to
de feedback (CMFB) circuit for the dual shell structure
hat of the CMFB circuit for the standard fully
n
to
IBIAS at each output terminal.
2.6.2 Common Mode Feedback
The implemented common mo
(Figure 2.11) is more complex than t
differential OTA (Figure 2.10) but still utilizes dual differential pairs and performs
the same function. The dual differential pair structure introduces only a small
capacitive load (Cgs16,19) at the output of the OTA avoiding resistive loading commo
to many CMFB circuits. The function of the common mode feedback circuit is
define/control the common mode voltage such that:
cmcmrefoo vvvv ==−=+ )()( (2.33)
when a common mode input is applied (vi(+)=vi(-)).
Vcmref is typically set to:
cmDD
cmref vVssVv =−
=2
(2.34)
such that for complementary sources, vcm=0. The common mode reference voltage
(Vcmref, Figure 2.10) is compared with vo,cm given by:
)()(= oov
2,−−+
cmovv (2.35)
via the dual differential pairs.
25
The common mode voltage of t y differential, dual shell, OTA is he conventional, full
controlled via current injection from the common mode feedback circuit at low
.11).
re required to provide correction currents for
eac
the
t
t
tage
ed at nodes
.
impedance nodes D/E (Figure 2
The CMFB circuit utilizes two, identical, current mirrors, formed by M27,29 and
M28,29, to generate replica correction currents (ICM) which are injected at low
impedance nodes D/E. ors a These mirr
e transistors
h complementary shell independently. Active control of the bias current will not
correct the common mode voltage of the dual shell fully differential OTA due to
mirroring function of the shell structures. Adjustment of the bias current would resul
in complementary voltage changes at nodes A/B, resulting in complementary drain
current changes for M5,6 and M11,12. The shell structure would mirror these
complementary changes to the output, resulting in zero net voltage change. Replica
common mode correction currents ICM are therefore required to facilitate independen
shell common mode correction. Based on this analysis, two common mode vol
correction scenarios are possible (referencing Figure 2.11) as follows:
1. If vo,cm > vcmref, less current is passed through M29. This decrease in current is
mirrored to M27,28. ID27,28 is fixed by transistors M17,18 respectively. The
excess current id17,18 generated by thes is then inject
E/D (transistors M7,13) and coupled to the output via mirror transistors
M8,14. The resulting increase in iD8,14 pulls current from the output node and
the output voltage is reduced, to attain: vo(+) = vo(-) = vcmref (Equation 2.33)
26
If vo,cm < vcmref, more current is passed through M29. This increase in current
is mirrored to M27,28. ID27,28 is fixed by transistors M17,18 respectively.
2.
The required increase in current is then pulled from nodes D/E (transistors
M7,13) and coupled to the output via mirror transistors M8,14. The resultin
decrease in iD8,14 injects current at the output node and the output voltage is
increased, to attain: vo(+) = vo(-) = vcmref (Equation 2.33).
Stability
Since the CMFB loop is a negative feedback loop, stability
g
2.6.3
is a key issue [4].
M ure has a dominant low frequency pole (fpIN) at the input (due to CL)
and fou
conventional OTA structure was presented.
tr e amplifier rejects common mode signals and generates an output
current n
n
The C FB struct
r high frequency poles associated with diode connected transistors M27,28
and the feedback injection transistors M7,13 (nodes D/E, Figure 2.11). The gain and
phase margin of the CMFB circuit must also be verified and remain within the
parameters outlined in Section 2.5.1.
2.7 Conclusions
A full analysis of the one-stage
The ansconductanc
dependent on the input voltage. Cascoding of the output shell to increase gai
necessitates the requirement of a purely capacitive load. The structure is class A and
the maximum output current is limited by the magnitude of the bias current in the
output shell. The mirror gain factor K (Figure 2.1) can be increased to increase the
maximum output current (slew rate) and gain bandwidth at the cost of an increase i
static power, and area, as well as a decr argin and stability. ease in phase m
27
Chapter 3 will provide a detailed analysis of the proposed OTA configuration with
local common mode feedback (LCMFB).
28
3 THE PROPOSED TRANSCONDUCTANCE AMPLIFIER
3.1 Introduction
The proposed operational transconductance amplifier (OTA), with local
Figure 3.1 OTA With Local Com e
common mode feedback (LCMFB) is shown in Figure 3.1.
Feedback.
imilar to the conventional OTA, the LCMFB OTA structure utilizes a differential
it
d
d
Vdd
Vi(-) Vi(+)
Vcasp
Vcasn
Vss
Ibias
M3 M4
M1 M2
MB1 MB2
M5 M6
M10
M9
M8M7
IR
Id1 Id2
Id3 Id4
R1 R2
Vout
K:1 1:K
B
C
A
mon Mod
modificati
S
pair (M1,2) and three current mirrors (M3,5, M7,8, and M4,6). In the LCMFB circu
however, the active load transistors M3,4 are reconnected to have a common gate
(node C) and matched resistors R1, R2 (Figure 3.1) are used to connect the gate an
drain terminals of M3, M4. This simple on has several performance
enhancing benefits versus the conventional OTA architecture including class AB
operation which provides enhancement in slew rate (SR), gain bandwidth (GB), an
29
linearity, with equal static power dissipation. Implementation of resistors R1,R2 with
MOS transistors MR1,MR2, shown in Figure 3.2, provides programmable
performance characteristics (via the co ge VR), allowing utilization
same OTA for multiple applications. Class AB operation characteristics allow the
LCMFB structure to outperform the conventional structure with unity mirror gain.
The analysis for the LCMFB OTA will therefore be based on a unity mirror gain
factor (K=1, M3=M4=M5=M6, and M7=M8).
3.2 Operation
h
MOS transistors MR1,MR2, shown in Figure 3.2, provides programmable
performance characteristics (via the co ge VR), allowing utilization
same OTA for multiple applications. Class AB operation characteristics allow the
LCMFB structure to outperform the conventional structure with unity mirror gain.
The analysis for the LCMFB OTA will therefore be based on a unity mirror gain
factor (K=1, M3=M4=M5=M6, and M7=M8).
3.2 Operation
of the
shows the LCMFB OTA structure with transistors MR1, MR2
implem
of the
shows the LCMFB OTA structure with transistors MR1, MR2
implem
ntrol volta
ented to fu
ntrol volta
ented to fu
Figure 3.2 Figure 3.2
nction in the triode region and act as programmable resistors. nction in the triode region and act as programmable resistors.
Vdd
Figure 3.2 LCMFB OTA With MOS Transistors MR1,MR2. Figure 3.2 LCMFB OTA With MOS Transistors MR1,MR2.
VR
MR1 MR2iR
Vi(-) Vi(+)
Vcasp
Vcasn
Vss
Ibias
M3 M4
M1 M2
M5 M6
M10
M9
M8M7
iD1 ID2
iD3 iD4
Vout
B
C
A
30
For quiescent (or common mode) operation, the drain currents of transistors M1-M10
cted)
have equal values (ID1-10=Ibias/2) while the current iR in transistors MR1,2 is zero.
The gate-source voltage of M3,4 is the same as their drain-source voltage. For
common mode signals, these transistors perform as low impedance (diode conne
loads with value:
4,3
1gm
RCML = (3.1)
Upon application of a differential signal, the signal current component (id=ir) flows
through transistors MR1,2, and iD1,2 are given by:
BIASIiIi =+= rdDD i±22,1 (3.2)
where:
2
2,12,12,1
2/12
−−=
THNGS
ddr VV
vvgmi (3.3)
and vd is the applied differential voltage. The drain currents in M3,4 remain
yunchanged (iD3,4=IBIAS/2). The current ir generates differential complementar
voltage changes at nodes A and B while node C remains at a constant voltage. S
voltages at nodes A and B are given by:
BA vv =−=
ignal
2,1MRr Ri
where RMR1,2 is the resistance g stors MR1, MR2 and, based on the
(3.4)
enerated by transi
triode channel resistance equation, is given by:
31
1)(2,1
2,1PTHRCMR
MR VVVR
−−=β
(3.5)
Where VR is the applied control voltage (Figure 3.2), βMR1,2=KP(WMR1,2/LMR1,2), and
VC is the constant voltage at node C. This complementary swing at A,B generates
large, non-complimentary, signal current ell (M5-10) of the OTA by
creating large gate-source voltage differentials for common source transistors M5,
M6, respectively.
3.3 Signal Analysis
3.3.1 Open Loop
s in the sh
Gain
Calculation of the open loop gain of the LCMFB OTA structure requires two
nput must first be analyzed followed by the
commo
e
independent analyses. The differential i
n source output shell. The collective LCMFB OTA gain will then be defined
as the combination of the previous analyses. The following analysis will assume
transistor matching for the following devices M1=M2, M3=M4=M5=M6, M7=M8,
and MR1=MR2. The gain will be analyzed focusing on the path from the negative
input terminal (at the gate of M1) to the output terminal. This analysis will therefore
focus on transistors M1, M3, MR1, and M5 but it should be noted that analysis of th
positive signal input (at the gate of M2) would yield identical results with equivalent
transistor substitutions as listed above.
32
3.3.1.1 Differential Input
The differential input stage is shown in Figure 3.3.
Vi(-) Vi(+) VR
MR1 MR2
Vdd
Ibias
M3 M4
M1 M2
B
C
A
Figure 3.3 LCMFB OTA Differential Input Stage.
Given that the common combined gate of M3,4 (node C) is an AC ground, the circuit
can be simplified to the analysis circuit and small signal models (derived from the
MOSFET hybrid-π model) shown in Figure 3.4 (a), (b), and (c).
g3g1
s1
s3
vgs1
vsg3
d1,3
ro1
ro3
RMR1
gm1vgs1
gm3vsg3
vsg3=0MR1
M3
M1id1
CA
g1
s1
vgs1RA,Bgm1vgs1
(a) (b) (c)
Vd2
Vd2
Vd2
Figure 3.4 (a) Input Stage Simplified Gain Analysis Schematic (b) Small Signal Equivalent Circuit (c) Simplified Small Signal Equivalent Circuit.
33
The source and gate terminals of M3 are grounded (vgs3=0) in the small signal model
eliminating the dependent current source gm3vgs3. Thus the small signal current is
given by:
i 2,12,12,1 gsd vgm= (3.6)
and the equivalent resistance is given by:
2,14,32,1, //// MRooBA RrrR = (3.7)
vA,B are then a combination of (3.6) and (3.7) and is given by:
))(////( 2,12,12,14,32,12,1, gsMRoooutdBA vgmRrrRiv == (3.8)
vd/2=vgs1,2 and the gain of the differential (ACORE) input stage is given by:
2
)////)((2
2,14,32,12,1,2,1, MRooBA
d
BACORE
RrrgmRgmv
vA === (3.9)
3.3.1.2 Common Source Output Shell
The common source output shell is shown in Figure 3.5 and consists of two
common source amplifiers (M5, M6), a current mirror (M7, M8), and cascoding
output transistors (M9, M10). The cascoded output provides the large output
resistance required for large gain in the output shell. The output resistance of the
LCMFB OTA is identical to that of the conventional OTA (Equation 2.5) and is given
by:
89961010 // ooooOUT rrgmrrgmR = (3.10)
34
Vdd
Vcasp
Vcasn
Vss
M5 M6
M10
M9
M8M7
Vout
BA
Figure 3.5 LCMFB OTA Common Source Output Shell.
The current mirror has unity gain, and the gain of the output stage (AOS) is given by:
)//(22 899610106,56,5 ooooOUTSHELL rrgmrrgmgmRgmA == (3.11)
3.3.1.3 Collective Open Loop Gain
The open loop gain of the LCMFB OTA is then given by the multiplication of
the gain of the input stage (ACORE, 3.9) and the output shell (ASHELL, 3.11) and is given
by:
OUTBAOL RgmRgmA 6,5,2,1= (3.12)
This definition indicates that the gain of the LCMFB OTA is a function of the
programmable resistance RMR1,2. This dependence provides an interesting
characteristic of functionality. For RMR1,2≈1/gm, RMR1,2 will dominate the parallel
combination ro1,2//ro3,4//RMR1,2, and the structure will behave as a one stage amplifier
35
(ACORE<<ASHELL). An increase in RMR1,2≈ro1,2//ro3,4 will result in increased gain in the
input stage and the structure will behave as a two stage amplifier (ACORE<ASHELL).
Two stage operation would eliminate the need for cascoding transistors M9,10 and
would require compensation.
3.3.2 AC Analysis
Figure 3.6 is referenced for AC analysis.
M5
M7
Vdd
Vi(-) Vi(+)
Vcasp
Vcasn
Vss
Ibias
M3 M4
M1 M2
M6
M10
M9
M8
1:KK:1
Iout
Id1
OUT
CL
Cgs5
Cdb3 Cdb4
Cgd2
Cgd5
Cgd1
Cgd6
Cgs6
Cdb10
Cdb9
Cgd10
Cgd9
VR
MR1 MR2
CCgs3 Cgs4
BA
Cdb1 Cdb2
CdbMR2CdbMR1
Figure 3.6 LCMFB One Stage OTA AC Analysis Schematic.
Similar to the conventional OTA, the frequency response of the LCMFB OTA is
determined mainly by the low impedance, high frequency, poles at nodes A/B, in
conjunction with the high impedance, low frequency pole at the output node.
36
The following analysis defines the high frequency pole and assumes nodes A and B
are equivalent nodes in terms of resistance and parasitic capacitance (M1=M2,
M3=M4, M5=M6, MR1=MR2). The resistance at nodes A/B (Equation 3.7) becomes
a function of the triode resistance (RMR1,2) created by MR1,2 and is given by:
2,14,32,1, //// MRooBA RrrR = (3.13)
Given that node C (Figure 3.6) is a virtual ground, the parasitic capacitance at nodes
A/B does not include Cgs3,4. The addition of MR1,2 does introduce an additional
parasitic Csb,MR1,2, but the well known relation Cgs >> Csb, and the relative dimensions
of the transistors W3 >> WMR, indicate the parasitic capacitance at A/B is reduced by a
factor close to 2 (K=1) versus the conventional structure. The parasitic capacitance at
A/B is given by:
6,52,16,56,54,32,12,1, gssbMRgsgddbdbgdBA CCCCCCCC ≈+++++= (3.14)
Combining equations (3.13) and (3.14), the pole at A/B is:
)////(2
12
1
2,14,32,16,5,,,
MRoogsBABABpA RrrCRC
fππ
== (3.15)
The output node capacitance is dominated by the load capacitance and is equal to that
of the conventional structure (Equation 2.11):
LLdbdgdbdgOUT CCCCCCC ≈++++= 101099 (3.16)
Combining (3.10) and (3.16), the dominant pole/bandwidth of the OTA is also
equivalent to the conventional structure (Equation 2.12) and is given by:
37
dBooooLOUTOUT
pOUT frrgmrrgmCRC
f 389961010 )//(2
12
1===
ππ (3.17)
3.3.3 Gain Bandwidth
Equations (3.12) and (2.17) are combined for the gain bandwidth product:
L
MRoo
OUTL
OUTBA
CRrrgmgm
RCRgmRgm
ππ 2)]////([
2]][[ 2,14,32,16,52,16,5,2,1 ==GB (3.18)
The GB is dependent on the programmable resistance RMR1,2. As RMR1,2 increases, the
GB increases.
3.3.4 Maximum Output Current
The maximum output current can be found by analysis of Figure 3.7.
VR
MR2
Vdd
Vcasp
M4 M6
M10
Iout
CVDS,SAT
QIOUTMAX
VGSMAX
Figure 3.7 LCMFB OTA Maximum Output Current Schematic.
Class AB operation provides large non-symmetric currents in the output shell. These
currents are created by the large gate-source voltage swings (generated at nodes A/B)
38
applied to M5,M6. Maximum output current generation occurs when the maximum
gate-source differential is applied to M6 (or M5) and M5 (or M6) is in cutoff.
The maximum output current is given by:
(3.19) 26,54,3,6,5 )( MAX
GSQ
SATSDMAXOUT VVI ∆+= β
where:
2,16,5 2 MRBIASMAX
GS RIV =∆ (3.20)
represents the maximum swing at nodes A and B.
3.3.5 Slew Rate
The slew rate (SR) is then given by:
L
MAXGS
QSATSD
L
MAXOUT
CVV
CISR
26,54,3,6,5 )( ∆+
==β
(3.21)
The slew rate is a function of (Equation 3.20) and is therefore directly
proportional to R
MAXGSV 6,5∆
MR1,2. An increase in RMR1,2 translates to an increase in the slew rate.
3.4 DC Analysis
3.4.1 Input Common Mode Range
The CMR of the LCMFB OTA is equivalent to the CMR of the conventional
structure. The analysis for the CMR can be found in Section 2.4.1.
39
3.4.2 Output Voltage Range
The output voltage range of the LCMFB OTA is also equivalent to the output
range of the conventional structure and a full analysis can be found in Section 2.4.2.
3.4.3 Static Power Dissipation
The static power dissipation (PSTATIC) is the product of the sum of the currents
flowing through the current sources or sinks with the power supply voltages and is
given by:
])[( 1,6,5,2,1, MBDMDMDMDMDSSDDSTATIC IIIIIVVP ++++−= (3.22)
And in terms of IBIAS (K=1 for the LCMFB structure):
BIASSSDDSTATIC VVP I3)( −= (3.23)
Class AB operation in the LCMFB OTA produces signal currents much larger
than the bias current applied with the same static power dissipation as that of the
conventional structure (K=1). The advantage of this operation is the capability to
design high slew rate architectures with low static power dissipation.
3.5 Characterization
3.5.1 Gain and Phase Margins
The gain and phase margin are defined in Section 2.5.1. The phase margin is
an indication of the relative position of the high frequency pole fpA,B (Figure 3.2) and
the gain bandwidth. For a fixed GB, an increase in the frequency of fpA,B translates to
an increase in the phase margin. Likewise, a decrease in fpA,B, translates to a decrease
in the phase margin. The addition of transistors MR1,2 results in a factor 2 reduction
40
in the capacitance at nodes A/B (as defined in Section 3.3.2), translating to an
increase in the position of the high frequency pole and an increase in the phase
margin. The position of fpA,B is a function of the resistance generated by transistors
MR1,2 (Figure 3.2) and is defined by equation 3.15. The control voltage VR provides
programmable resistance values for transistors MR1,2 and therefore allows
programmable control of the phase margin. Both the phase margin (via fpA,B) and the
open loop gain (Equation 3.12) are a function of the triode resistance generated by
MR1,2, RMR1,2 (Equation 3.5). As mentioned in Section 2.5.1, a decrease in phase
margin increases slew rate at the cost of decreased stability. The resistance RMR1,2
can, therefore, be used to trade off slew rate and gain bandwidth enhancement with
phase margin.
3.5.2 Input Offset Voltage
The definition of the offset voltage for the conventional OTA is equivalent to
the LCMFB structure and is presented in Section 2.5.2.
3.5.3 Total Harmonic Distortion
The definition of the THD for the conventional OTA is equivalent to the
LCMFB structure and is presented in Section 2.5.3.
3.5.4 Noise
3.5.4.1 MOSFET Noise Models
MOSFET noise models are presented in Section 2.5.4.1 and are equivalent to
models used to perform noise analysis for the LCMFB OTA.
41
3.5.4.2 Cascode Stage Noise
Section 2.5.4.2 defines the negligible contribution of noise sources due to
cascoding transistors. Cascode noise sources will therefore be excluded in the
following analysis.
3.5.4.3 Noise Analysis
Figure 3.8
Figure 3.8 LCMFB OTA with MOSFET Noise Sources.
shows the LCMFB OTA structure with MOSFET noise sources.
VR
MR1 MR2
Vdd
Vi(-) Vi(+)
Vcasp
Vcasn
Vss
Ibias
M3 M4
M1 M2
M5 M6
M10
M9
M8M7
Vout
B
C
A
in,M62
in,M102
in,M92
in,M82
in,M52
in,M72
in,M42in,M3
2
in,M12 in,M2
2
in,MR12 in,MR2
2
Assuming matching (M1=M2, M3=M4=M5=M6, M7=M8, MR1=MR2), neglecting
the noise introduced by cascoding transistors M9, M10, and neglecting common
mode noise introduced by the biasing transistors, the input referred noise can be
derived (in terms of in2) as follows.
42
)]()(
1[2 27,
25,2
,6,5
21,
23,
21,
2, MnMn
BAMRnMnMnLCMFBOTAni ii
Rgmiii ++++=i (3.24)
The noise of the LCMFB OTA is a function of the transconductance of M5,6, and the
resistance RA,B (Equation 3.13). RA,B is dependent on RMR indicating that an increase
in RMR results in a decrease in noise contributed from the shell transistors. The
addition of transistors MR1,2 results in the addition of two sources of noise for the
LCMFB configuration (2*i2n,MR1) which contribute negligible additional noise and
decrease the noise contribution of the shell transistors.
3.6 Fully Differential Implementation
3.6.1 Structure
A fully differential implementation of the OTA with local common mode
feedback and a common mode feedback network is shown in Figure 3.9. The basic
structure of the fully differential LCMFB architecture is similar to that of its single
ended counterpart with the following exceptions. A second shell, formed by
transistors M11-16, provides complementary output current. Implementation of the
second shell is required to provide mirroring of large, non-symmetric, class AB
currents at the positive and negative outputs. A common mode feedback circuit,
formed by transistors M17-30, has been implemented to control the common mode
output voltage. The common mode voltage is controlled via current injection from
the common mode feedback circuit at low impedance nodes D/E.
43
VR
MR1 MR2iR
Vdd
Vi(-) Vi(+)
Vcasp
Vcasn
Ibias
M3 M4
M1 M2
M5 M6
M10
M9
M8M7
iD1 ID2
iD3 iD4
Vo(+)
B
C
A Vcasp
Vcasn
Vss
M12M11
M16
M15
M14 M13
Vo(-)
Fully Differential OTA With Local Common Mode Feedback Common Mode Feedback Circuit
ICM
E
ICM
D
M17
M28M27
ICMICM
M23 M24 M25 M26
M29
Vss
Vdd
M19
Vbiasp
Vcmref Vo(+) Vo(-)
M20
M30
M18
M22M21 Vcasp
Figure 3.9 Fully Differential LCMFB OTA And Common Mode Feedback Circuit.
Advantages of the fully differential structure include: improved voltage swing, less
susceptibility to common mode noise, and even-order nonlinearity cancellation [5].
3.6.2 Common Mode Feedback
Common mode voltage variables (vcm (2.36), vcmref (2.36), vo,cm (2.37)) and the
function of the common mode feedback circuit are defined in Section 2.6.1. The
CMFB circuit for the LCMFB OTA utilizes two, identical, current mirrors, formed by
M27,29 and M28,29, to generate replica correction currents (ICM) which are injected
at low impedance nodes D/E (Figure 3.9). These mirrors are required to provide
correction currents for each complementary shell independently. Active control of
the bias current will not correct the common mode voltage of the LCMFB fully
differential OTA due to the mirroring function of the shell structures. Adjustment of
the bias current would result in complementary voltage changes at nodes A/B,
44
resulting in complementary drain current changes for M5,6 and M11,12. The shell
structure would mirror these complementary changes to the output, resulting in zero,
net voltage change. Replica common mode correction currents ICM are therefore
required to facilitate independent shell common mode correction. Based on this
analysis, and similar to the conventional structure, two common mode voltage
correction scenarios are possible (referencing Figure 3.9) as follows:
1. If vo,cm > vcmref, less current is passed through M29. This decrease in current is
mirrored to M27,28. ID27,28 is fixed by transistors M17,18 respectively. The
excess current id17,18 generated by these transistors is then injected at nodes
D/E (transistors M7,13) and coupled to the output via mirror transistors
M8,14. The resulting increase in iD8,14 pulls current from the output node and
the output voltage is reduced, to attain: vo(+) = vo(-) = vcmref (Equation 2.33).
2. If vo,cm < vcmref, more current is passed through M27. This increase in current
is mirrored to M27,28. ID27,28 is fixed by transistors M17,18 respectively.
The required increase in current is then pulled from nodes D/E (transistors
M7,13) and coupled to the output via mirror transistors M8,14. The resulting
decrease in iD8,14 injects current at the output node and the output voltage is
increased, to attain: vo(+) = vo(-) = vcmref (Equation 2.33).
3.6.3 Stability
Stability of the common mode feedback loop is equally important to that of
the differential loop. The LCMFB OTA CMFB structure has a dominant low
frequency pole (fpIN) at the input (due to CL) and four high frequency poles associated
45
with diode connected transistors M27,28 and the feedback injection transistors M7,13
(nodes D/E, Figure 3.9). The gain and phase margin of the CMFB circuit must be
verified and remain within the parameters outlined in Section 2.5.1.
3.7 Conclusions
A full analysis of the LCMFB OTA structure was presented. The addition of
LCMFB was shown to have several performance enhancing benefits versus the
conventional OTA architecture including Class AB operation which provides
enhancement in slew rate (SR), and gain bandwidth (GB), with equal static power
dissipation. Implementation of LCMFB with MOS transistors MR1,MR2, shown in
Figure 3.2, provides programmable gain (via the control voltage VR), allowing
utilization of the same OTA for multiple applications. Class AB operation
characteristics allow the LCMFB structure to outperform the conventional structure
with unity mirror gain (K=1). MR1,2 provide the ability to trade slew rate and gain
bandwidth enhancement for phase margin. The benefits of the LCMFB structure are
considerable for a negligible increase in area and equal static power dissipation.
Chapter 4 focuses on design and testing of the conventional and LCMFB OTA
structures in both the single ended and fully differential configuration and provides a
detailed performance comparison from theoretical, simulation, and experimental
perspectives.
46
4 ANALYSIS
4.1 Introduction
As a method of verifying performance enhancements achieved with the
addition of local common mode feedback, Chapter 4 will focus on a detailed
comparison of performance characteristics for the single ended (SE) and fully
differential (FD) OTA structures with and without local common mode feedback.
The design and evaluation, via theoretical calculation, simulation, and
experimentation, of the following four structures is presented:
1. Single-Ended Conventional (SE-CONV)
2. Single-Ended With Local Common Mode Feedback (SE-LCMFB)
3. Fully Differential Conventional (FD-CONV)
4. Fully Differential With Local Common Mode Feedback (FD-LCMFB)
Transistor level design of all test structures is presented in detail in Section 4.2.
Block diagrams, shown in Figure 4.1, are used to distinguish architectures and
illustrate simulation and experimental configurations throughout the chapter.
+_ +
_VI(+)
VI(-)
VO(-)
VO(+)
+_
VI(+)
VI(-)VO
(a)
(c)
+_ +
_VI(+)
VI(-)
VO(-)
VO(+)
+_
VI(+)
VI(-)VO
(b)
(d)
SE-CONV SE-LCMFB
FD-CONV FD-LCMFB
Figure 4.1 Diagrams: (a) SE-CONV (b) SE-LCMFB (c) FD-CONV (d) FD-LCMFB.
47
4.2 Design
4.2.1 Design Specifications and Parameters
The parameters listed in were used for theoretical design
calculations.
Table 4.1
Table 4.1 Design Specifications and Parameters.
PARAMETER SPECIFICATION Technology AMI 0.5µm CMOS Lambda (λ) 1λ=0.3µm Threshold Voltages (VTHN,VTHP) 0.75V, 0.95V Transconductance (KPN,KPP) 116µA/V2,38µA/V2 Power Supply (VDD,VSS) ±1.65V Bias Current (IBIAS) 500µA Gain Bandwidth (GB) 100MHz Load Capacitance (CL) 3.0pF
The AMI 0.5µm technology was available for fabrication and was used to maintain
consistency for theoretical calculations, simulation results, and experimental data.
Voltage supply and bias current values were selected based on technology
parameters, power usage, and the load capacitance and gain bandwidth requirement.
The gain bandwidth parameter was defined at 100MHz to provide a reasonable speed
requirement for OTA architecture comparison while allowing accurate measurement
capability using available lab equipment. The load capacitance was defined based on
an approximation of a reasonable on-chip OTA load requirement.
48
4.2.2 Single Ended Conventional OTA
4.2.2.1 Theoretical Design
The conventional OTA, shown in Figure 2.1, was designed based on a gain
bandwidth product of 100MHz and a load capacitance of 3.0pF.
M5
M7
Vdd
Vi(-) Vi(+)
Vcasp
Vcasn
Vss
Ibias
M3 M4
M1 M2
MB1 MB2
M6
M10
M9
M8
Vout
1:KK:1
Figure 4.2 Conventional One Stage Operational Transconductance Amplifier.
The gain bandwidth of the conventional OTA is defined in Equation (2.13) as:
LC
Kgmπ2
2,1=GB (4.1)
Rearranging (4.1), with unity mirror gain (K=1), the following equation can be used
to calculate the transconductance gain of the input differential pair.
LCGBgm π22,1 = (4.2)
49
The transconductance of a MOS transistor can be calculated with the following
expression:
DIL
WKPgm 2= (4.3)
Using this expression, the width of the NMOS differential input pair (M1,2,
) can be determined based on a fixed bias current and predetermined length by
rearranging Equation (4.3) for the following relation:
Figure
2.1
DN IKPLgm
2)( 2,1
22,1
2,1 =W (4.4)
Utilizing a drain current of ID=IBIAS/2=250µA (for VDS,SAT≈0.25V), a length L1=3λ
(L1,2>LMIN=2λ for improved matching) and recognizing KPN=3KPP, Equations (4.2)
and (4.4) can be used to size all transistors for the conventional OTA. Designed
transistor sizes and corresponding VDS,SAT voltages, based on theoretical calculations
(Appendix A), are listed below in Table 4.2.
Table 4.2 Conventional OTA Theoretical Design Transistor Sizes.
TRANSISTORS DIMENSIONS (λ) VDS,SAT (V) M1=M2=M7=M8 184/3 0.26 M3=M4=M5=M6 551/3 0.26 M9=M8/2, (LMIN) 92/2 0.30 M10=M6/2, (LMIN) 276/2 0.30 MB1=MB2=2M1 368/3 0.26
50
Cascoding output transistors (M9,M10 in Figure 2.1) do not require matching design
and were designed with minimum length for speed. Their widths were reduced by a
factor 2 to reduce area.
4.2.2.2 Final Design
Simulation performance and layout considerations resulted in transistor sizing
for matching and performance resulting in final transistor sizing shown in Table 4.3.
Table 4.3 Conventional OTA Final Design Transistor Sizes.
TRANSISTORS DIMENSIONS (λ) VDS,SAT (V) M1=M2 200/3 0.25
M3=M4=M5=M6 500/3 0.28 M7=M8 250/3 0.23
M9 150/2 0.24 M10 300/2 0.30
MB1=MB2 500/3 0.23
Final designed transistor sizes, listed in Table 4.3, are the result of extensive
simulation and are adjusted from theoretical design values in Table 4.2 to provide
increased performance and practical layout topologies with transistor matching via
common-centroid and interdigitation.
4.2.3 Single Ended LCMFB OTA
The SE-LCMFB OTA shown in Figure 1.4 was designed for comparison with
the conventional structure shown in Figure 2.1. For an equivalent comparison, the
SE-LCMFB structure was designed with core transistor sizes identical to those of the
conventional OTA listed in Table 4.3. The core of the SE-LCMFB structure is
51
therefore identical to the conventional structure and the only design required is the
sizing of triode resistance transistors MR1, MR2. As presented in Section 3.5.1, the
VR
MR1 MR2
Vdd
Vi(-) Vi(+)
Vcasp
Vcasn
Vss
M3 M4
M1 M2
M5 M6
M10
M9
M8M7
Vout
B
C
A
Ibias
MB1 MB2
Figure 4.3 Single Ended OTA with Local Common Mode Feedback.
resistance formed by MR1,2 (RMR1,2) can be used to trade slew rate and gain
bandwidth enhancement with phase margin for the class AB SE-LCMFB OTA. The
high frequency pole at nodes A/B (Equation 3.15), maximum output current
(Equation 3.19), and open loop gain (Equation 3.12), are all functions of RMR1,2.
RMR1,2 is programmable, is determined by the control voltage VR (Figure 1.4), and is
given by Equation (3.5) as:
)(
1
2,12,1
PTHRCMRMR VVV
R−−
=β
(4.5)
52
where VR is the control voltage applied at the gate of MR1,2, VC is the constant
voltage at node C, and βMR1,2=KPP(WMR/LMR). For design of MR1,2, a range of
∆RMR1,2 can be determined based on a desired range of phase margin ∆PM.
Simplifying (Equation 3.15) for the position of the high frequency pole (phase
margin) as a function of the resistance RMR (assuming ro1≈ro2≈ro3≈ro4) the following
expression is obtained:
6,52,16,54,3,2,12,1
4.3,2,12,1, 2
12
2
gsMRgsoMR
oMRBpA CRCrR
rRf
ππ≈
+= (4.6)
This relationship indicates a decrease in fpA,B and consequently, a decrease in phase
margin, as RMR1,2 increases. A decrease in RMR1,2 would then lead to an increase in
fpA,B and an increase in the phase margin.
The design method for sizing MR1,2 involves replacing transistors MR1,2
with resistors R1,2 as shown in Figure 4.4.
Vdd
Vi(-) Vi(+)
Vcasp
Vcasn
Vss
Ibias
M3 M4
M1 M2
MB1 MB2
M5 M6
M10
M9
M8M7
R1 R2
Vout
K:1 1:K
B
C
A
Figure 4.4 SE-LCMFB OTA MR1,2 Design Schematic.
53
A parametric step of resistors R1,2 in simulation will then determine a desired range
of resistance (∆RMR1,2) corresponding to a desired range of phase margin
(∆PM≈40°<PM<80°). A parametric simulation of the structure shown in Figure 4.4,
with core transistor sizes listed in , resulted in a resistance range of
(RMR,MIN=200Ω>RMR1,2<RMR,MAX=1000Ω) corresponding to a range of phase margin
(40°<PM<80°).
Table 4.3
WMR and LMR can then be determined analytically by rearranging Equation
(4.5) for the following:
)(
1
2,12,1
2,1
PTHRCPMRMR
MR
VVVKPRLW
−−= (4.7)
The voltage at node C (VC) can be calculated, leaving the control voltage range
∆VR=VRMAX-VRMIN as the unknown variables. Simultaneous functions of Equation
(4.7) can then be solved for WMR1,2/LMR1,2 based on a voltage range ∆VR that
corresponds to the desired resistance range ∆RMR1,2 as shown in Appendix A. Results
are shown below in Table 4.4.
Table 4.4 SE-LCMFB MR1,2 Design Transistor Sizes.
PARAMETER MIN VALUE MAX VALUE Phase Margin (°) 40 80
RMR1,2 (Ω) 200 1000 VR (V) -1.75 -0.75
TRANSISTORS WMR1,2 (λ)/LMR1,2 (λ) MR1,MR2 220/2
54
4.2.4 Fully Differential Conventional OTA
The fully differential dual conventional OTA (FD-CONV) is shown in
and was designed based on the core transistor sizes listed in .
OTA (FD-CONV) is shown in
and was designed based on the core transistor sizes listed in .
Figure
4.5
Figure 4.5 Fully Differential, Dual Shell, Conventional OTA.
Figure
4.5
Figure 4.5 Fully Differential, Dual Shell, Conventional OTA.
Table 4.3Table 4.3
Vdd
Vi(-) Vi(+)
Vcasp
Vcasn
M3 M4
M1 M2
M5 M6
M10
M9
M8M7
Vo(+)
BA Vcasp
Vcasn
Vss
M12M11
M16
M15
M14 M13
Vo(-)
Fully Differential Conventional OTA Common Mode Feedback Circuit
ICM
E
ICM
D
M17
M28M27
ICMICM
M23 M24 M25 M26
M29
Vss
Vdd
M19
Vbiasp
Vcmref Vo(+) Vo(-)
M20
M30
M18
M22M21 Vcasp
Ibias
MB1 MB2
The fully differential architecture contains new shell transistors M12-16 and common
mode feedback transistors M17-30. Shell transistors M12-16 were designed to
match those of the interior shell (K=1) and are listed in .
The fully differential architecture contains new shell transistors M12-16 and common
mode feedback transistors M17-30. Shell transistors M12-16 were designed to
match those of the interior shell (K=1) and are listed in . Table 4.5
Table 4.5 Fully Differential Conventional OTA Shell Transistor Sizes.
Table 4.5
Table 4.5 Fully Differential Conventional OTA Shell Transistor Sizes.
TRANSISTORS DIMENSIONS (λ) M11=M12 500/3 M13=M14 250/3
M15 150/2 M16 300/2
Common mode feedback circuit transistors (M17-30) were designed based on
matching concerns and core transistor sizes and are listed in . Table 4.6
55
Table 4.6 Fully Differential Conventional OTA CMFB Transistor Sizes.
Table 4.6
TRANSISTORS DIMENSIONS (λ) M17=M18=M19=M20 500/3
M21=M22 300/3 M23=M24=M25=M26 500/3 M27=M28=M29=M30 250/3
4.2.5 Fully Differential LCMFB OTA
The FD-LCMFB OTA shown in Figure 4.6 was designed for comparison with
the conventional fully differential structure shown in Figure 4.5.
Figure 4.6 Fully Differential OTA with Local Common Mode Feedback.
VR
MR1 MR2
Vdd
Vi(-) Vi(+)
Vcasp
Vcasn
M3 M4
M1 M2
M5 M6
M10
M9
M8M7
Vo(+)
B
C
A Vcasp
Vcasn
Vss
M12M11
M16
M15
M14 M13
Vo(-)
Fully Differential OTA With Local Common Mode Feedback Common Mode Feedback Circuit
ICM
E
ICM
D
M17
M28M27
ICMICM
M23 M24 M25 M26
M29
Vss
Vdd
M19
Vbiasp
Vcmref Vo(+) Vo(-)
M20
M30
M18
M22M21 Vcasp
Ibias
MB1 MB2
For an equivalent comparison, the FD-LCMFB structure was designed with all
transistor sizes (M1-30) identical to those of the fully differential conventional OTA
as listed in Table 4.3, , and . The design of the FD-LCMFB
structure is therefore identical to the conventional structure and, similar to its single
Table 4.5
56
ended counterpart, the only design required is the sizing of triode resistance
transistors MR1, MR2. Addition of the second shell (M11-16) for the FD-LCMFB
OTA doubles the capacitance at nodes A/B ( ) due to the addition of gate-
source capacitances associated with M11,12, respectively. This increase in
capacitance results in a decrease in the position of the high frequency poles at A/B
and reduces the phase margin. This reduction necessitates redesign of MR1,2 for the
FD-LCMFB OTA following the procedure outlined in Section 4.2.3. Parametric
simulation of the FD-LCMFB OTA, with a range of phase margin equal to that of the
SE-LCMFB OTA (∆PM≈40°<PM<80°), indicated a reduced resistance range
(∆RMR1,2) requirement. WMR1,2/LMR1,2 were selected identical to those of the SE-
LCMFB OTA listed in (WMR1,2/LMR1,2=220/2) and the resistance range was
adjusted with a reduced control voltage range (∆VR) as listed below in Table 4.7.
Figure 4.6
Table 4.4
Table 4.7 FD-LCMFB MR1,2 Design Transistor Sizes.
PARAMETER MIN VALUE MAX VALUE Phase Margin (°) 40 80
RMR1,2 (Ω) 200 650 VR (V) -1.75 -0.90
4.3 Calculation-Simulation-Experimentation
Theoretical values (calculations, Appendix B), simulation results, and
experimental results, for the single ended (SE-CONV, SE-LCMFB) and fully
differential (FD-CONV, FD-LCMFB) architectures, with and without local common
mode feedback are presented in the following sections. Results for all three
evaluation methods (theory, simulation, and experimentation) for all four
57
architectures will be presented in tabular form in each section to provide a quick
reference of results consistency. Tabular data will also emphasize enhancement
factors as a result of the addition of local common mode feedback.
4.3.1 Parameters
The parameters listed in Table 4.8 were used for test and analysis.
Table 4.8 Simulation Parameters.
PARAMETER SPECIFICATION Technology AMI 0.5µm CMOS Power Supply (VDD,VSS) ±1.65V Bias Current (IBIAS) 500µA Load Capacitance (CL) 55pF VCMREF 0V VR (SE-LCMFB) -0.75V VR (FD-LCMFB) -0.90V
The parameters listed above were used consistently for theoretical calculation,
simulation, and experimental measurement configurations for all four devices under
test (SE-CONV, SE-LCMFB, FD-CONV, and FD-LCMFB).
The large load capacitance of 55pF was calculated to match the experimental
test configuration. The load capacitance was determined via several iterations of
experimental measurement and simulation for the single ended conventional OTA.
The experimental load capacitance (CL) can be divided into five dominant
capacitances in parallel: CCHIP (off chip), CBOARD (prototype board), CCABLE (output
coax test cable), CCONN (output coax test cable connectors), and CINST (test instrument
input). The experimental load capacitance is then the summation of these parallel
58
capacitance values. Three experimental and simulation gain bandwidth measurement
test iterations were performed on the SE-CONV architecture in which the
experimental test configuration was identical with the exception of the length of the
output coax test cable. Variation of the cable length (∆CCABLE) provided variation of
the load capacitance (∆CL). This variation, in conjunction with the theoretical GB
equation for the SE-CONV architecture (Equation 2.13), provided a correlation
between simulation and experimental GB values. The net result indicated a load
capacitance of CL=55pF for a six inch coax test cable.
4.3.2 Results and Analysis
4.3.2.1 Open Loop Gain
The open loop gain was calculated and verified via simulation to provide a
reference for simulation validity and to indicate the gain enhancement provided by
the addition of local common mode feedback. Circuit simulation test configurations
for both the (a) single ended and (b) fully differential architectures can be seen in
. Figure 4.7
Figure 4.7 Open-Loop Simulation Circuit Configurations: (a) SE (b) FD.
vIN
+_
VOUT-SE
CL
RF
CF
100M
10u
+_ +
_VO+
CL
VO-vINEDA=0.5
RF
100M
RF
100M
CF
10u
CF
10u
CL
(a) (b)
55p
55p
55p
59
Open loop gain simulation results for the single ended and fully differential
architectures can be seen in Table 4.9 below.
Table 4.9 Open Loop Gain Results.
Open Loop Gain (dB) SE CONV SE LCMFB FD CONV FD LCMFB
THEORY 66 76 72 76 SIMULATION 60 70 69 74
Results indicate modest improvements in the open loop gain as the result of the
addition of local common mode feedback.
4.3.2.2 Gain Bandwidth
Gain bandwidth circuit test configurations for simulation and experimental
measurements for both the (a) single ended and (b) fully differential architectures can
be seen in . Figure 4.8
Figure 4.8 Gain-Bandwidth Test Circuit Configurations: (a) SE (b) FD.
+_ +
_VO+
CL
VO-vIN
RF
470K
RF
470K
CL
RI
470K
RI
470K
CF 10p
CF 10p
CI 10p
CI 10p
55p
55p.01u
.01u
1K
1K
50
50
(a) (b)
vIN
+_
VOUT-SE
CL55p
Input Network
60
Gain bandwidth experimental measurements were made with the spectrum analyzer
(HP 4195A). The FD test configuration, shown in Figure 4.8(b), implements an
inverting, fully differential, voltage follower, via resistors RI/RF and capacitors CI/CF.
CI and CF provide compensation for the introduction of the feedback (RF) and input
resistors (RI) loading the OTA structures. The input network (also shown in
(b)) formed by two 10nF capacitors, two 50Ω, and two 1KΩ resistors is used
consistently throughout fully differential testing configurations and was realized to
create complementary input signals by forcing floating function generator and
spectrum analyzer inputs. Fifty ohm resistors provide a ground reference at the input.
The 10nF capacitors and 1KΩ resistors form a (low corner frequency) high pass filter
(f3dB=16KHz) at each input, blocking DC and maintaining phase consistency for the
floating input signals.
Figure
4.8
GB results for theoretical calculations, simulation, and experimental
measurements can be seen below in . Enhancement ratios provide quick
reference for the improvements in bandwidth as a result of the addition of local
common mode feedback for both single ended and fully differential structures.
Table 4.10
Table 4.10 Gain Bandwidth Results.
GAIN BANDWIDTH (MHz) SE CONV SE LCMFB FD CONV FD LCMFB
THEORY 5.7 18.9 5.7 10.6 ENHANCEMENT 3.32 1.86
SIMULATION 5.9 25 5.6 10.6 ENHANCEMENT 4.24 1.89
EXPERIMENTAL 5.7 19.5 5.1 9.1 ENHANCEMENT 3.42 1.78
61
Results indicate a factor greater than 3 increase in GB for the single ended OTA
structures and a factor of nearly 2 increase for the fully differential structures.
4.3.2.3 Maximum Output Current
Maximum output current circuit test configurations for simulation and
experimental measurements for both the (a) single ended and (b) fully differential
Figure 4.9 Maximum Out t
architectures can be seen in Figure 4.9.
Test Circuit Configurations: (a) SE (b) FD.
aximum output current results for theoretical calculations, simulation, and
ts.
100
+_ +
_vIN+
VO+
VO-
100RL
100RL
vIN
+_
VOUT-SE
RL
(a) (b)
vIN-
put Curren
M
experimental measurements can be seen below in Table 4.11.
Table 4.11 Maximum Output sulCurrent Re
SE CONV SE LCMFB FD CONVMAXIMUM OUTPUT CURRENT (mA)
FD LCMFB THEORY 1.95 0.5 1.95 0.5
E 3 9 3.9 MULATION 0.48 2.34 0.48 2.08
ENHANCEMENT 4.88 4.33 XPERIMENTAL 0.47 1.98 0.48 1.84
ENHANCEMENT 4.21 3.83
ENHANC MENT .SI
E
62
Enhancement ratios provide quick reference for the improvements in output current
t
ate
uit test configurations for simulation and experimental
measur ures can
lew rate results for theoretical calculations, simulation, and experimental
measurements can be seen below in Table 4.12.
ent ratios provide quick reference for the improvements in output current
t
ate
uit test configurations for simulation and experimental
measur ures can
lew rate results for theoretical calculations, simulation, and experimental
measurements can be seen below in Table 4.12.
as a result of the addition of local common mode feedback for both single ended and
fully differential structures. Results indicate a factor of 4 increase in the maximum
output current for both the single ended and fully differential architectures as a resul
of the addition of local common mode feedback. Maximum output currents larger
than four times the bias current indicate class AB characteristics for the structures
with LCMFB.
4.3.2.4 Slew R
as a result of the addition of local common mode feedback for both single ended and
fully differential structures. Results indicate a factor of 4 increase in the maximum
output current for both the single ended and fully differential architectures as a resul
of the addition of local common mode feedback. Maximum output currents larger
than four times the bias current indicate class AB characteristics for the structures
with LCMFB.
4.3.2.4 Slew R
Slew rate circSlew rate circ
ements for both the (a) single ended and (b) fully differential architect
be seen in Figure 4.10.
ements for both the (a) single ended and (b) fully differential architect
be seen in Figure 4.10.
Figure 4.10 Slew Rate Test Circuit Configurations: (a) SE (b) FD. Figure 4.10 Slew Rate Test Circuit Configurations: (a) SE (b) FD.
+_ +
_VO+
CL
VO-vIN
RF
470K
470K
CL
RI
470K
RI
470K
CF 10p
CI 10p
CI 10p
55p
55p.01u
.01u
1K
1K
50
50
(a) (b)
vIN
+_
VOUT-SE
CL55p
RF
CF 10p
SS
63
Table 4.12 Slew Rate Results.
SLE (VW RATE
9.1 35.3
/µs) SE CONV SE LCMFB FD CONV FD LCMFB
THEORY 18.2 70.7 ENHANCEMENT 3.88 3.88
SIMULATION 8.6 36.5 15.1 77.1 ENHANC MENT .2 .1E 4 4 5 1
ERIMENT 8.2 34.6 17.5 67 ENHANCEMENT 4.22 3.83
ancement ratios ind 4 incr rrespo
EXP AL
Enh icate a factor ease in the slew rate (co nding to a
ctor of 4 increase in maximum output current in Section 4.3.2.3) for both the single
s, simulation, and experimental
m Table 4.13.
fa
ended and fully differential architectures as a result of the addition of local common
mode feedback. Class AB operation in the LCMFB configurations provides large
dynamic currents for increased slew rate capability.
4.3.2.5 Static Power Dissipation
Static power results for theoretical calculation
measure ents can be seen below in
Table 4.13 Static Power Dissipation Results.
STATIC POW IPER DISS
4.95 4.95 9.90
ATION (mW) SE CONV SE LCMFB FD CONV FD LCMFB
THEORY 9.90 ENHANCEMENT 1.00 1.00
SIMULATION 9.42 4.83 4.84 9.42 E 0 9 1 0
ERIMENT 4.91 4.98 9.91 9.92 ENHANCEMENT 0.98 0.99
ENHANC MENT .9 .0EXP AL
64
Results indicate equal static p issipation for single ended and fully differential
rchitectures with and without local common mode feedback.
Gain and phase margin simulation results can be seen below in Table 4.14.
Table 4.14 Gain and Phase Margin Simulation Results.
ower d
a
4.3.2.6 Gain and Phase Margins
GAIN MARGIN (dB) AND PHASE MARGIN (°) SE CONV SE LCMFB FD CONV F D LCMFB
°) 88.3 66.1 84 GM (dB) 25.2 15.3 20.6 15.6 PM ( 78.5
Simulat e effec e applic local co n mode feedback via
e reduction in gain and phase margin for both the single ended and fully differential
rchitectures. LCMFB can be used to trade off slew rate and gain bandwidth
enhancement with gain and phase margin (stability).
Systematic offset voltage simulation results can be seen below in Table 4.15.
Table 4.15 Offset Voltage Simulation Results.
ions indicate th t of th ation of mmo
th
a
4.3.2.7 Input Offset Voltage
OFFSET VOLTAGE (V) SE CONV SE LCMFB FD CONV FD LCMFB
VOS 15.9m 3.2m 1.9p 8.3p
Relatively la fset vol s c
e non-symmetric structure of the shell structures (Figures 2.1, 3.1). This non-
mmetric shell structure provides increased speed at the cost of increased offset.
rge of tages for the ingle ended ar hitectures can be attributed to
th
sy
65
Results indicate a reduction in the offset voltage with the addition of LCMFB for the
single ended structures and a negligible increase for the fully differential
architectures.
4.3.2.8 Harmonic Distortion
Harmonic distortion simulation results are shown in Table 4.16 below.
Table 4.16 Harmonic Distortion Simulation Results.
Nth Order HD (dB) AND THD (%) SINGLE ENDED STRUCTURES
VIN(1KHz) SE-CONV SE-LCMFB
2nd th THD 3rd 4th THD 2nd 3rd 4200mV -87.09 -104.01 -105.28 0.0046 -80.89 -95.49 -105.13 0.0092
V 9 -78.03 0.0583 -62.39 -6800mV -61.85 -59.87 -80.10 0.1314 -49.21 -52.85 -56.18 0.4556
FULLY D STRUCTURES IFFERENTIAL VIN
200mV -97.73 -104.99 -106.83 0.0018 -97.71 -104.94 -106.84 0.0018 400mV -97.40 -125.55 -105.84 0.0017 -97.34 -123.79 -105.87 0.0017
V800mV -96.92 -7 5 0.0148 -97.00 - 4 0.099 7.22 -105.0 80.74 -104.7
armonic istortio simulations for al four stru tures w e config red with 1KHz
nusoidal nput sig l with a plitude 00, 400 600, an 800mV. able
400mV -78.27 -83.56 -96.25 0.0140 -72.84 -84.07 -94.05 0.0238 600m -67.21 -68.9 8.23 -72.96 0.0891
(1KHz) FD-CONV FD-LCMFB 2nd 3rd 4th THD 2nd 3rd 4th THD
600m -95.63 -90.37 -102.84 0.0037 -95.52 -92.36 -102.85 0.0032
H d n l c er u a
si i na m values of 2 , d T
.16 provides normalized harmonic distortion data in dB for the first three harmonics 4
at all four applied amplitudes and corresponding percentage THD values. Results
66
indicate an increase in distortion with the addition of LCMFB for both single ended
and fully differential architectures.
4.3.2.9 Noise
Total input noise spectral de
ferential architectures.
4.3.2.9 Noise
Total input noise spectral density plots for all four OTA architectures are
4.11((a) SE-CONV, SE-LCMFB (b) FD-CONV, FD-LCMFB).
nsity plots for all four OTA architectures are
4.11((a) SE-CONV, SE-LCMFB (b) FD-CONV, FD-LCMFB). shown in Figureshown in Figure
67
Figure 4.11 OTA Total Input Noise Simulation Plots (a) SE (b) FD.
Tot
al In
put N
oise
(uV
)
Figure 4.11 OTA Total Input Noise Simulation Plots (a) SE (b) FD.
Tot
al In
put N
oise
(uV
)
1 10 100 1k 10k 100k 1M 10M 100MFrequency (Hz)
0
5
10
15
20
25
30
35
40
45
50
55
60
FD-LCMFB
FD-CONV
FULLY DIFFERENTIAL OTA TOTAL INPUT NOISE(a)
(b)
1 10 100 1k 10k 100k 1M 10M 100MFrequency (Hz)
0
5
10
15
20
25
30
35
40
45
50
Tot
al In
put N
oise
(uV
)
SE-LCMFB
SE-CONV
55
60
65SINGLE ENDED OTA TOTAL INPUT NOISE
Input noise results plots show a decrease in noise as a result of the addition of e results plots show a decrease in noise as a result of the addition of local
Table 4.17 Total Input Noise at 10MHz.
local
Table 4.17 Total Input Noise at 10MHz.
common mode feedback. Table 4.17 below lists total noise extracted from spectral
density plots (Figure 4.11)
common mode feedback. Table 4.17 below lists total noise extracted from spectral
density plots (Figure 4.11) at 10 MHz for all four OTA structures. at 10 MHz for all four OTA structures.
INPUT NOISE AT 10MHz SE-C NV FD-LCMFB ONV SE-LCMFB FD-CO
20 14 18 15 NOISE (µV)
esults indicate a reduction in noise as a result of the addition of LCMFB. This
4.3.2.10 Common Mode Feedback Characterization
ferential structures were
charact
uit test
R
reduction is the result of increased gain as outlined in Section 3.5.4.3.
Common mode feedback circuits for the fully dif
erized via an AC open loop simulation to verify their open loop gain,
bandwidth, gain margin, and phase margin. The common mode feedback circ
configuration is shown below in Figure 4.12.
Figure 4.12 CMFB Open Loop Characterization Simulation Circuit Configuration.
+_ +
_VO+
CT
VO-
RF
500K
500K
RT
RI
500K
RI
500K 100M
100M
CT
RT CMFB VCM,REF
CMIN-
CMIN+
VCM,REF
CMOUTCMIN
100u
100uCL
CL
RF
68
Simulation results for the CMFB circuits for both fully differential architectures are
shown below in Table 4.18.
Table 4.18 Common Mode Feedback Circuit Simulation Results.
COMMON MODE FEEDBACK CIRCUIT CHARACTERIZATION AOL(dB) GB(MHz) GM(dB) PM(º)
FD-CONV 54 3.9 28.6 88.7 FD-LCMFB 54 3.9 28.6 88.7
4.3.2.11 Silicon Area
Layout figures and dimensions for the single ended and fully differential OTA
structures with and without LCMFB are shown in Figure 4.13 below.
SE-CONV SE-LCMFB
Dimensions: 216µm*55µm=11880µm2
(a)
Dimensions: 253µm*57µm=14421µm2
(b)
FD-CONV FD-LCMFB
Dimensions: 588µm*55µm=32340µm2
(c)
Dimensions: 646µm*57µm=36822µm2
(d)
Figure 4.13 Layout (a) SE-CONV (b) SE-LCMFB (c) FD-CONV (d) FD-LCMFB.
69
Results indicate only a 15-20% increase in silicon area as a result of the addition of
local common mode feedback transistors.
4.4 Conclusions
Table 4.19
Table 4.19 Analysis Summary Results.
Table 4.19
below provides a summary of characteristic improvement factors
for the single ended and fully differential architectures with local common mode
feedback versus their conventional counterparts. The data represents a compilation of
the benefits and costs of the addition of LCMFB as presented in the previous sections.
ANALYSIS SUMMARY
SINGLE ENDED DIFFERENTIAL
PARAMETER FACTOR IMPROVEMENT
FACTOR IMPROVEMENT
GB 4 2
IOUTMAX 4 4
SR 4 4
PSTATIC 1 1
PARAMETER EFFECT OF LCMFB EFFECT OF LCMFB
GM/PM PROGRAMMABLE PROGRAMMABLE
VOS DECREASE DECREASE
THD INCREASE INCREASE
NOISE DECREASE DECREASE
AREA 15-20% INCREASE 15-20% INCREASE
illustrates several performance enhancing benefits of LCMFB versus the
conventional OTA architecture including class AB (IOUTMAX) operation which
70
provides enhancement in slew rate, and gain bandwidth, with equal static power
dissipation and reduced noise. Implementation of LCMFB with MOS transistors
MR1,MR2, ( , ) provides programmable gain (via the control
voltage VR), allowing utilization of the same OTA for multiple applications. MR1,2
provide the ability to trade slew rate and gain bandwidth enhancement for phase
margin. The benefits of the LCMFB structure are considerable for a negligible
increase in harmonic distortion and silicon area.
Figure 1.4 Figure 4.6
71
5 APPLICATIONS
5.1 Fully Differential Charge Scaling Digital-Analog Converter
As a test application requiring high slew rate performance, an 8-bit, fully
differential, charge-scaling, digital-to-analog converter was implemented and
simulated for both the FD-CONV (Figure 2.10) and FD-LCMFB (Figure 3.9)
architectures. The designed OTA structures function as the core amplifier for the
Figure 5.1 Fully Differential C ling Ana
charge scaling architecture shown in Figure 5.1 below.
log-Digital Converter.
The fully differential, charge-scaling structure utilizes dual reference voltages
REF+,
F= REF )
e c on
+_ +
_
VO+
VO-
CF=(2N)CU
RESET
CF=(2N)CU
RESET
bN-1
CLK
(2N)CU2
b1
CLK
(2N)CU
b0
CLK
CU (2N-1)CU
bN-1CLK
b1CLK
b0CLK
CUCU
VREF+
VREF-
(2N)CU(2N-1)
(2N)CU2
VREF+
VREF-
harge Sca
(V VREF-) at each input for a full scale, differential, reference voltage equal to
VRE 2(V +-VREF-). Based on the charge/voltage relation for a capacitor (C=Q/V
th harge the scaling capacitors, in terms of the unit capacitance (CU), the digital
input code (b0-b7), and the full scale reference voltage (VREF), can be defined as:
222 UN
UN
UN CCC
++++= −−− 2...
22 122110 NNNUREF bbbCbVQ (5.1)
72
The output voltages, in terms of VREF are then given by:
++++−=−= −
−−−+ 2... 1
22
110 N
NNNREFOObbbbVVV
222 (5.2)
The differential output voltage is given by VO=VO+-VO-, and the maximum output
voltage of the converter, with respect to VREF, is given by:
NREFO VV −= REFMAX V2
(5.3)
The DAC shown in Figure 5.1 was implemented for a comparative, application
specific, reference to the operation characteristics of both fully differential amplifiers.
.1.
5.1.1 Simulation Specifications and Parameters
Simulation parameters and design specifications for the implemented charge
scaling DAC (Figure 5.1) are shown below in Table 5
Table 5.1 Fully Differential Charge Scaling DAC Design Parameters.
AMETER SPPAR ECIFICATION Technology AMI 0.5µm CMOS Power Supply (VDD,VSS) ±1.65V Bias Current (I ) 500µA BIAS
Number of Bits (N) 8 Reference Voltage (VR F=E 2(VREF+-VREF-) 2.0 Unit Capacitance (CU) 0.25pF Feedback Capacitance (CF=256*CU ) 64pF Resolution (R=VREF/2N) 7.8125mV VO (2(VREF+-VREF-)MAX -Resolution) 1.992V VR (FD-LCMFB) -0.9V
73
5.1.2 Results and Analysis
The charge scaling DAC structure in Figure 5.1 was simulated with both fully
-CONV (Section 2.6), FD-LCMFB (Section 3.6))
with id
l
, a L
differential OTA structures (FD
74
Figure 5.2 FD-CONV-DAC Analysis Plots (a) DNL (b) INL.
0 50 100 150 200 250-1
-0.8
-0.6
-0.4
-0.2
0
0.2
Digital Input Code(Decimal)(a)
DN
L(LS
Bs)
0 50 100 150 200 250-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Digital Input Code(Decimal)(b)
INL(
LSB
s)
INL vs. Input Code
INLMAX(LSBs)=0.71283
entical parameters as defined in Table ll digital scale transient
simulation with a clock frequency (fCLK) of 1MHz provided data for analysis of
standard DAC specifications including: ial nonlinearity (DNL), integra
nonlinearity (INL), offset, gain error nd settling time. Figure 5.2 shows (a) DN
and (b) INL plots for the FD-CONV-DAC.
0.6
0.8
1DNL vs. Input Code
DNLMAX(LSBs)=0.5104
5.1. A fu
different
0.4
Annotated DNL and INL values are listed on the corresponding plots and indice listed on the corresponding plots and indicate the
Table 5.2 summarizes simulated DAC specifications for both the conventional
and local common mode feedback configurations. Listed characteristics were
determined via a DAC Matlab script.
ate the
Table 5.2 summarizes simulated DAC specifications for both the conventional
and local common mode feedback configurations. Listed characteristics were
determined via a DAC Matlab script.
maximum error measured in simulation. Figure 5.3 shows (a) DNL and (b) INL plots
for the FD-LCMFB-DAC.
maximum error measured in simulation. Figure 5.3 shows (a) DNL and (b) INL plots
for the FD-LCMFB-DAC.
Figure 5.3 FD-LCMFB-DAC Analysis Plots (a) DNL (b) INL. Figure 5.3 FD-LCMFB-DAC Analysis Plots (a) DNL (b) INL.
0 50 100 150 200 250-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
Digital Input Code(Decimal)(a)
DN
L(LS
Bs)
DNLMAX(LSBs)=0.4624
0 50 100 150 200 250-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Digital Input Code(Decimal)(b)
INL(
LSB
s)
INL vs. Input Code
INLMAX(LSBs)=0.33578
0.8
1DNL vs. Input Code
75
Table 5.2 Simulated DAC Specifications Summary.
PARAMETER FD-CONV-DAC FD-LCMFB-DAC
INL(LSB) DNL(LSB) 0.5104 0.4624
0.7128 0.3358
Offset(V) 0.24m 1.3m
Gain Error(V/LSB) 14.7u 2.16u
Settling Time(sec) 236n 100n
PSTATIC(W) 9.4m 9.4m
cifications recorded 5.2 identify im ents in
e diff (with the exception of offset voltage), with
Spe in Table provem all aspects of
the performance of th erential DAC
qual static power dissipation, due to the addition of local common mode feedback.
Settling
e
76
Figure 5.4 Transient, Full Scale Settling Time Response.
450 500 550 600 650 700 750 800TIME (ns)
-1.5
-1.0
-0.5
0.0
0.5
Vol
tage
(V) (
Vo+
,Vo-
)
time values (Table 5.2) were measured at 99.9% (10 bit resolution) of a full
scale (VREF=2V) input pulse shown in Figure 5.4.
1.5
2.0
1.0FD-CONV-DAC
FD-DAC Settling Response
FD-LCMFB-DAC
The LCMFB configuration demonstrates more than a factor of 2 improvement
in set
accuracy
5.2 Proposed Applications
s require high gain bandwidth values, high slew rates,
and at t
h
tling time. The addition of local common mode feedback to the fully
differential, charge-scaling, digital-to-analog converter, results in increased
and speed with equal static power dissipation.
Battery powered system
he same time very low static power dissipation. The class AB characteristics
of both the single ended and fully differential OTA structures with local common
mode feedback match these requirements. The programmability of the LCMFB
architecture, in conjunction with its ability to generate large dynamic currents wit
low static power dissipation, makes it an ideal choice for analog filtering, data
conversion, and wireless applications.
77
APPENDICES
APPENDIX A
DESIGN CALCULATIONS
80
L5 L1:=W5 500=W5 K W3⋅:=
L4 L1:=W4 500=W4 W3:=L3 L1:=W3 500:=
L2 L1:=W2 200=W2 W1:=L1 3:=W1 200:=DESIGNED TRANSISTOR SIZES:
L6 L5:=W6 W5:=L5 L4:=
LMB2 3:=WMB2 500=WMB2 WMB1:=LMB1 3:=WMB1 500:=
L10 2:=W10 300:=L9 2:=W9 150:=
L8 L1:=W7 500=W8 W7:=L7 L1:=W7 500:=
L6 L1:=W6 500=W6 K W4⋅:=
IBIAS 500 10 6−⋅:=
DESIGN SPECIFICATIONS:
Conventional OP-AMP Design (Hand Calculations):
K 1:=L1 3:=CJp 1.42 10 3−⋅:=CJn 9.3 10 4−
⋅:=
CGDOp 1.10 10 10−⋅:=CGDOn 1.30 10 10−
⋅:=Coxpr 4.6 10 15−⋅:=
Vthp 0.95:=KPp 38 10 6−⋅:=Vthn 0.75:=KPn 116 10 6−
⋅:=
Parameters:
DESIGN AND SIMULATION CALCULATIONS: CMOS 0.5um TECHNOLOGY
SINGLE-ENDED CONVENTIONAL OTA (FIGURE 2.1):
W5 W4:=
L4 L3:=W4 W3:=W3 551.337=L3 L2:=W3 3W2:=
L2 L1:=W2 W1:=W1 183.779=W1gm1( )2 L1⋅
2KPn ID⋅
:=
gm1 1.885 10 3−×=gm1 GB 2⋅ π⋅ CLD⋅:=
DESIGN CALCULATIONS:
CLD 3.0 10 12−⋅:=GB 100 106
⋅:=ID 2.5 10 4−×=ID
IBIAS2
:=
APPENDIX B
THEORETICAL ANALYSIS CALCULATIONS
82
AOL_VV 2 103×=
AOL_VV gm1 ROUT⋅:=
ROUT 1.017 106×=ROUT gm9 ro9⋅ ro8⋅( ) 1− gm10 ro10⋅ ro6⋅( ) 1−
+
1−:=
gm10 1.688 10 3−×=gm10 2 KPp⋅
W10L10
K⋅ ID⋅:=
gm9 2.086 10 3−×=gm9 2 KPn⋅
W9L9
⋅ K⋅ ID⋅:=
ro10 2.222 104×=ro10
1λ10. K⋅ ID⋅
:=ro6 4.444 104×=ro6
1λ6. K⋅ ID⋅
:=
ro9 2.5 104×=ro9
1λ9. K⋅ ID⋅
:=ro8 5 104×=ro8
1λ8. K⋅ ID⋅
:=
THEORY-SIMULATION-EXPERIMENTAL PARAMETERS:
VDD 1.65:= VSS VDD−:= IBIAS 500 10 6−⋅:= ID
IBIAS2
:= CL 55 10 12−⋅:= K 1:=
THEORETICAL ANALYSIS:
OPEN LOOP GAIN (EQ: 2.7):
gm1 2 KPn⋅W1L1
⋅ ID⋅:= gm1 1.966 10 3−
×=
Output Resistance (EQ 2.5):
Channel Length Modulation Parameters Of Output Transistors:
λ8. 0.08:= λ9. 0.16:= λ6. 0.09:= λ10. 0.18:=
83
PSTATIC 4.95 10 3−×=PSTATIC VDD VSS−( )IBIAS 2 K+( )⋅:=
STATIC POWER DISSIPATION (EQ: 2.24):
SR 9.091=SR
IOUTMAXCL
1⋅ 10 6−⋅:=
SLEW RATE (EQ: 2.15):
IOUTMAX 5 10 4−×=
IOUTMAX K IBIAS⋅:=
MAXIMUM OUTPUT CURRENT (EQ: 2.14):
GB 5.69 106×=
GB Kgm1
2 π⋅ CL⋅⋅:=
GAIN BANDWIDTH (EQ: 2.13):
f3dB 2.845 103×=
f3dB1
2 π⋅ ROUT⋅ CL⋅:=
Dominant Pole fout=f3dB (EQ: 2.12):
fA 3.421 108×=fA
gm32 π⋅ Cgs3⋅ 1 K+( )⋅
:=
High Frequency Pole fA (EQ: 2.10):
gm3 1.78 10 3−×=
gm3 2 KPp⋅W3L3
⋅ ID⋅:=
Cgs3 4.14 10 13−×=Cgs3
23
W3⋅ L3⋅ Coxpr⋅ 0.3( )2⋅:=
AC Analysis:
84
RMRMAX 2.01 103×=
RMRMAX1
KPpWMRLMR
⋅ VC VRMAX−( ) Vthp− ⋅
:=
RMRMIN 213.788=RMRMIN
1
KPpWMRLMR
⋅ VC VRMIN−( ) Vthp− ⋅
:=
Vthp 1.05:=Body Effected Threshold Voltage:LMR 2:=WMR 220:=
Select W MR/LMR Ratio Based On RWL And LMIN=2λ:
RWL 114.044=RWL
RWL1 RWL2+( )2
:=
RWL2 120.15=RWL2
1RMRMAX KPp VC VRMAX−( ) Vthp− ⋅⋅
:=
RWL1 107.938=RWL1
1RMRMIN KPp VC VRMIN−( ) Vthp− ⋅⋅
:=
VR Selection Determines RWR=WWR/LWR Based On Triode Resistance (EQ;3.5):
VRMAX 0.75−:=VRMIN 1.75−:=
Select Appropriate Control Voltage (VR) Range (based on voltage rails):
RMRMAX 1000:=RMRMIN 200:=
Parametric Sweep To Determine Range of R Corresponding To: 40>PM>80:
VC 0.419=VC VDD
IBIAS L3⋅( )KPp W3⋅
Vthp+
−:=
Calculate Voltage At Node C (Figure 3.1)
LCMFB OTA: MR1,2 DESIGN:
SIMULATION PARAMETERS MATCH CONVENTIONAL PARAMETERS
DESIGNED CORE TRANSISTOR SIZES: MATCH CONVENTIONAL DESIGN
HAND CALCULATIONS: MATCH CONVENTIONAL DESIGN
SINGLE-ENDED LCMFB OTA (FIGURE 3.2):
85
ACOREMAX 3.675=
Output Shell Gain (EQ: 3.11):
gm5 2 KPp⋅W5L5
⋅ ID⋅:= gm5 1.78 10 3−
×=
Output Resistance (Defined Above) (EQ 2.5, 3.10):
ROUT 1.017 106×=
ASHELL gm5 ROUT⋅:= ASHELL 1.81 103×=
Open Loop Gain (EQ 3.12):
AOL_VV_MIN ACOREMINASHELL⋅( ):= AOL_VV_MIN 754.726=
AOL_dB_MIN 20 log AOL_VV_MIN( )⋅:= AOL_dB_MIN 57.556=
AOL_VV_MAX ACOREMAX ASHELL⋅( ):= AOL_VV_MAX 6.651 103×=
AOL_dB_MAX 20 log AOL_VV_MAX( )⋅:= AOL_dB_MAX 76.458=
THEORETICAL ANALYSIS:
OPEN LOOP GAIN (EQ: 3.12):
Differential Input Stage Gain (EQ: 3.9):
gm1 2 KPn⋅W1L1
⋅ ID⋅:= gm1 1.966 10 3−
×=
λ1 0.06:= ro11
λ1 ID⋅:= ro1 6.667 104
×= ro3 ro6:= ro3 4.444 104×=
RAMIN ro1( ) 1− ro3( ) 1−+ RMRMIN
1−+
1−:= RAMIN 212.088=
RAMAX ro1( ) 1− ro3( ) 1−+ RMRMAX
1−+
1−:= RAMAX 1.869 103
×=
ACOREMIN gm1 RAMIN⋅:= ACOREMIN 0.417=
ACOREMAX gm1 RAMAX⋅:=
86
PSTATIC 4.95 10 3−×=PSTATIC VDD VSS−( )3IBIAS:=
STATIC POWER DISSIPATION (EQ: 2.24):
SR 35.341=SR
IOUTMAXCL
1⋅ 10 6−⋅:=
SLEW RATE (EQ: 2.15):
IOUTMAX 1.944 10 3−×=
IOUTMAXKPp
2
W5L5
⋅
2 ID⋅ L3⋅
W3 KPp⋅
IBIAS2
RMRMAX⋅+
2
:=
MAXIMUM OUTPUT CURRENT (EQ: 3.19):
GBMAX 1.893 107×=
GBMAXgm1 gm5⋅ RAMAX⋅
2π CL⋅:=
GBMIN 2.148 106×=
GBMINgm1 gm5⋅ RAMIN⋅
2π CL⋅:=
GAIN BANDWIDTH (EQ: 3.18):
f3dB 2.845 103×=
f3dB1
2 π⋅ ROUT⋅ CL⋅:=
Dominant Pole fout (EQ: 3.17):
fAMAX 1.813 109×=fAMAX
12 π⋅ RAMIN⋅ Cgs5⋅
:=
fAMIN 2.057 108×=fAMIN
12 π⋅ RAMAX⋅ Cgs5⋅
:=
High Frequency Pole fA (EQ: 3.15):
Cgs3 4.14 10 13−×=Cgs5
23
W5⋅ L5⋅ Coxpr⋅ 0.3( )2⋅:=
AC Analysis:
87
PSTATIC 9.9 10 3−×=PSTATIC VDD VSS−( ) 2 IBIAS⋅ 2 K+( )⋅ ⋅:=
STATIC POWER DISSIPATION (EQ: 2.24):
SR 18.182=SR 2
IOUTMAXCL
1⋅ 10 6−⋅:=
Differential:
SLEW RATE (EQ: 2.15):
IOUTMAX 5 10 4−×=
IOUTMAX K IBIAS⋅( ):=
Differential:
MAXIMUM OUTPUT CURRENT (EQ: 2.14):
GB 1.138 107×=
GB 2Kgm1
2π CL⋅⋅:=
GAIN BANDWIDTH:
AOL_dB 72.04=AOL_dB 20 log AOL_VV( )⋅:=
AOL_VV 3.999 103×=
AOL_VV 2 gm1 ROUT⋅( ):=
OPEN LOOP GAIN:
THEORETICAL ANALYSIS:
SIMULATION PARAMETERS MATCH CONVENTIONAL PARAMETERS
DESIGNED CORE TRANSISTOR SIZES: MATCH CONVENTIONAL DESIGN
HAND CALCULATIONS: MATCH CONVENTIONAL DESIGN
FULLY-DIFFERENTIAL CONVENTIONAL OTA:
88
AOL_dB_MAX 77.464=AOL_dB_MAX 20 log AOL_VV_MAX( )⋅:=
AOL_VV_MAX 7.468 1×=AOL_VV_MAX 2 ACOREMAX ASHELL⋅( )⋅:=
AOL_dB_MIN 63.97=AOL_dB_MIN 20 log AOL_VV_MIN( )⋅:=
AOL_VV_MIN 1.579 10×=AOL_VV_MIN 2 ACOREMINASHELL⋅( )⋅:=
ACOREMAX 2.063=ACOREMAX gm1 RAMAX⋅:=
ACOREMIN 0.436=ACOREMIN gm1 RAMIN⋅:=
RAMAX 1.049 103×=RAMAX ro1( ) 1− ro3( ) 1−
+ RMRMAX1−
+
1−:=
RAMIN 221.925=RAMIN ro1( ) 1− ro3( ) 1−
+ RMRMIN1−
+
1−:=
RMRMAX 1.092 103×=
RMRMAX1
KPpWMRLMR
⋅ VC VRMAX−( ) Vthp− ⋅
:=
RMRMIN 223.788=RMRMIN
1
KPpWMRLMR
⋅ VC VRMIN−( ) Vthp− ⋅
:=
VRMIN 1.75−=VRMAX 0.9−:=Vthp 1.1:=Body Effected Threshold Voltage:OPEN LOOP GAIN:
THEORETICAL ANALYSIS:
SIMULATION PARAMETERS MATCH CONVENTIONAL PARAMETERS
DESIGNED CORE TRANSISTOR SIZES: MATCH CONVENTIONAL DESIGN
HAND CALCULATIONS: MATCH CONVENTIONAL DESIGN
FULLY-DIFFERENTIAL LCMFB OTA:
89
GAIN BANDWIDTH:
GBMINgm1 gm5⋅ RAMIN⋅
2π CL⋅:= GBMIN 2.247 106
×=
GBMAXgm1 gm5⋅ RAMAX⋅
2π CL⋅:= GBMAX 1.062 107
×=
MAXIMUM OUTPUT CURRENT:
IOUTMAX KPpW5L5
⋅
2ID L3⋅
W3 KPp⋅
IBIAS2
RMRMAX⋅+
2
:= IOUTMAX 1.944 10 3−×=
SLEW RATE:
SR 2IOUTMAX
CL
1⋅ 10 6−⋅:=
SR 70.695=
STATIC POWER DISSIPATION:
PSTATIC VDD VSS−( )6IBIAS:= PSTATIC 9.9 10 3−×=
APPENDIX C
MICROGRAPHS
Micrographs of all four OTA structures are shown in figures C.1(SE-CONV),
C.2(SE-LCMFB), C.3(FD-CONV), C.4(FD-LCMFB) below.
Figure C.1 Micrograph of Fabricated SE-CONV Structure (11880µm2).
Figure C.2 Micrograph of Fabricated SE-LCMFB Structure (14421µm2).
Figure C.3 Micrograph of Fabricated FD-CONV Structure (32340µm2).
Figure C.4 Micrograph of Fabricated FD-LCMFB Structure (36822µm ). 2
91
A Micrograph of the fabricated 0.5um MOSIS test chip is shown in Figure
C.5 below.
Figure C.5 Micrograph of Fabricated 0.5um CMOS Test Chip.
92
APPENDIX D
INTERNET LINKS
MOSIS Spice Transistor Model Files Can Be Found At:
http://www.mosis.com/Technical/Testdata/
Thesis Data, Files, and Reference Information Including:
Thesis: Document/Presentation Files Simulation: Schematics/Simulation Command Files Electronics Letters: Publication File MWSCAS 2002: Publication\Presentation Files ISCAS 2002: Publication\Presentation Files
Can Be Found At:
http://www.ece.nmsu.edu/vlsi/Research/Theses/Michael-Holmes/Michael-Holmes.htm
94
REFERENCES [1] J. Harrison and N. Weste, “350MHz OpAmp-RC Filter in 0.18um CMOS,”
Electronics Letters, vol. 38 (6), pp. 259-260, March 2002. [2] J. Ramirez-Angulo and M. Holmes, “A Simple Technique to Significantly
Enhance Slew Rate and Bandwidth of One-Stage CMOS Operational Amplifiers,” Proceedings of the 2002 International Symposium on Circuits and Systems, Phoenix, Arizona, May 2002.
[3] M. Holmes, J. Ramirez-Angulo, and R.G. Carvajal, “New Architectures of
Class AB CMOS and BICMOS Operational Amplifiers with Local Common Mode Feedback,” Proceedings of the 2002 Midwest Symposium on Circuits and Systems, Tulsa, Oklahoma, August 2002.
[4] R. Baker, H. Li, and D. Boyce, CMOS Circuit Design, Layout, and Simulation,
New York: IEEE Press, 1st ed., 1997, Pages: 617-679. [5] D. Johns and K. Martin, Analog Integrated Circuit Design, New York: John
Wiley & Sons, 1st ed., 1997, Pages: 181-204. [6] P. Gray, P. Hurst, S. Lewis, and R. Meyer, Analysis and Design of Analog
Integrated Circuits, New York: John Wiley & Sons, 4th ed., 2001, Pages: 748-802, 808-856.
[7] B. Razavi, Design of Analog CMOS Integrated Circuits, New York: McGraw-
Hill, 1st ed., 2001, Pages: 232-233.
95