a 10-bit, 100 ms/s analog-to-digital converter in 1-µm...
TRANSCRIPT
June 1996
FFFFFINALINALINALINALINAL R R R R REPOREPOREPOREPOREPORTTTTT
Kwang Young KimIntegrated Circuits & Systems LaboratoryElectrical Engineering DepartmentUniversity of CaliforniaLos Angeles, CA 90095-1594
Supported by Analog Devices, Burr Brown, Raytheon Semiconductor,Signal Processing Technologies, and the State of California MICROProgram.
A 10-bit, 100 MS/sAnalog-to-DigitalConverter in 1-µm CMOS
iv
1. Introduction .................................................................................................... 1
2. High Speed ADC architectures ..................................................................... 6
2.1 Fully Parallel (Flash) A/D Converter ...................................................... 6
2.2 Subranging and two-step A/D Converter ................................................ 9
2.2.1 Subrange A/D converter ........................................................... 10
2.2.2 Two-stage A/D converter .......................................................... 11
2.3 Multi-Stage Pipeline A/D Converters ................................................... 13
2.4 Parallel Pipelined A/D Converters ........................................................ 16
3. General Considerations ............................................................................... 19
3.1 Digital error correction ......................................................................... 19
3.2 Nonlinearity in interstage block of ADC .............................................. 27
3.2.1 Offset of residue amplifier ........................................................ 27
3.2.2 Gain inaccuracy of residue amplifier ........................................ 29
3.3 Capacitor and resistor mismatch ........................................................... 32
3.3.1 Capacitor mismatch .................................................................. 32
Table of Contents
v
3.3.2 Resistor mismatch ..................................................................... 34
3.4 Amplifier design ................................................................................... 37
3.4.1 Residue amplifier ...................................................................... 37
3.4.2 Effect of feedback switch size .................................................. 41
3.4.3 Non-resetting Sample-and-Hold Amplifier .............................. 43
3.5 Analysis of clock jitter .......................................................................... 48
3.6 Analysis of non-linear effect at multi-channel ...................................... 50
3.6.1 Timing mismatch in the channels ............................................. 50
3.6.2 Offset and gain mismatch between the channels ...................... 54
3.7 Signal dependent clock feed through .................................................... 58
3.8 Metastability ......................................................................................... 62
4. System and Circuit Design .......................................................................... 66
4.1 Timing and requirement of system ....................................................... 72
4.2 Non-resetting Sample-and-Hold amplifier ........................................... 77
4.3 A 4-bit AD-DA ..................................................................................... 86
4.3.1 Comparator circuit .................................................................... 88
4.3.2 Latch Circuit ............................................................................. 93
4.3.3 Interpolated Quantizer ............................................................ 100
4.3.4 Reconstruction DAC ............................................................... 100
4.4 Residue Amplifier ............................................................................... 104
4.4.1 Gain-of-2 Amplifier ................................................................ 104
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4.4.2 Gain-of-4 amplifier ................................................................. 106
4.5 Super cascode amplifier ...................................................................... 107
4.5.1 Different common mode output level ..................................... 108
4.6 Error correction circuit and output buffer ........................................... 110
4.6.1 Error correction circuit ............................................................ 110
4.6.2 Output buffer ........................................................................... 113
4.7 Layout ................................................................................................. 113
4.7.1 Gain-of-2 amplifier layout ...................................................... 116
4.7.2 4-bit AD-DA ........................................................................... 119
4.8 Simulations ......................................................................................... 122
4.8.1 Input referred noise analysis ................................................... 122
4.8.2 Performance simulation .......................................................... 122
5. Testing Summary ....................................................................................... 126
5.1 DC test using a monitoring pin ........................................................... 127
5.1.1 Resistor DAC test result .......................................................... 128
5.1.2 Comparator offset ................................................................... 129
5.2 Testing Setup ...................................................................................... 132
5.3 DC performance .................................................................................. 136
5.3.1 Input referred interchannel offset ............................................ 136
5.3.2 Reconstructed spectrum at low input frequency ..................... 139
5.4 Dynamic Performance ........................................................................ 140
vii
5.5 Power dissipation and test summary ................................................... 145
6. Conclusions ................................................................................................. 150
6.1 Summary of research .......................................................................... 150
6.2 Performance Analysis ......................................................................... 153
A. Comparators............................................................................................... 155
A.1 Bipolar comparator ............................................................................. 155
A.2 CMOS comparators ............................................................................ 157
B. Glossary ...................................................................................................... 169
C. Distortion in RC sampling circuit ............................................................ 171
D. Detail schematic of ADC ........................................................................... 175
D.1 Schematic of top ................................................................................. 175
D.2 Schematic of non-resetting S/H .......................................................... 175
D.3 First ADDA......................................................................................... 183
D.4 First residue amplifier ......................................................................... 183
D.5 Second residue amplifier..................................................................... 183
Bibliography ................................................................................................ 194
viii
Figure 1-1 Video-rate 10-bit ADC map ............................................................3
Figure 2-1 Flash(Parallel) A/D converter architecture .....................................7
Figure 2-2 Subrange A/D converter architecture ............................................11
Figure 2-3 Two-step A/D converter architecture ............................................12
Figure 2-4 multi-stage pipeline A/D converter architecture ...........................13
Figure 2-5 Parallel pipeline A/D converter ....................................................16
Figure 2-6 A parallel pipeline ADC with a single S/H ...................................18
Figure 3-1 Effect of comparator offset in algorithmic A/D converter ............20
Figure 3-2 (a) Block Diagram of N-bit/stage in a pipeline A/D converter.
(b)Ideal residue versus input. (c) Residue versus input with
quantizer nonlinearity when N=2 ................................................22
Figure 3-3 Effect of comparator offset in algorithmic A/D converter ............24
Figure 3-4 Ideal Residue vs. input of the ADC block (a) without a offset
comparator (b) with 1/2 LSB comparator offset ...........................26
Figure 3-5 Schematic of offset canceling switched-capacitor amplifier ........28
Figure 3-6 Effects of interstage gain error ......................................................30
Figure 3-7 Schematic for calculating required DC gain with Miller
Table of Figures
ix
capacitor (Cgd) ..............................................................................31
Figure 3-8 Matching requirement in resistor string with n-bit precision
and N-bit accuracy ........................................................................35
Figure 3-9 (a) Schematic of residue amplifier with offset compensation
(b) During sampling phase (c) During amplifying phase .............38
Figure 3-10 Time constant vs. sampling capacitor ...........................................40
Figure 3-11 A zero introduced by feedback switch ..........................................43
Figure 3-12 Transient step response with different switch size .......................44
Figure 3-13 (a) Non-reset Track and Hold amplifier schematic
(b) During sampling and holdingII period
(c) During holdingI period ............................................................45
Figure 3-14 Signal to noise due to clock timing jitter at 10 MHz, 30 MHz,
and 50 MHz input frequency .......................................................49
Figure 3-15 Sampling of M channel parallel ADC with Timing offset ..........50
Figure 3-16 Digital Spectrum of M channel parallel ADC
with timing offset ..........................................................................53
Figure 3-17 Model for the ADC in i th channel with gain and offset
mismatch .......................................................................................54
Figure 3-18 Multi-channel ADC transfer characteristic ...................................55
Figure 3-19 Reconstructed spectrum of sinusoidal input
(a) offset mismatch (b) gain mismatch .........................................57
x
Figure 3-20 (a) SFDR with gain mismatch in 2 channel ADC
(b) SFDR with offset mismatch in 2 channel ADC
with ± 1 V full scale input ............................................................59
Figure 3-21 Offset compensated voltage amplifier with voltage
independent clock feed through (a)Schematic (b) timing .............60
Figure 3-22 (a) Comparator with preamplifier and cascade of two latch
with time constant t1 and t2 (b) Latch schematic
during regeneration (c) Transient response of the latch
during regeneration phase (d) Metastability region
in coarse quantizer with 15 comparator ........................................63
Figure 4-1 Block Diagram of Architecture .....................................................67
Figure 4-2 SNR with gain mismatch 2 channel pipeline ADC ......................69
Figure 4-3 Timing Diagram of ADC front end ..............................................73
Figure 4-4 First residue amplifier bank (a) Block diagram
(b) Timing diagram .......................................................................75
Figure 4-5 7 bit pipeline converter
(a) block diagram (b) timing diagram ...........................................76
Figure 4-6 Block diagram and timing diagram of (a) resetting S/H
(b) double resetting S/H (c) non-resetting S/H .............................78
Figure 4-7 Non-resetting sample and hold amplifier ......................................79
Figure 4-8 Non-resetting sample and hold Amplifier: (a) at f1, (b) at f2 .......80
xi
Figure 4-9 Feedback capacitor configuration of non-resetting S/H
and resetting (conventional) S/H ..................................................83
Figure 4-10 4 bit AD-DA Block Diagram ........................................................87
Figure 4-11 Comparator Circuit .......................................................................89
Figure 4-12 Preamplifier Input arrangement ....................................................90
Figure 4-13 First stage preamplifier schematic (a) applying differential
input in one differential pair (b) applying differential input
in each differential. pair, respectively ...........................................91
Figure 4-14 Schematic of dynamic latch ..........................................................93
Figure 4-15 Latch schematic ............................................................................94
Figure 4-16 (a) timing diagram of latch and FF (b) hysteresis of
the master slave FF (c) back-to-back inverter latch ......................96
Figure 4-17 Simulation result of latch and F/F .................................................98
Figure 4-18 Block diagram of interpolated quantizer .....................................101
Figure 4-19 Two possible layouts of AD-DA using single
resistor ladder ..............................................................................102
Figure 4-20 Elmore delay model ....................................................................104
Figure 4-21 Gain of 2 residue amplifier circuit ..............................................105
Figure 4-22 Gain of 4 residue amplifier circuit ..............................................106
Figure 4-23 Super cascode amplifier ..............................................................108
Figure 4-24 Input and Output common mode range ......................................109
xii
Figure 4-25 Op amp Common-mode Feedback .............................................110
Figure 4-26 Error correction circuit (ECC) (a) Error correction
circuit block diagram (b) Adder in ECC .....................................111
Figure 4-27 Detail logic of simplified carry-look ahead in ECC ...................112
Figure 4-28 Schematic of differential output buffer .......................................113
Figure 4-29 Floor Plan of A/D converter .......................................................114
Figure 4-30 Chip microphotograph of the ADC .............................................116
Figure 4-31 Gain-of-2 residue amplifier layout ..............................................117
Figure 4-32 4-bit AD-DA layout ....................................................................120
Figure 4-33 Measured mean and standard deviation of comparator
threshold offset from 1st quantizer in first version .....................121
Figure 4-34 Layout of resistor ladder for reconstruction DAC ......................122
Figure 4-35 Input referred Noise in ADC .......................................................123
Figure 4-36 Noise floor in 2N point FFT of ideal 10-bit ADC .......................125
Figure 5-2 DAC linearity testing setup .........................................................128
Figure 5-1 Captured layout of resistor ladder DACs ....................................129
Figure 5-3 Resistor DAC testing result ........................................................130
Figure 5-4 Measured mean and standard deviation of comparator
threshold offset from 1st quantizer .............................................131
Figure 5-5 A/D converter test setup ..............................................................132
Figure 5-6 PCB board (a) component location (b) signal line layout
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at top plate ..................................................................................135
Figure 5-7 Histogram of measured input referred inter-channel offset mis-
match ...........................................................................................137
Figure 5-8 (a) Histogram of fs/2 tone
(b) histogram of RMS sum of fs/2 and fs/4 tone
referred to ± 1 V, measured in ± 0.5 V input full scale ..............138
Figure 5-9 Reconstructed spectrum from measurement at
500 KHz input frequency and 4 MHz conversion rate ...............139
Figure 5-10 (a) Measured signal-to-distortion ratio (b)measured total
harmonic distortion (THD) and spurious free dynamic range
(SFDR) where input signal frequency is fixed 500 KHz ............141
Figure 5-11 Measured signal-to-distortion and noise ratio at 4 MHz,
50MHz and 95MHz conversion rate ..........................................142
Figure 5-12 Projected SNDR at 95 MHZ conversion rate .............................144
Figure 5-13 Reconstructed spectrum from measurement at
2 MHz input frequency and 95.2 MHz conversion rate ..............145
Figure 5-14 Differential nonlinearity from 2 MHz input frequency
at 90 MHz conversion rate ..........................................................146
Figure 5-15 Integral nonlinearity from 2 MHz input frequency
at 90 MHz conversion rate ..........................................................147
Figure 5-16 Power dissipation vs. sampling frequency ..................................148
xiv
Figure 5-17 Power dissipation at 95 MHz sampling rate ...............................148
Figure A-1 Basic bipolar comparator circuit .................................................156
Figure A-2 Bipolar comparator with high-level clocking .............................157
Figure A-3 Comparator schematic from Nauta, 1996 [63] ...........................158
Figure A-4 Comparator schematic from Fiedler, 1981 [16] ..........................159
Figure A-5 Comparator schematic from Song, 90 [88] .................................160
Figure A-6 Comparator Schematic from Lewis, 1992 [42] ...........................162
Figure A-7 Comparator schematic from Robert, 87 [75] ..............................163
Figure A-8 Comparator schematic modified from Yukawa, 1985 [108] ......164
Figure A-9 Comparator Schematic from Sutarja, 1988 [94] .........................166
Figure A-10 Comparator schematic from Kobayashi, 1993 [35] ....................167
Figure A-11 Steady state response of RC network ..........................................171
Figure A-12 Sample-and-hold output of RC network
where t0= 0 ..................................................................................173
Figure A-13 Non-resetting S/H and 4-bit ADDA ...........................................176
Figure A-14 Block diagram of one of 2 channel .............................................177
Figure A-15 Schematic of non-resetting S/H ..................................................178
Figure A-16 Schematic of non-resetting S/H op amp .....................................179
Figure A-17 Auxiliary amplifier for PMOS cascode device
in non-resetting S/H ....................................................................180
Figure A-18 Auxiliary amplifier for NMOS cascode device
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in non-resetting S/H ....................................................................181
Figure A-19 Schematic of CMFB of non-resetting S/H ..................................182
Figure A-20 Block diagram of first ADDA (100 MHz) ..................................184
Figure A-21 Block diagram of comparator circuit in first
4-bit quantizer .............................................................................185
Figure A-22 Schematic of pre-amplifier in first 4-bit quantizer .....................186
Figure A-23 Schematic of latch in first 4-bit quantize ....................................187
Figure A-24 Block diagram of first residue amplifier .....................................188
Figure A-25 Schematic of gain-of-2 residue amplifier in first
residue amplifier bank ................................................................189
Figure A-26 Schematic of gain-of-2 residue amplifier in first
residue amplifier bank ................................................................190
Figure A-27 Schematic of gain-of-2 in second residue amplifier ...................191
Figure A-28 Schematic of gain-of-4 in second residue amplifier
with simple offset control switch ................................................192
Figure A-29 Schematic of op amp in second residue amplifier bank .............193
xvi
Table 1.1 ADC requirement in conventional and HDTV system................... 2
Table 2.1 High speed Flash A/D converters ................................................... 7
Table 2.2 Effective bits vs. residue amplifier gain and number of
comparator in 10-bit ADC 15
Table 2.3 SDR with 10ps of timing mismatch in two channel ideal ADC... 17
Table 4.1 Gain-bandwidth of linear component ........................................... 70
Table 4.2 Simulation summary of non-resetting S/H amplifier at 70oC....... 86
Table 4.3 Comparator specification.............................................................. 92
Table 4.4 Parameters for device mismatch ................................................... 92
Table 5.1 Signals in different layers ........................................................... 134
Table 5.2 Summary of ADC characteristic................................................. 149
Table A.1 Summary of comparator performance .........................................168
List of Tables
xx
ABSTRACT OF THE DISSERTATION
A 10-bit 100 Msample-per-SecondAnalog-to-Digital Converter
in 1-µm CMOS
by
Kwang Young Kim
Doctor of Philosophy in Electrical Engineering
University of California, Los Angeles, 1996
Professor Asad A. Abidi, Chair
Applications such as high-end video signal processing, high performance
digital communications, and medical imaging require ADCs with sample rates
approaching 100 MS/s and a dynamic range at the Nyquist bandwidth close to 60
dB. In response to these needs, there is a continued search for architectures and
circuit techniques enabling a monolithic ADC to meet these specifications with a
reasonable chip area and power dissipation. It is of particular interest that if such an
ADC is fabricated in a standard CMOS technology.
xxi
This work addresses some of the known problems inherent in time-
interleaved, or parallel, pipeline ADCs with a new architecture. A prototype of this
architecture demonstrates, for the first time, 10-bit operation at the maximum
sampling rate up to 95 MHz in 1µm CMOS technology. It attains 59.5 dB SNDR
at a low conversion rate, and more than 50 dB SNDR at 50MHz input frequency
with a 95 MHz conversion rate. By using a minor offset control to suppress the fs/2
tone, 65 dB spurious free dynamic range (SFDR) is achieved. The simulated bit
error rate is less than 10-10. The ADC implemented in fully differential circuitry
uses the 2-channel 3-stage pipeline architecture. Each stage converts 4-bits, and
2-bits from 12-bit are used for digital error correction. Because all the digital clock
signals are generated from the on-chip clock buffer, it requires a single full speed
clock signal. The active chip area is 50 mm2 and the ADC dissipates 1.2 W from a
single 5 V power supply.
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Chapter 1
Introduction
The analog-to-digital converter (ADC) and digital-to-analog converter
(DAC) are required between the analog signal and the digital processor to take
advantage of digital signal processing, because most signals in use are analog in
nature. The digital signal processor has developed rapidly due to integrated circuit
technology over the past 20 years. There are several reasons why digital signal
processing of an analog signal may be preferable to processing the signal directly
in the analog domain. First, accuracy considerations play an important role in
determining the form of the signal processor. Second, the digital signals are easily
stored on magnetic media (tape or disk) without deterioration or loss of signal
fidelity beyond that introduced in the ADC. As a consequence, the signals become
transportable and can be processed off-line. The digital signal precessing method
also allows for the implementation of more sophisticated signal precessing
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algorithms which is difficult to perform precise mathematical operations on analog
signal form. And, in some case, a digital implementation of the signal processing
system is cheaper than its analog counterparts. However, one of the practical
limitations of digital implementation is the speed and accuracy of the operation of
the ADC, which normally requires more power and complex circuitry than DACs.
Applications such as high-end video signal processing [65][96], high
performance digital communications [78], and medical imaging require ADCs with
sample rates approaching 100 MS/s and a dynamic range at the Nyquist bandwidth
close to 60 dB. For instance, the conventional NTSC TV system requires 8-bit
resolution and a 20 MHz sampling rate. However, recently proposed high definition
television (HDTV) digital VTR in Japan requires 10-bit resolution and 75 MHz
sampling for 1125 scanning lines, a 60Hz field rate with 30MHz bandwidth
luminance signal, and two 15MHz bandwidth color-difference signals. The
requirements of conventional and HDTV systems are summarized in Table 1.1. In
response to these needs, there is a continued search for architectures and circuit
Table 1.1 ADC requirement in conventional and HDTV system
Applications Requirements
NTSC Resolution 8 bit
HDTV 10 bit
TV, VCR Sampling Rate 20 MHz
HDTV ENCODER 50 MHz
HDTV STANDARD 75 MHz
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techniques enabling a monolithic ADC to meet these specifications with a
reasonable chip area and power dissipation. It is of particular interest if such an
ADC is fabricated in a standard CMOS technology.
Most published ADCs which come close to these specifications are 10-bit
bipolar ADCs [9][34][72][87][99] as shown in Figure 1-1 and 12-bit bipolar ADC
[59]. Their high speed and wide dynamic range owes to the use of open-loop precise
building blocks, including low-offset comparators. A recent ADC attains up to a 70
dB dynamic range with this approach [59]. CMOS ADCs, by contrast, tend to use
94929088
Sampling Rate (sps)
100M
10M
Multi-step
50M
5M
Pipeline
500M
Flash
UCB[12]
AT&T[88] Hitachi[50]
AT&T[42]
AD[47]
NEC[106]
NEC[87]UCLA[9]
Philips[99]Siemens[72]
Matushita[52]
AD[76]Hitachi[83]
Matushita[34]
Year
Figure 1-1 Video-rate 10-bit ADC map
This work
96
Bipolar
Bi-CMOS
CMOS
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closed-loop op-amp based circuits for precise analog signal processing and closed
loop auto-zeroed comparators in quantizers resolving 4-bits or more. It is therefore
difficult for these circuits to attain both the dynamic range and the speed of a bipolar
ADC built with devices of comparable ft. For instance, an open-loop folding and
interpolation ADC in 0.8 mm CMOS clocks at up to 75 MHz, but is limited to about
45 dB in dynamic range [62]. Device layout and other averaging techniques yield
limited improvements in the accuracy of the intrinsically poorly-matched
MOSFET. Parallelism is one reliable way to obtain a high throughput while
retaining wide dynamic range. For instance, an array of identical high-resolution
but low-speed ADCs may be time-interleaved in parallel to increase overall
throughput, proportional increase in hardware complexity and power dissipation
[2].
This work addresses some of the known problems inherent in time-
interleaved, or parallel, pipeline ADCs with a new architecture. A prototype of this
architecture demonstrates, for the first time, 10-bits operation at 100 MS/s in a 1µm
CMOS technology.
The thesis is organized as follows. In Chapter 2, the high speed ADC
architectures are reviewed and limitations of each type have been analyzed. Chapter
3 describes the basic limitations and requirements to build a CMOS ADC, the
methods to overcome or relax the limitations, and an analysis of speed limitations
in amplifiers. A detailed explanation of our system blocks, circuit design and layout
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issues are presented in Chapter 4. The test results of this prototype CMOS ADC are
discussed in Chapter 5, followed by conclusions in Chapter 6.
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Chapter 2
High Speed ADC architectures
2.1 Fully Parallel (Flash) A/D Converter
Parallel (Flash) A/D conversion is by far the fastest and conceptually
simplest conversion process [1][19][27][36][54][68][84][100][105][108]. As
shown in Figure 2-1, an analog input is applied to one side of a comparator circuit
and the other side is connected to the proper level of reference from zero to full
scale. For N-bit resolution, 2N-1 comparators simultaneously evaluate the analog
input and generate the digital output as a thermometer code. All the output from the
comparator is encoded to Binary or Gray code digital output by encoding circuitry.
Because the flash converter needs only one clock cycle per conversion, it is
often the fastest converter as shown in Table 2.1 . Moreover, since references are
made by a resistor string, they are monotonic, resulting in low differential
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nonlinearity. However, there are several drawbacks. One is that the hardware
Table 2.1 High speed Flash A/D converters
Process N-bitsConversion
rateAffiliation Year
Bipolar 6-bits 2 GHz NTT[100] 1988
8-bits 500 MHz Sony[19] 1991
400 MHz NTT[1] 1987
10-bits 300 MHz Matsushita[34] 1993
CMOS 6-bits 125 MHz Micro Networks[54] 1992
8-bits 30 MHz TI[84] 1991
Latc
hes
ThermometerCode
Enc
oder
N -bitCodeword
Analog Input
Strobe
full
scal
e re
fere
nce
Figure 2-1 Flash(Parallel) A/D converter architecture
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complexity increases exponentially with the resolutions because it needs a 2N-1
comparator circuits. This also means that the power dissipation and the chip area
increase exponentially with the resolution. The second drawback is that the analog
input must drive the large nonlinear input capacitance of the comparators. Since this
input capacitance for the 10-bit is typically 40-100pF and the driving current
reaches 24-60mA for a 100 MHz, 2 Vp-p input signal, large-signal distortion may
occur, further aggravated by the nonlinearity of the input capacitance.
The third disadvantage is that the mismatch in the resistor reference ladder
and the unequal input offset voltage of comparators limits the resolution to about 8-
bit in CMOS technologies [84]. The mismatches in offset voltage can be
represented by Vbe mismatches in bipolar process and Vt mismatches in CMOS
process. The Vbe mismatch of the self-aligned bipolar transistor is due to both
emitter saturation current mismatch and emitter resistance mismatch of transistor
pairs.∆Vbe can be written as
(2.1)
whereIs1 and Is2 is a saturation current of two devices andRe1 andRe2 are the
emitter resistance of two devices, respectively. In the low emitter current range, the
first term of eq. (2.1), which has a linear dependency on the emitter perimeter-to-
area ratio, is the dominant factor in the mismatch of Vbe. In the high current range,
the emitter contact resistance which is the second term of eq. (2.1), is the dominant
∆VbeKTq
-------Is1
Is2------
ln Re1 Re2–( ) Ie+=
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factor of the mismatch in Vbe. In the self-aligned bipolar process, the standard
deviation of a Vbe mismatch is 1~2 mV for medium emitter current (≈ 200µA) or
less with the emitter area larger than 0.2x2.3µm2 [79]. A 10-bit A/D converter has
been reported by adding a preamplifier in front of the comparator and by choosing
a proper emitter size transistor to reduce the comparator offset due to Vbe mismatch
[34]. The threshold voltage,Vt, in the CMOS process can be represented as
(2.2)
whereVfb is a flatband voltage,εsi is a permittivity of silicon, andNA is a doping
density. The local doping density variation causes aVt mismatch in a CMOS
process, and the standard deviation of length of 1µm and width of 9µm device
mismatch fabricated in 1µm process with 20nm thin oxide thickness is about 5 mV
[69]. To obtain a 10-bit resolution with a 2.0 Vp-p input signal, the comparator
should resolve 2 mV, which is very difficult to obtain in bipolar and even more
difficult in a CMOS process. Therefore, several schemes, such as adding a chopper
amplifier [36] and auto-zero scheme to sample an offset in the capacitor in front of
the latch, or inserting a preamplifier [108] in front of the latch, have been developed
to decrease DNL of the ADC.
2.2 Subranging and two-step A/D Converter
The subrange and two-step architecture was developed to reduce hardware
Vt Vfb
2εsiqNA2ϕb( )Cox
----------------------------------------- 2ϕb+ +=
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complexity, reduce power dissipation and die area, and also to reduce input
capacitance which loads the preceding circuit. Conceptually, these types of
converter need comparator instead of comparators where
assumingn1, n2,......, nm are all equal to n. For example, the 10-bit 2-stage
subranging converter needs 64 ( ) comparators instead of 1024 ( )
comparators in flash type. However, the conversion in subrange and two-step ADC
does not occur instantaneously like a flash ADC, and the input has to be held
constant until the sub-quantizer finishes as its conversion. Therefore, the sample-
and-hold circuit is required to improve performance. Even though multi-stage (> 2)
converters are possible, these types of ADC must be 2-stage because of delay in the
sub-stage.
2.2.1 Subrange A/D converter
A subrange ADC which consists of 2N resistors, 2N/2-1 comparators, a
switch bank, and a S/H [11][80] is illustrated in Figure 2-2. In the first step, the S/H
samples the input signal and the sampled input is quantized by the first quantizer
which consist of 2N/2 -1 comparator referenced on a resistor string every 2N/2 taps
apart. In the second phase, the previous quantized result (MSB) determines the
selected interval of a resistor string for the second quantization where the fine
conversion (LSB) has to be made. One with 2N/2-1 comparators can perform both
the MSB and LSB quantization.
m 2n× 2
NN m n⋅=
2 25× 2
10
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The simple holding capability has been added to the 2nd comparator circuit
to increase a conversion speed, especially in CMOS ADC so that the S/H can
acquire a new input signal after the MSB has been determined. The extra
comparators were added to the 2nd quantizer, and a digital error correction scheme
was used to increase conversion linearity [17][51][88].
2.2.2 Two-stage A/D converter
A two-stage converter consists of a sample-and-hold (S/H), two coarse
quantizers, DAC, subtracter and gain block as shown in Figure 2-3. The S/H
samples and holds the input signal. This sampled signal from the S/H circuit is
S/HVin
Decoder
Decoder
Vref
LSB
MS
B
Figure 2-2 Subrange A/D converter architecture
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quantized by the first coarse quantizer. The first quantizer output selects the DAC
output, and the residue is made from the difference between a sampled input signal
and DAC output. The residue is amplified and is quantized by a 2nd coarse
quantizer. The S/H output is held until the 2nd quantizer finishes the conversion. In
a subrange architecture, the second quantizer can only tolerate a±1/2 LSB of N-bit
offset for theN-bit ADC, even though the precision of the first quantizer can be
relaxed by adding some of the extra comparator at both ends of the second quantizer
and by adapting an error correction scheme. But in a two-step architecture, both the
first and second quantizers can tolerate more than a±1/2 LSB ofN-bit offset for the
N-bit ADC because the residue amplifier can amplify the residue signal to the full
input scale.
However, there are several disadvantages in the two-step architecture
Figure 2-3 Two-step A/D converter architecture
Combination Logic
N = n1 + n2
N1bit
N1bit
ADC
DAC
X 2M
N1 bits
N2bitADC
S/HVin
13
June 3, 1996
changed to the flash architecture. The two-step ADC requires a DAC whose
linearity should be better thanN-bits forN-bit ADC, and also requires a subtracter
(or a subtracter and residue amplifier) which can be the speed bottleneck. In
addition, the conversion time is longer than a flash ADC because the two-step ADC
has to wait until the residue signal is settled and quantized.
10-bit resolution has been reported in a two-step converter [12][58][83][72]
[89]. Furthermore, the 12-bit two-step ADC has been achieved with the supports of
a self-calibration circuit and a trimming feature [30][31][40].
2.3 Multi-Stage Pipeline A/D Converters
The pipeline A/D architecture as shown in Figure 2-4 utilizes a sample-and-
hold (S/H) in each stage to improve the conversion rate [9][42][46][47][50]
[87][90]. Each stage consists of a S/H, an N-bit flash ADC, a reconstruction DAC,
a subtracter, and a residue amplifier. The conversion mechanism is similar to that of
N bit
N bit
ADC
DAC
X 2N-1
Delay Registers, Combination Logic, and Digital Error Correction
n bits
S/H
N bit
N bit
ADC
DAC
X 2N-1
n bits
S/H
N bitADC
n bits
S/HInput
Figure 2-4 multi-stage pipeline A/D converter architecture
1st stage 2nd stage Nth stage
G1 G2
14
June 3, 1996
subranging conversion in each stage. Now the amplified residue is sampled by the
next S/H, instead of being fed to the following stage. All theN-bit digital outputs
emerging from the quantizer are combined as a final code by using the proper
number of delay registers, combination logic and digital error correction logic.
Although this operation produces a latency corresponding to the sub-
conversion stage before generating a valid output code, the conversion rate is
determined by each stage’s conversion time, which is dependant on the
reconstruction DAC and residue amplifier settling time. The multi-stage pipeline
structure combines the advantages of high throughput by flash converters with the
low complexity, power dissipation, and input capacitance of subranging converters.
Furthermore, the T/H function can be obtained free if a switched capacitor amplifier
is used in a residue amplifier circuit in CMOS technology.
One effective way to reduce power dissipation is by converting to one
effective bit per each stage. When 2 effective bits have been digitized in each stage,
the total number of the pipeline stage and the total number of the residue amplifier
are reduce to half, but the residue amplifier gain increases by 2 times, which means
the gain-bandwidth product has to be twice as large as the 1 effective bit per stage.
Since the transconductance is
(2.3)
Id has to be 4 times larger in an ADC converting 2 effective bits per stage than in 1
effective bit per stage. The number of comparators required to build the ADC is
gm 2µCoxWL-----Id=
15
June 3, 1996
larger in 1 effective bits per stage than that in 2 effective bits. The required residue
amplifier gain and number of comparators are summarized in Table 2.2. However
the number of comparators shown in Table 2.2 can be further reduced by using more
sophisticated error correction scheme. For example, a 10-bit ADC which converts
1 effective bit per stage and consists of nine stages, nine op amps, and 19
comparators has been reported [42]. A power dissipation of 50 mW or less is
obtained in 10-bit 20 MHz ADC using the 1 effective bit per stage concept [8][91].
However, the limitation of the low power approach in converting less bit per stage
is that the gain accuracy of the first residue amplifier becomes more stringent,
because the accuracy requirement is dependent on the remaining number of bits to
be converted. For example, in 10-bit ADC using a one effective bit per conversion,
the tolerable gain error in the first residue amplifier is less than± 2-9/2. Since the
capacitor matching is about 0.1%, the gain of the first several residue amplifiers
Table 2.2 Effective bits vs. residue amplifier gain and number of comparatorin 10-bit ADC
Effectivebits
Number ofstage
Structure GainNumber ofcomparator
1 9 2bx9 2 3x9
2 5 3bx4+2b G1~3=4G4=2
7x4+3
3 3 4bx3 8 15x3
5 2 5b+6b 16 31+61
16
June 3, 1996
might need a gain adjustment.
2.4 Parallel Pipelined A/D Converters
The throughput rate can be increased further by using a parallel architecture
[2][10][74][106][107] as shown in Figure 2-5. The first channel samples the input
while the other two channels are evaluating previously sampled input.
Theoretically, the conversion rate can be increased by the number of parallel paths,
at the cost of a linear increase in power and chip area.
However, this parallel pipeline architecture has three major sources of
distortion. One error source is that a timing mismatch among the input samplers of
x 2N-1S/H S/H
N
N
x 2N-1S/H
N
N
N
x 2N-1S/H S/H
N
N
x 2N-1S/H
N
N
N
x 2N-1S/H S/H
N
N
x 2N-1S/H
N
N
N
Input
Figure 2-5 Parallel pipeline A/D converter
channel 1
channel 2
channel 3
17
June 3, 1996
each channel can degrade spectrum purity. The timing mismatch among the
channels is unavoidable because of asymmetry among the clock distribution in the
layout, and also due to mismatch of devices such as clock buffer devices. With this
fixed amount of timing mismatch, the signal-to-distortion ratio decreases at higher
input signal frequency as shown in Table 2.3.
The other sources of distortions are the input-referred offset mismatch, and
the gain mismatch at the residue amplifiers among these channels. The inter channel
input referred offset mismatch gives rise to fixed pattern noise. This can be found
in the frequency domain as a tone at multiples offs/N whereN is the number of
channel andn= 1, 2,…, N. The inter channel gain mismatch can generate a spurious
tone at fs/N±fin, 2⋅fs/N±fin,…,N⋅fs/N±fin. The input referred offset mismatch
generates a tone at1⋅fs/N, 2⋅fs/N,…, N⋅fs/N. In addition, the first S/H in each channel
must have enough tracking bandwidth to acquire an input frequency up to the
Nyquist frequency.
The effects of all three limitations can be dramatically reduced by adding a
single sample-and-hold circuit in front of each channel, as shown in Figure 2-6. The
Table 2.3 SDR with 10ps of timing mismatch in two channel ideal ADC
Input signal frequency SDR (dB)
10 MHz 70.1
20 MHz 64.0
50 MHz 56.1
18
June 3, 1996
timing mismatch among the channels is not an issue when the parallel pipeline
architecture has a single S/H, because S/H is distributing sampled signals instead of
dynamic signals [74][106].
x 2N-1S/H S/H
N
N
N
S/H
x 2N-1S/H S/H
N
N
N
x 2N-1S/H S/H
N
N
N
Figure 2-6 A parallel pipeline ADC with a single S/H
Vin
19
June 3, 1996
Chapter 3
General Considerations
3.1 Digital error correction
The digital error correction scheme is one way to overcome an offset of
comparator in a data converter system using a coarse quantizer such as algorithmic
ADCs [43][60][67][83] and pipelined ADCs. For example, we want to design a 8-
bit algorithmic ADC with an ideal residue amplifier and an ideal DAC but with a
comparator which has a 5-LSB input referred offset as shown in Figure 3-1.
Because of the offset of the comparator, theVin1 (which should be 100000012 in an
ideal A/D converter) is quantized to 0 instead of 1 at the first conversion. The
amplified (x 2) residue ofVin1 after the first quantization lands on an over-range
scale, and the second through 8th quantized data are all quantized to 1 at sub-
conversion, resulting in 011111112. TheVin2 (which should be 100000102 in an
20
June 3, 1996
ideal A/D converter) also converted to 0111111112 because after the first
conversion, all the amplified residue landed on the over-range scale. Therefore, the
requirement of the comparator is that the offset should be less than 1/2LSB of the
converter. To relax this requirement, the simple digital error correction scheme has
been introduced[25][31][41].
As shown in Figure 3-2 (a), this offset at the comparator in the subconverter
block which contains a coarse quantizer, a D/A converter and a residue amplifier
1
1/2
1/4
3/4
0
vin2x 2
Ref
eren
ce
x 2x 2 x 2
0 01 011 0111 01111111
vin1
vin1vin2 0 01 011 0111 01111111
Ove
r R
ange
Figure 3-1 Effect of comparator offset in algorithmic A/D converter
vin2
vin1
vin2
vin1 1/2 FS
1/ 2 FS+5 LSB
Comp. Offset
Comp. offset
21
June 3, 1996
can be explained with a residue versus input plot. In Figure 3-2 (b), both the coarse
quantizers and the D/A converter are assumed to be ideal. The residue can be
expressed as
(3.1)
whereDACoutis selected by a coarse quantizer. If the input (Vin) of a subconverter
block is between two adjacent thresholds of the coarse quantizer, the residue is a
linearly increasing function with the input. Once the Vin is increased over the
coarse quantizer threshold, the residue abruptly changes by 1LBS because the DAC
input has increased by 1. Therefore the ideal residue waveform looks like a
saw-tooth as shown in Figure 3-2 (a). Here, the residue is always between± 1/2
LSB and consists only of the part of the input that is not quantized by the first stage.
With the interstage gain equal to 2, the maximum residue is amplified into a full-
scale input to the next stage; therefore, the conversion range of the next stage is
equal to the maximum residue out of the first stage.
Two similar curves are shown in Figure 3-2 (c) for a case when the coarse
quantizer has some input referred offset, but the DAC is still ideal. In this example,
two of the A/D subconverter decision levels are shifted, one by -1/4 LSB and the
other by +1/4 LSB. If the decision levels are shifted by less than ±1/4 LSB, the
range of the residue increases 1/4 LSB on both ends of the ideal conversion range
which is between -1/2 LSB and +1/2 LSB. Because the residue consists of the
unquantized part of the input and the error caused by the offset of the coarse
Residue Vin DACout–=
22
June 3, 1996
Figure 3-2 (a) Block Diagram of N-bit/stage in a pipeline A/Dconverter. (b)Ideal residue versus input. (c) Residueversus input with quantizer nonlinearity when N=2
N-bitADC
X 2N
n-bits
THInput
N-bitDAC
Residue
(a)
(b)
+1/4 LSBcomp. offset
Residue
Vin
00 011/2 LSB
-1/2 LSB
10 11
Residue
Vin
00 01
1/2 LSB
-1/2 LSB
1 LSB
-1 LSB
10
Residue
Vin
00 01
1/2 LSB
-1/2 LSB
1 LSB
-1 LSB
10
-1/4 LSBcomp. offset
ConversionRange
of Next Stage
(c)
-3/4 LSB
3/4 LSB
23
June 3, 1996
quantizer, these increased residues are accurate for the codes to which they
correspond as long as the DAC output is ideal; therefore, at this point, no
information is lost. Even though the interstage gain is 2, however, information can
be lost when the larger residues saturate the next stage and produce overflow in the
conversion. Therefore, if the conversion range of the second stage is increased to
handle the larger residues, they can be encoded and the errors corrected. This
process is called digital error correction.
A digital error correction scheme can be utilized with the 8-bit A/D
converter shown in Figure 3-3, which illustrates the two conversion process with
the non-ideal (vin1) and ideal (vin2) comparator, and with the underflow and
overflow indication. The non-ideal comparator is modeled as a comparator with
offset of more than 6 LSB of 8 bit and the ideal comparator is modeled as a
comparator with zero offset. Because of the offset in a non-ideal comparator case,
the output is 0 instead of 1. At the second conversion process, the residue input is
larger than full scale and the comparator output indicates the 1 with the overflow.
With the overflow indication, the second residue of the non-ideal comparator case
becomes the same as that of the ideal comparator case. Once the conversion process
is completed, the digital output with overflow and underflow indication should be
recalculated such that a digital output 1+ has to add 1 to the upper digital data and
set itself to 0 and a digital output 0- has to subtract 1 from the upper digital data and
set itself to 1. If the comparator has no offset, the overflow and underflow range are
24
June 3, 1996
not needed. Otherwise, these are used for generating extra information for digital
error correction. The digital error correction scheme improves linearity by allowing
the converter to postpone decisions on inputs that are near the first coarse quantizer
threshold until the residue from these inputs are amplified to the point where similar
coarse quantizer threshold offset in the later A/D converter block is insignificant.
The penalty in using a digital error correction is that it requires a redundant
Figure 3-3 Effect of comparator offset in algorithmic A/D converter
1
1/2
1/4
3/4
0
x 2
Ref
eren
ce
x 2
vin1,2
vin1
vin2 0 10 10 0
vin1
vin1,2
vin2 vin1,2
Nom
inal
Ran
geO
ver
Ran
geU
nder
Ran
ge
0 01+ 01+0 01+001100
10 001100(with comp. offset)
(without comp. offset)
comp. offset
25
June 3, 1996
comparator and correction logic.
Because in digital circuits the subtraction process, which consists of two’s
complement and addition, is more complex than the addition process, digital error
correction with only an addition process algorithm has been
investigated[15][42][83]. One way to eliminate subtraction in the digital error
correction by shifting a comparator offset by 1/2 LSB has been investigated [42],
and the residue waveform of this method is illustrated in Figure 3-4. The correction
range can be defined as the amount of offset shift at the coarse quantizer that can be
tolerated without error. If the DAC and the residue amplifier is ideal with gain of 2,
the amplified residue from Figure 3-4 (a) remains within the conversion range of
the next stage when the coarse quantizer offsets are shifted no more than 1/2 LSB.
Under this condition, errors caused by the coarse quantizer offsets can be corrected.
Because the offset introduced into the coarse quantizer in Figure 3-4 (b) is 1/2 LSB,
the digital output is always less than or equal to its ideal value if a coarse quantizer
offset can shift the threshold back to the left by no more than 1/2 LSB. Thus, the
correction requires no change or addition. While the ideal residue in Figure 3-4 (a)
is always between± Vr/ 4, the range of ideal residues in Figure 3-4 (b) is- Vr/ 2 to
+ Vr/ 4. With identical stages and an interstage gain of 2, the minimum residue in
Figure 3-4 (b) occurs on the left end of the plot and rests on the lower conversion-
range boundary of the next stage. Although movement of the threshold of the coarse
quantizer has no effect on the value of this left-end residue, interstage offset or gain
26
June 3, 1996
error may cause the left-end residue to lie below the conversion range of the next
stage.
Residue
Vin
00 01
1/2 LSB
-1/2 LSB
Residue
Vin
1/2 LSB
-1/2 LSB
Vr/2= 1 LSB
-Vr/2= -1 LSB
10 11
00 01 10 11
-Vr - Vr/4 Vr/4 3Vr/4
-Vr - Vr/2 Vr/2 Vr0
Con
v.R
ange
Vr/2= 1 LSB
-Vr/2= -1 LSB
Con
v.R
ange
Figure 3-4 Ideal Residue vs. input of the ADC block (a) without aoffset comparator (b) with 1/2 LSB comparator offset
27
June 3, 1996
3.2 Nonlinearity in interstage block of ADC
3.2.1 Offset of residue amplifier
As was discussed in the previous section, if the amplified residue does not
exceed the full conversion range of the following coarse quantizer, the linearity of
ADC is not affected by the digital error correction scheme. Therefore, the input
referred offset of a residue amplifier must meet the following requirement:
(3.2)
with the conversion range as shown in Figure 3-4.
Even though the offset canceling scheme has been used to cancel out the
offset of op amp, offsets still remains due to a limited op amp DC gain, mismatches
in switches, and capacitors in the residue amplifier. An offset resulting from two
different sources with a slightly mismatched capacitor is reviewed. For example,
one of the four capacitors in Figure 3-5 is mismatched as follows:
(3.3)
Let’s assume the op amp has an infinite DC gain and zero input referred offset. From
charge conservation, the charge stored at each node of the differential input of op
amp can be described as follows
12---– LSB⋅ offset_RA + offset_quant.
12--- LSB⋅≤ ≤
Cs1 N C⋅=
Cs2 N C⋅=
Cf1 C=
Cf2 1 ε+( ) C⋅=
28
June 3, 1996
(3.4)
. (3.5)
AssumeVboc = Voc for simplicity. Then, during the reset phase (φ1 = “1”), Va1 and
Va2 becomeVoc because the residue amplifier is shorting its output to input of the
op amp through switchMf11 andMf21 due to DC gain of the op amp. During the
amplifying phase (φ2 = “1”), Va1 andVa2 become equal. Therefore, eq. (3.4) and
Figure 3-5 Schematic of offset canceling switched-capacitor amplifier
Vbic
M11(φ1)
M21(φ1)
M12(φ2)
Mf11(φ1)Mf12(φ1)
Mf21(φ1)Mf22(φ1)
Mf13(φ2)
Mf23(φ2)
VbocCf1
Cs2
Cf2
M22(φ2)
Cs1
Va1
Va2
+Vin2
+Vic
-Vin2
+Vic
+Vo2
+Vco
Vboc
-Vo2
+Vco
Cs1 Voc Vic
Vin
2-------+
–
Cf1 Voc Vboc–( )+
Cs1 Va1 Vbic–( ) Cf1 Va1 Voc
Vo
2------+
–
+=
Cs2 Voc Vic
Vin
2-------–
–
Cf1 Voc Vboc–( )+
Cs1 Va1 Vbic–( ) Cf1 Va1 Voc
Vo
2------+
–
+=
29
June 3, 1996
(3.5) becomes
. (3.6)
From eq. (3.6), we can find that
1. The offset is due to difference between the output common mode of the
previous stage (Vic) and the input common mode voltage (Vbic) when the
amplifier is amplifying the residue. And the offset can be found due to the
difference between the biasing voltage ofCf (Vboc) and the op amp output
common mode voltage (Voc).
2. The other offset is due to the injected chargeQinj from Mf11 andMf21 to
the node of input differential pair of the op amp at the end ofφ1= “1” which
can be modeled as the input common mode difference (Qinj = Cs1·δV =
Cs2·δV).
3.2.2 Gain inaccuracy of residue amplifier
The gain deviation from the ideal gain in a residue amplifier increases the
DNL of the A/D converter as shown in Figure 3-6. In order to avoid a missing code
at the end of the transition, the tolerable gain error (ε) can be expressed as
(3.7)
whereG is interstage gain, a unit of 1LSBis a resolution of coarse quantizer,Vr is
input full scale, andr is the number of bits of resolution of the sum of the following
subconverters. Since
Vo 1N 2+N 1+------------- ε
2---⋅+
N 1 ε2 N 1+( )-----------------------–
VinNε
N 1+------------- Vbic Vic–( )–=
Gideal Gactual–( ) 12---LSB⋅ 1
2--- 2
r–Vr⋅ ⋅<
30
June 3, 1996
, (3.8)
Therefore,
(3.9)
the gain accuracy required at the residue amplifier is determined by the sum of the
following subconverters resolution. The gain inaccuracy arises from capacitor
mismatch and the finite DC gain of the residue amplifier.
The gain of the op amp can be represented by the product of the
Residue
Vin
+Vr
-Vr
-Vr/2 - Vr/4 Vr/4 Vr/20
Amplifiedgain too small
Vin0 +Vr/2-Vr/2
A/D convertercharacteristic
Negative DNL
Residue
Vin
+Vr
-Vr
-Vr/4 - Vr/4 Vr/4 Vr/20
Amplified gain too large
Vin0 +Vr/2-Vr/2
A/D convertercharacteristic
positive DNL
Positive DNL
negative DNL
Figure 3-6 Effects of interstage gain error
1LSB Gideal⋅ Vr=
ε 2r–
=
31
June 3, 1996
transconductance to the output and output impedance where the signal current
generated from the differential pair flows through the cascode stage. As the
impedance at the output goes high, not all the current generated from the differential
pair can pass through the cascode stage. This means that the input impedance of the
cascode stage is not low any more. Therefore, a voltage swing develops at the input
of the cascode stage which is represented asG1 in Figure 3-7. The output (Vout) of
the amplifier can be represented as
(3.10)
whereG(= G1•G2) is the overall DC gain of the op amp, andCgd is the gate to drain
Vin G1 G2
Cload
Cf
Cgd
Vout
Ci
Cip= wiring + Cgs
Figure 3-7 Schematic for calculating required DC gain with Millercapacitor (Cgd)
Vo
Ci
Cf 11G---- 1
Cip G+1Cgd Ci+
Cf------------------------------------------+
⋅+
------------------------------------------------------------------------------------------= Vin
Ci
Cf----- 1 1
G----– 1
Cip G+1Cgd Cs+
Cf------------------------------------------+
Vin≅
32
June 3, 1996
capacitance in the input differential pair. The gain error should be less than 2-r,
which is tolerable from eq. (3.9). Therefore, the overall DC gain,G, should be
. (3.11)
This tolerable gain error is calculated from the static requirement which applies at
low conversion rates, whereas the unavoidable gain error due to incomplete settling
of the op amp in the ADC can be observed in the high conversion rate.
There are two major sources of static gain inaccuracy. The one gain
inaccuracy occurs from the capacitor mismatch, and the other gain inaccuracy
occurs from the finite DC gain of the OP amplifier as shown in eq (3.11).
3.3 Capacitor and resistor mismatch
3.3.1 Capacitor mismatch
The matched capacitors or precision capacitor ratios have been used
extensively for many years to make accurate A/D and D/A converters
[55][93][104], filters, and precision amplifiers. Because the capacitor matching
accuracy plays an important role in performance, many studies have been reported
on this topic [37][39][56][85][86][95].
There are several mismatch error sources in MOS capacitors. The first error
source consists of long-range, gradient related systematic errors, which are strongly
correlated for all capacitors on the same chip. These can be kept to a minimum by
G 2r
1Cip G+
1Cgd Cs+
Cf------------------------------------------+
>
33
June 3, 1996
using unit-capacitor layout techniques with a common centroid geometry [55].
The second error type results from uncorrelated random effects of edge
variations and deviations of oxide thickness and permittivity of MOS capacitors.
These random errors decide the ultimate limitation on the achievable accuracy of
MOS analog integrated circuits. The systematic and random capacitor mismatches
are calibrated in the prototype ADC.
The voltage coefficients of small signal capacitance can limit the accuracy
of the ADC. For MOS capacitors on heavily doped N+ back plates, about 30 ppm/V
voltage coefficients have been reported[56]. And McCreary reported the
temperature dependence of MOS capacitors measured approximately 25 ppm/C.
Capacitor hysteresis and MOS threshold voltage hysteresis due to dielectric
absorption in the capacitor has also been reported [39][95].
The 10-bit and 8-bit capacitor ratio mismatch was measured[55][93] in the
early days of MOS ADCs. A 9-bit capacitor matching accuracy has been reported
using a binary weighted capacitor array which is made of 25X25µm poly-N+
diffusion in NMOS technology[86] where the capacitor matching between two
minimum unit capacitors was better than 10-bit. And the measured capacitor
matching between 26 ~ 90 fF unit capacitor has been measured at 0.1~1% [37]. In
addition, layout rules which makes it possible to achieve 0.1% accuracy for the
individual systematic error sources with unit capacitor in the 20~40µm range has
also been reported [57].
34
June 3, 1996
3.3.2 Resistor mismatch
The matching properties of the resistor is one of the limiting factors in ADC
and DAC performance such as the reference voltage for comparators, DAC output
of a subconverter block in ADC, and DAC output itself. The reference voltage for
each comparator can be generated from one of the 2n resistor cells connected
between two reference voltages at the end of the resistor string. The integral
nonlinearity and differential nonlinearity of ADC are dependent upon that of the
resistor string, especially in the flash and subrange type. In some of 8~10 bits
subrange [11][12][53][83], two-step[72], and pipeline[41] ADC, the resistor has
been used to generate a DAC output to form a residue for the following stage. The
matching of resistor string and the operation speed was proven by the 10-bit 50
MHz DAC[4][70].
To find the resistor matching requirement for ann-bit resistor string withN-
bit matching, assume that the resistor values are normally distributed with meanR
and standard deviationσR. Then, the mean and the variance of them-bit resistor
string (RSm) which consists of 2m resistors connected in series, can be describe as:
(3.12)
Since the worst deviation from the ideal value occurs at the mid-point of the resistor
string as shown in Figure 3-8, we can model this as two big segments of resistors.
mean RSm( ) 2m
R⋅=
Var RSm( ) 2m σR
2⋅=
35
June 3, 1996
Eq. (3.12) can be written such that each segment matching of a resistor string
can be represented as normal distribution with
. (3.13)
The deviation must be less than± 1/2 LSB ofN-bit ADC from the gain accuracy
requirement. Assuming that the each segment of the resistor string can be
represented as a mean value and a standard deviation, this resistor matching
condition can be described as
< 1/2 LSB of N-bit
RSN/2=Normal (2N/2 R, 2N/2σ2)
2N/2
2N/2
Resistor Value
# of resistor string
Ideal line
Figure 3-8 Matching requirement in resistor string with n-bit precision andN-bit accuracy
mean RSn 2⁄( ) 2n 2⁄
R⋅=
Var RSn 2⁄( ) 2n 2⁄ σR
2⋅=
36
June 3, 1996
(3.14)
To maximize the effect of mismatch, one part of the segment has a positive sign and
the other has a negative sign in the variation. With this assumption, eq. (3.14)
becomes
(3.15)
wheren is the resolution andN is the linearity in bits [12]. For example, if 4-bit
resolution and 10-bit linearity is needed,σR/R should be < 0.27%.
In order to achieve good matching, all resistors in the DAC should be built
of the same basic resistor element. Three effects are considered to have an impact
on relative accuracy: geometry (which is determined by shape), width, and length,
resulting in local mismatches, gradients of sheet resistance, and variations in the
polysilicon-metal contacts. In hand-crafted analog design, it is not unusual to
design well-matched resistors without any bends. In a flexible layout generator for
different resolutions (2N resistors), the resistors must contain bends or the area
requirement would become excessive. Effects that decrease matching due to
deterministic errors caused by bends, lithography, and etching are minimized by
using an identical basic resistor cell for all matched resistors. In addition, better
matching can be obtained by increasing width and length of a resistor basic cell,
because most of the randomness stems from the perimeter due to lithography. The
12--- 1 1
2N
------– 2
n 1–R 2
n 1–( ) 2⁄ σR±
2n 1–
R 2n 1–( ) 2⁄ σR± 2
n 1–R 2
n 1–( ) 2⁄ σR±+--------------------------------------------------------------------------------------------------------------
12--- 1 1
2N
------+
.≤ ≤
σR
R------ 2
n 1–( ) 2⁄ N–=
37
June 3, 1996
gradients of the sheet resistance can be eliminated in the first order by layout in the
cross coupled manner[72]. Another matching problem stems from contacts
interconnecting a string resistors. The widely varying contact resistant becomes
important to get a good matching in a low resistor sting especially in high-resolution
converters. Further, the contacts should be avoided in the current path because it can
lead to contact alignment error by mask tolerance.
3.4 Amplifier design
3.4.1 Residue amplifier
Figure 3-9 shows the switched capacitor amplifier with offset
compensation. At the sampling phase, the sampling behavior depends on the unit
gain bandwidth and phase margin of the circuit. But at the amplify phase, the
settling behavior mostly depends on the closed-loop time constant of the amplifier
only. Because the feedback factor (β) is smaller than 1, the phase margin is not an
issue at the amplifying phase.
The feedback factor (β) during the amplifying phase is
(3.16)
and the time constant (τ) is
. (3.17)
Since
βCf
Cf Cip Cin+ +----------------------------------=
τ Req Ceq⋅=
38
June 3, 1996
Figure 3-9 (a) Schematic of residue amplifier with offset compensation(b) During sampling phase (c) During amplifying phase
Ss
Sf1
Cf
Co
Csm
Cip
Ssmpl
Samp
VinVoutVe
Sf2
VinCsm
Cip
Cf
Co (= Cip + Cload )
Vout
Cf
Csm
CipVoutgm
Ve
(a)
(b)
(c)
Co (= Cip + Cload )
39
June 3, 1996
(3.18)
and
(3.19)
whereCsmis an input sampling capacitor,Cf is a feedback capacitor,Cip is an input
differential pair capacitance including wiring, andCop is a parasitic capacitance
from an op-amp output device and from wiring. Then, the time constant (τ)
becomes
. (3.20)
Figure 3-10 plots time constant from eq. (3.20) with a varying sampling
capacitor size ( ) where a gain of amplifier is 2 and with the following
parameters: in the case where an amplifier gain isA ( ), the optimum
time constant can be retained when the optimum feedback capacitor( ) and the
optimum sample capacitor( ) are
Req 1 gmeff⁄=
1 β gm⋅( )⁄=
Cf Cip Cin+ +( )Cf
----------------------------------------- 1gm------⋅=
Ceq Co1
1Cf----- 1
Cin Cip+----------------------+
----------------------------------+=
Cload Cop1
1Cf----- 1
Cin Cip+----------------------+
----------------------------------+ +=
τCip Cin Cload Cop Cin Cip+( ) Cload Cop+( ) Cf⁄+ + + +
gm--------------------------------------------------------------------------------------------------------------------------------------------------=
Csm
Csm A Cf⋅=
Cfop
Csmop
40
June 3, 1996
. (3.21)
By choosing a following capacitive load equal to the input capacitor
, (3.22)
the optimum feedback capacitor ( ) and the optimum input capacitor ( )
becomes
. (3.23)
Figure 3-10 Time constant vs. sampling capacitor
0.0 1.0 2.0 3.0Csm (Sampling Capacitor Size in pF)
0.60
0.65
0.70
0.75
0.80
0.85
Tim
e C
onst
ant
Gm = 14mS, Cpin = 460fF, CL = 2.0pF, Gain (C sm/Cf) = 2
CLCpin
Cf
Csm
Gm
VinVout
Cfop
Cload Cop+( ) Cip⋅A
-----------------------------------------------=
Csmop A Cload Cop+( ) Cip⋅ ⋅=
Cload Csm=
Cfop Csmop
Cf
Cip Cop⋅A A 2+( )⋅----------------------------=
Csm ACip Cop⋅
A 2+---------------------
⋅=
41
June 3, 1996
3.4.2 Effect of feedback switch size
Once the optimum capacitor sizes are chosen, the next step is to decide upon
a size for the switches. All the switches (Ssmpl, Samp, Sf2) exceptSf1 in Figure 3-9
(a) should be sized such that the time constant of switch resistance and the
associated capacitor is small enough so that it does not decrease the -3 dB
bandwidth of the amplifier. But the size of theSf1 is selected differently. The
optimum switch size ofSf1 mayincrease the -3 dB bandwidth by introducing a zero
to help position the closed-loop poles at a desired location. The transfer function
from Vin to Vout is
(3.24)
whereYf is an admittance in the feedback path. Since ,
the equation (3.24) becomes
(3.25)
The denominator of equation (3.25) can be expressed as
Vout
Vin----------
Csm Yf gm–( )⋅
s2
CL Csm Cinp+( )⋅ ⋅ s Yf CL Cf Cinp+ +( ) gm Yf⋅+⋅ ⋅+--------------------------------------------------------------------------------------------------------------------------------------------=
Yf 1 Rf 1 s Cf⋅( )⁄+( )⁄=
Vout
Vin---------- Csm sCf 1 gmRf–( ) gm–( )⋅ s
2CLCfRf Csm Cinp+( )
s CL Cf+( ) Csm Cinp+( ) CfCL+( ) Cfgm+ +
⁄=
42
June 3, 1996
. (3.26)
where
. (3.27)
The zero location can be easily estimated by equating a feedback current (if)
with gm current as shown in Figure 3-11
, (3.28)
or by using equation (3.25). Also, a closed loop pole location can be found from
Figure 3-10 if the sampling capacitor (Csm) is determined by the time constant (τ)
requirement. The value of feedback resistor (Rf) can be estimated from eq. (3.28)
by substitution ofs with .
The transient step input response of the correspondingRf is shown in Figure
3-12. From the transient response in Figure 3-12, when theRf is larger than the
optimum value, peaking can be observed in the frequency domain and the overshoot
Den s( ) gmCf
s2
Csm Cinp+( ) CLRf
gm---------------------------------------------------
s CL Cf+( ) Csm Cinp+( ) CfCL+( )gmCf
--------------------------------------------------------------------------------------- 1+ +
gmCfs
2
ω02
--------- sQω0----------- 1+ +
⋅=
⋅=
ω0
gm
CLRf Csm Cpin+( )---------------------------------------------=
QCf
CL Cf+( ) Csm Cpin+( ) CfCL+------------------------------------------------------------------------------ gmRfCL Cs Cpin+( )⋅=
gmVa
Va
Rf 1 s Cf⋅( )⁄+( )--------------------------------------------=
1 τ⁄–
43
June 3, 1996
appears in the step response. However, the step response of the system can not be
exactly estimated from theQ factor because the system has a zero. Therefore, the
optimum step response can be found from the transient simulation. With more than
one overshoot, ringing increases the settling time drastically. The optimum
feedback resistor value is converted to the MOS switch size forMf2.
3.4.3 Non-resetting Sample-and-Hold Amplifier
The major advantage of using a non-resetting sample-and-hold amplifier is
that the subsequent stage can sample the amplifier output during the full period,
unlike the resetting amplifier which provides a valid output only during half of the
clock period. If interchannel offset mismatch is the one of the major performance
Figure 3-11 A zero introduced by feedback switch
gm
Csm
Cf Rf (from S f1)
CLVin
Vout
Cinp
Vin
Csm
Cinp
Cf Rf
CL
Vout
gmVa
=YfVa
RL
44
June 3, 1996
Figure 3-12 Transient step response with different switch size
0.0e+00 1.0e-08 2.0e-08 3.0e-08 4.0e-08time (sec)
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
Am
plitu
de (
V)
1.10e-08 1.20e-08 1.30e-08 1.40e-08 1.50e-08 1.60e-08
time (sec)
0.80
0.90
1.00
1.10
Am
plitu
de (
V)
1.20
(a)
Vin
1.2 K
1.0 K
0.5 K
0.0 K
0.8 K
1.2
Vout 12...
45
June 3, 1996
Cload
Cload
Figure 3-13 (a) Non-reset Track and Hold amplifier schematic (b) Duringsampling and holdingII period (c) During holdingI period
Vin+
Vout-
s1(φ1) s3(φ2)
s2(φ1) s4(φ2)
s5(φ2) s6(φ1)
C1
C2
C2d
Vbin
Vbo
Vout+
Vin+
Vout-
C1
C2
C2d
Vbin
Vbo
Vout+
Vout-
C1
C2
C2d
Vout+
(a)
(b)
(c)
Cip
Cip
Cip
Cload
46
June 3, 1996
limitation in ADCs such as a parallel architecture, an offset cancellation scheme is
required. However, the bandwidth of unity gain feedback is set up by the op amp,
and this is usually much lower than that of the passive sampling. Therefore, the non-
resetting amplifier is more important in a high speed ADC than offset cancellation.
The half circuit of a non-resetting sample-and-hold amplifier [64] is illustrated for
simplicity in Figure 3-13. During a sampling period (Figure 3-13 (b)), the sampling
bandwidth on the sampling capacitor (C1) is determined by theRC time constant of
C1 and associated resistance from the MOSFET switchesS1 andS2. Therefore, the
sampling bandwidth can be as large as 1GHz[6]. Meanwhile, the holding capacitor
(C2) is holding a previously sampled value whileC1 is sampling a new input.
During holdingI period (Figure 3-13 (c)), the sampling capacitor (C1) is inserted in
the negative feedback path and the dummy holding capacitor (C2d) is inserted in
positive feedback. Even though there are two capacitor (C1, C2) in the feedback
path, the charge from theC2 in the feedback path is cancelled out byC2d which is
the same size asC2, andC1 will be the only feedback capacitor to determine the
output of the op amp. The feedback factors at the tracking period (βtrack) and at the
holding period (βhold), are
(3.29)
βtrack
C1 C2 C2d–+
C1 C2 C2d Cip+ + +-------------------------------------------------=
βhold
C2
C1 Cip+--------------------=
47
June 3, 1996
where Cip is the capacitance of the wiring, diffusion of switches, and input
differential pair. IfC2 = C2d, eq. (3.29) can be simplified as
(3.30)
The effective capacitive loading at the output at the holdingI period (Co_holdI) and
at the holding period (Co_holdII), are
(3.31)
Therefore, the time constants associated with each period are
(3.32)
From eq. (3.32), in order to reduce the time constant (τholdI) during holdingI period,
theCd should be decreased, because not only does the effectivegm decrease asβ
decreases (eq. (3.29)), butCo_holdI also reduces the effective capacitive loading. As
Cd reduces, however, the time constant (τholdII) during holdingII period reduces.
Therefore,Cd has to be larger than a certain value so that the sample-and-hold
output can recover from injected charges due to capacitor switching during the
holdingII period.
βtrack
C1
C1 C2 C2d Cip+ + +-------------------------------------------------=
βhold
C2
C2 Cip+--------------------
.=
Co_holdI 1 βtrack–( ) C1 C2+( ) Cload 1 βtrack+( ) C2d+ +=
Co_holdII 1 βhold–( )= C2 Cload C2d .+ +
τholdI
Co_holdI
gm βholdI------------------------=
τholdII
Co_holdII
gm βholdII--------------------------
.=
48
June 3, 1996
3.5 Analysis of clock jitter
A small clock jitter in the high speed Nyquist analog-to-digital converter is
required so as not to reduce signal-to-noise ratio, especially at input frequencies
near Nyquist input [2][29]. The average error power due to clock jitter is given by
(3.33)
wherem is the number of samples in one period and is the sampled value of .
For a sinusoidal input waveform, and ideal samplers which exhibit a timing skew,
(3.34)
and
(3.35)
where is the value sampled at nT and is the value sampled atnT with the
timing jitter noise . For the values of and , the error power, in eq. (3.33)
becomes
(3.36)
which for small values of timing jitter may be approximated by
Ej xiˆ xi–
2⟨ ⟩
i 1=
m
∑=
xiˆ xi
xn A ω nT⋅( )sin⋅=
xnˆ A ω nT δ–( )⋅( )sin⋅=
xi xnˆ
δ xi xnˆ Ej
EjA
2
m------ ω nT δ–( )⋅( )sin ω nT⋅( )sin–( )
n 1=
m
∑⋅=
A2
m------ 1 ωδ( )cos–( )
n 1=
m
∑⋅=
A2 ω2δ2
2!------------ ω4δ4
4!------------ …+ +
⋅=
49
June 3, 1996
(3.37)
Therefore, signal-to-noise due to clock jitter (SNRj) is
(3.38)
whereδ is the R.M.S. value of clock timing jitter. TheSNRj vs.δ is plotted in Figure
3-14. This plot shows that the clock timing jitter should be less than 5 ps (rms) to
avoid reducing the SNR by 3 dB from quantized noise at 50 MHz input frequency.
EjA
2ω2δ2
2------------------≅
SNRj 10 A2
2⁄
A2ω2δ2
2⁄-------------------------log⋅=
20 ωδ( )log⋅–=
Figure 3-14 Signal to noise due to clock timing jitter at 10 MHz, 30 MHz, and50 MHz input frequency
0.0e+00 5.0e-12 1.0e-11 1.5e-11 2.0e-11Rms clock timing jitter (sec)
40.0
50.0
60.0
70.0
80.0
90.0S
igna
l-to-
Noi
se (
dB)
50
June 3, 1996
3.6 Analysis of non-linear effect at multi-channel
Multi-channel parallelism in an ADC can increase conversion speed by the
number of channels, but there are well-known problems such as offset, gain and
timing mismatches among the channels which do not arise in digital systems
[2][10][29][71][74].
3.6.1 Timing mismatch in the channels
The effect of timing mismatch among the channels has been analyzed and
documented[29]. The analysis can be summarized as follows. Let the original
sampled data sequenceS = [x(t0), x(t1), x(t2), …, x(tm), …, x(tM), x(tM+1), …] be
T (= 1/ fs)
MT
t0 t1 t2 t3 tM tM+1 tM+2
MTMT
Time
Amplitude
Figure 3-15 Sampling of M channel parallel ADC withTiming offset
51
June 3, 1996
divided intoM subsequencesS0, S1, S2, …, SM-1 as follows:
. (3.39)
The Sm is obtained by uniformly sampling the signalx(t+tm) at the rate 1/MT.
Assume
(3.40)
we can represent the original sequence, S, as
(3.41)
Then, the digital spectrum,X(ω), of S can be represented as
(3.42)
Let rmbe the ratio ofmT- tm to the average sampling periodT, which is
(3.43)
then we can rewrite eq. (3.42) as
S0 x t0( ) x tM( ) x t2M( ) …, , ,[ ]=
S1 x t1( ) x tM 1+( ) x t2M 1+( ) …, , ,[ ]=
S2 x t2( ) x tM 2+( ) x t2M 2+( ) …, , ,[ ]=
:
Sm x tm( ) x tM m+( ) x t2M m+( ) …, , ,[ ]=
:
SM x tM 1–( ) x t2M 1–( ) x t3M 1–( ) …, , ,[ ]=
Sm x tm( ) 0 0 … M 1 zeros–( ) x tM m+( ) 0 0 …, , , ,, , ,[ ] ,=
S Smzm–
m 0=
M 1–
∑= .
X ω( ) 1MT-------- X
a ω 2πkMT---------–
ej ω 2πk MT⁄( )–[ ] tm
k ∞=
∞
∑ ejmωT–
m 1=
M 1–
∑⋅=
tm mT rmT–=
52
June 3, 1996
(3.44)
Since the Fourier transform of the sinusoidal input with the frequencyf0, is
, (3.45)
eq. (3.44) becomes
(3.46)
where
(3.47)
From eq. (3.46) and (3.47), we can find some important consequences of
timing offset in the multi-channel A/D converter with sinusoidal input. First, from
(3.47), the sequenceA(k) is periodic onk with the periodM, hence the spectrum
X(ω) given by eq. (3.46) is periodic onω with a period equal to 2π/ T (= 2πfs). The
M line spectra uniformly spaced on the frequency is comprised in one period of the
spectrum with neighboring spectra separated by thefs/ M. The main signal is
located atf0 and the magnitude isA(0), while them-th spectral line is located at
fo+(m+M)fs and with magnitude |A(m)| as shown in Figure 3-16. SinceA(k) in eq.
X ω( ) 1T--- 1
M----- e
j ω 2πk MT⁄( )–[ ]– rmTe
jkm 2 π M⁄( )( )–
m 0=
M 1–
∑
k ∞–=
∞
∑⋅=
Xa ω 2πk
MT---------–
⋅
Xa ω( ) 2πδ ω ω0–( )= and ω0 2πf0=
X ω( ) 1T--- A k( ) 2πδ ω ω0– k
2πMT--------
–k ∞=
∞
∑⋅=
A k( ) 1M-----e
jr m2πf0 fs⁄–e
jkm 2π M⁄( )–
m 0=
M 1–
∑= .
53
June 3, 1996
(3.47) is a discrete Fourier transform of the sequence of [ ,m= 0,
1, 2, …, m-1], by Parseval’s theorem,
. (3.48)
Therefore, the signal-to-noise ratio (S/N), due to timing offset sampling in the
multiple-channel [29], can be expressed as
. (3.49)
Let’s consider the A/D converter with two channels. By definition ofrm, r0=0 and
Freq .
Amplitude
|A(0)|
|A(1)|
|A(2)| |A(M-2)||A(M-1)|
|A(0)|
|A(1)|
|A(-1)|
fsf0 f0+ 2fs/M
f0+ fs/M f0+ (M-2)fs/M f0+ (M-1)fs/Mf0- fs/M
Figure 3-16 Digital Spectrum of M channel parallel ADC withtiming offset
1 M⁄( ) ejr m2πf0 fs⁄–
A k( ) 2
k 0=
M 1–
∑ 1=
S N⁄ 10 log10A 0( ) 2
1 A 0( ) 2–
----------------------------
dB⋅=
54
June 3, 1996
, hence,
(3.50)
and from eq. (3.49), we have
(3.51)
where assuming that the average sampling frequencyfs is
greater than the Nyquist frequency ( ).
3.6.2 Offset and gain mismatch between the channels
The gain and offset mismatches among the channels can be modeled as
parallel ADC with different conversion gain and offset as shown in Figure 3-17.
1– r0 1< <
A 0( ) 2 2 π r1f0 fs⁄( )cos=
S N⁄ 20 10 π r1 f0 fs⁄( )cot( ) dBlog⋅=
1 2⁄– r1 f0 f⁄s
1 2⁄< <
f0 fs⁄ 1 2⁄<
Figure 3-17 Model for the ADC ini th channel with gain and offsetmismatch
Ideal ADC
bi
ai
Ideal ADC
bi+1
ai+1
Ideal ADC
b1
a1
Input
55
June 3, 1996
The transfer characteristics of two converters with offset and gain mismatch
between two channels and the best fit line minimizing error power for each transfer
curve is depicted in Figure 3-18. The error in ADC ofi th channel can be
represented as
(3.52)
where
(3.53)
and
(3.54)
ith channel
Output Code
Figure 3-18 Multi-channel ADC transfer characteristic
jth channel
min error powerchannel
∆i(x)
δi(x) X
best fit line
εi x( ) δi x( ) ∆i x( )+=
δi x( ) xiˆ aix bi+( )+=
∆i x( ) ai amin+( ) x bi bmin–+=
56
June 3, 1996
in which is the quantized level ofx, andai andbi are error minimization terms
corresponding to the best fit converter gain and offset. In eq. (3.52), (3.53), and
(3.54), indicates that the error would exist if the ADC ini th channel were
used alone, while indicates an additional error which exists when the ADC
in i th channel is used as part of a parallel converter. The best fit gain and offset of
the ADC ini th channel is represented byai andbi, while the best fit gain and offset
of the whole parallel converter is given byamin andbmin. The average error power
for anM channel converter[2] is represented as
. (3.55)
From eq. (3.55), the distortion due to the gain mismatch (ai) and offset mismatch
(bi) and the distortion due to each ADC can be calculated respectively. Therefore,
the signal-to-distortion ratio of ADC [71] in Figure 3-17 is represented as
(3.56)
where is a variance of gain and is a variance of offset in each channel of
ADC, and A is an amplitude of sinusoidal input.
Figure 3-19 illustrates a reconstructed spectrum of sinusoidal input with
offset mismatches and gain mismatch among theM channel of ADC. Assume that
the sampling periods are uniform and the input sinusoidal magnitudes are different
in each channel (Figure 3-17) such that the sequences of input sinusoids are ,
xiˆ
δi x( )
∆i x( )
Ep1m---- δi
2⟨ ⟩ ∆i2⟨ ⟩+
i 1=
m
∑=
SNR 10 10 σ2a
2σ2b
A2
-----------+
log–=
σ2a σ2
b
a1ejω0T
57
June 3, 1996
,......, , ,..... andrm = 0, theA(k) in eq. (3.47)
can be rewritten as
(3.57)
for the gain mismatches inM channel case as shown in Figure 3-19 (a). Therefore,
fs/M 2fs/Mfin
Amp(dB)
Freq
fs/M 2fs/Mfin
fs/M-fin fs/M+fin 2fs/M-fin 2fs/M+fin
Amp(dB)
Freq
(a)
(b)
Figure 3-19 Reconstructed spectrum of sinusoidal input (a) offsetmismatch (b) gain mismatch
a2ejω0 2T( )
aM 1– ejω0 M 1–( ) T
aMejω0MT
A k( ) amejkm 2π M⁄( )–
m 0=
M 1–
∑=
58
June 3, 1996
from eq. (3.46) we can note that the frequency of spurious tones are the same as that
of non-uniform sampling case such that the frequency of spurious tone is atfs/M ±
fin, 2fs/M ± fin,......, (M-1)fs/M ± fin.
The offset mismatch among the channel generates a fixed pattern noise. In
the frequency domain this is manifested as frequency tone at multiples offs/M as
shown in Figure 3-19 (b), because the offsets (bk) can be interpreted as a periodic
signal withM/fs period sampled at the frequencyfs.
The simulated total distortions due to gain and offset mismatch in 2-channel
with ideal ADC model are shown in Figure 3-20. The gain is matched to better than
0.1% and the offset is less than 0.5 mV in ± 1.0 V input full scale so that the total
distortion from gain mismatch and the tone due to fixed pattern noise are less than
-65 dBc, respectively.
3.7 Signal dependent clock feed through
The signal dependent charge feed through in analog MOS switches causes
distortion. The analytic expression and characterization for the switch induced error
voltage on a sampled capacitor has been studied in [81] and [103]. In order to avoid
the problem from voltage dependent clock feed through, dummy switches[14] and
the transmission gate[101] have been investigated. But using those methods can not
cancel this effect perfectly due to mismatch and randomness in the device.
The systematic way to reduce voltage dependant clock feed through is by
59
June 3, 1996
0.0 0.4 0.8 1.2 1.6 2.0Offset mismatch between 2 channel (mV)
80.0
75.0
70.0
65.0
60.0
55.0
50.0
SF
DR
(dB
c)
(a)
(b)
Figure 3-20 (a) SFDR with gain mismatch in 2 channel ADC (b) SFDR withoffset mismatch in 2 channel ADC with ± 1 V full scale input
0.00 0.10 0.20 0.30 0.40Gain mismatch between 2 channel (%)
80.0
75.0
70.0
65.0
60.0
55.0
50.0
SD
R (
dB)
± 1.0V input
60
June 3, 1996
using bottom-plate sampling [43][44][66][90]. The two differentφ1 andφ1d clock
signals are used instead of singleφ1 clock signals to cancel the voltage- dependent
charge injection from the sampling switch (Ssmpl), as shown in Figure 3-21. At the
end ofφ1 = “1”, the unit gain feedback switchSs will inject the chargeQs to node
Ss
sf1
Cf
Co
Cin
Cip
Ssmpl
Samp
Vin
VoutVe
Vs
φ1d
φ2d
Csp
φ1
sf2φ2d
φ1d
Qsmpl1Qsmpl2
Qs
φ1
φ1d
φ2
φ2d
(a)
(b)
Figure 3-21 Offset compensated voltage amplifier with voltageindependent clock feed through (a)Schematic (b) timing
61
June 3, 1996
Ve. At the end ofφ1d, the sampling switchSsmplinjects the chargeQsmpl1andQsmpl2
which cause the signal voltage-dependent charge injection, to nodeVe, and the
injected chargeQsmpl1andQsmpl2 are stored at a parasitic capacitorCip andCsp. The
sampling capacitor,Csmpl memorizes the amount of charge (Qsmpl1) flowing
throughCsmplas a voltage difference on the sampling capacitor. Assuming the DC
gain is infinite and the offset at the input is negligible, the injected charge due toSs,
Qs, is constant all the time and is independent of the input voltage. During phase
φ2= “1”, the input signal charge and the signal dependent injection charge (Qsmpl1)
stored inCip are removed throughCin to ground. Since the charge due to the input
signal voltage dependent injection does not come from the feedback capacitor (Cf)
but from a stored charge atCip, the input signal voltage dependent charge injection
from the sampling switch does not effect the output voltage. Also, the part of input
signal voltage dependent injected charge (Qs2) does not effect the output voltage
because both terminals of the parasitic capacitor (Csp) are connected to a low
impedance node.
If this scheme is implemented in a fully differential circuit, differential
injected charge due toSs (Qs) is cancelled out by the opposite side injected charge
due toSs. Therefore, the differential output is not effected by the charge injected
from the switches.
62
June 3, 1996
3.8 Metastability
Metastability is a phenomenon typically associated with binary digital logic
system, particularly those using flip-flops for synchronization of signals. A latch is
expected to store two distinct states, representing a logic 1 and a logic 0. All flip-
flops are also capable of generating a third, indeterminate level between 1 and 0
levels. This can occur when setup and hold times are violated, causing a clock edge
to occur while an input signal is still in transition. The intermediate state is
described as being metastable because the condition will eventually decay, not
necessarily in a monotonic fashion, to one of the valid logic levels. The
metastability problem has been analyzed by theoretical approaches and
measurement [24][26][77][98] to focus on the understanding of the phenomena and
by ac small signal analysis to optimize a latch or flip-flop [33].
Metastability has long been understood as a limitation in the design of high-
speed converters because the comparator occasionally could not have enough time
to resolve a small differential input to a valid logic level in a short clock cycle. To
reduce errors arising from comparator metastability, the comparator architecture
with cascaded latches [45] and cascaded sub-comparators [109] have been reported.
In addition, the latch with a series of connected M/S flip-flops has been analyzed
[18].
The probability that a cascade of two latches as shown in Figure 3-22(a) is
in a metastable state can be explained as follows. First, consider a single latch case.
63
June 3, 1996
t
Vout+-Vout-
Vout-Vout+
α exp(t/τ) saturated
(b)
(c)
Figure 3-22 (a) Comparator with preamplifier and cascade of two latchwith time constantτ1 and τ2 (b) Latch schematic duringregeneration (c) Transient response of the latch duringregeneration phase (d) Metastability region in coarse quantizerwith 15 comparator
latch
τ1
latch
τ2Vin Dout
Preamp
A
clk φ1 clk φ1
(a)
≈
vth1
vth2
vth14
vth15
Ful
l Sca
le
Met
asta
ble
regi
on
(d)
64
June 3, 1996
When the latch is switched from reset mode to regenerative “latch” mode as shown
in Figure 3-22(b), the output voltage can be approximated by a simple
expression[98]:
(3.58)
whereV0 is the output of the latch,A is the gain in “reset” mode,Vi is the input
voltage at the start of regeneration,t is the time since the onset of positive feedback,
and τ is the time constant of the latch in positive feedback. The output voltage
roughly follows this exponential growth until it reaches the valid logic level as
shown in Figure 3-22(c). During this period, we can consider the regenerative
circuit to have an effective gain which is a function of time:
. (3.59)
As the clock rate of the ADC is increased, the amount of time the latch spends in
positive feedback is reduced and the effective gain reached at the end of half a clock
cycle is lower. A lower effective gain makes it more likely that an input voltage will
be too small to be amplified to a full logic level, and thus increases the chances for
an error. The effective gain(Acomp) of a comparator in Figure 3-22 (a) is:
(3.60)
whereT is the period of clock (φ), τ1 and τ2 are the time constant of each latches,
A1 andA2 are the gains in “reset” mode andApreampis a preamplifier gain. Since the
metastable state occurs around each threshold of the comparator as shown in Figure
V0 AVitτ--
exp=
Aeff V0 Vi⁄ AVitτ--
exp= =
Acomp Apreamp A1exp 2T τ1⁄( )[ ] A2 2T τ2⁄( )exp[ ]=
65
June 3, 1996
3-22 (d), the probability (Pmetastable) that the comparator output is at metastable
condition depends on the number of thresholds in the quantizer. Therefore,
Pmetastable can be calculated:
. (3.61)Pmetastable
Valid digital level( )Acomp
-------------------------------------------------- full scale( )
2N
----------------------------⁄=
66
June 3, 1996
Chapter 4
System and Circuit Design
This 10-bit 100 M Samples/sec ADC is focused on how to reconfigure the
architecture of a paralleled, pipelined ADC to solve all three of the known
limitations discussed in the previous chapter, that is the timing skew, the gain
mismatch of residue amplifier, and the offset mismatch between the channels in
paralleled ADC architecture. To achieve a 10-bit, 100 MS/s in 1.0µm CMOS
technology, a 2-channel, 3-stage ADC with a single non-resetting sample-and-hold
amplifier and a reconstruction DAC at the front end has been used, as shown in
Figure 4-1. The underlying rationale of this architecture are as follows. A non-
resetting full-speed (100MHz) single sample-and-hold at the front-end generates a
held output which is distributed to both channels, thus avoiding the problems of
timing skew. The front S/H and reconstruction DAC are optimized to run at the full
speed because these are the most sensitive parts of the ADC to gain and offset
67
June 3, 1996
50 M
Hz
F/F
F/F
F/F
EC
CD
OU
TF
/F
50 M
Hz
F/F
F/F
F/F
EC
CD
OU
TF
/F
24 4
4b4b
44b
S/H
100
MH
z
50 M
Hz
25 M
Hz
10b
S/(N
+D)
7 b
linea
rity
Diffe
rent
ial O
ffset
< 1
LSB
2
4b
4b4b
24 4
4b4b
44b
2
4b
Vin
Figure 4-1 Block Diagram of Architecture
4-b
offs
etca
ncel
latio
n
68
June 3, 1996
mismatches as shown in Figure 3-20. The S/H circuit, using passive sampling for
large bandwidth, might face a larger offset than the active sampling using an offset
cancellation (or auto-zero) scheme. The offset mismatch between the residue
amplifier has been reduced by applying an offset canceling scheme to each residue
amplifier. Since the offset canceling is an active sampling scheme which requires a
unit gain feedback, it takes more time than passive sampling. The bandwidth of unit
gain feedback is 300MHz and that of S/H is 250MHz. Since the resetting S/H
amplifier allows 5ns for following amplifier to sample its output, the minimum
bandwidth requirement of the cascade of S/H and sampling circuit is 200 MHz.
Therefore, it is very difficult to implement in a single channel. However, it is
possible to accomplish this using non-resetting S/H, because the S/H output does
not reset between samples, allowing the full clock period (10ns) for the residue
amplifier in two channels to operate on the held sample. The other source of the
distortion in the parallel pipeline architecture is the gain mismatch between the
residue amplifier. As shown in Figure 4-2, a pipeline consisting of 1~2 bit/stage will
suffer from the gain mismatch because the capacitor can be matched up to 0.1%.
Since our goal is to achieve a high conversion rate without extensive trimming, a
conversion of 3-bits/stage has been chosen, even though the converting multi-
bit/stage will dissipate more power than 1-bit/stage to obtain constant bandwidth
with larger gain.
A full-speed 4-bit quantizer and reconstruction DAC follows the
69
June 3, 1996
non-resetting S/H, distributing the residue to time-interleaved channels.
Subsequently, the residue amplifier output needs to be quantized only to 7-bits,
which means that a of gain error of up to 1% can be tolerated. Since the capacitor
mismatch is about 0.1~0.2%, the residue amplifier gain mismatch due to the
capacitor in the 4-bits/stage conversion does not adversely effect accuracy.
However, since a residue amplifier input-referred inter-channel offset mismatch is
1 mVrms from the measurement of various device mismatches, which can cause a
0.00 0.01 0.02 0.03 0.04 0.0540.0
50.0
60.0
70.0
80.0
90.0
SD
R (
dB)
1-bit
4-bit
3-bit
2-bit
N bitDAC
X 2N
Combination Logic
N bitADC
∞ bitADC
Vin
Gain mismatch between residue amplifier
Figure 4-2 SNR with gain mismatch 2 channel pipeline ADC
70
June 3, 1996
tone larger than 60 dBc at 2 Vp-p input full scale, a programmable inter-channel
offset correction circuit has been added to keep the tone below -65dBc from the
input signal. This offset correction circuit has been inserted at the second residue
amplifier, where the sensitivity is the lowest to errors in this circuit.
Once the residue signal, which is the difference between S/H output and
reconstruction DAC, is interleaved into two channels, then the residue signal is
processed at half of the full speed, 50MHz in each channel. Since the ADC converts
4-bits/stage, the required residue amplifier gain is 8, which is impossible to achieve
in 1µm CMOS at 50 MHz clock. This problem is overcome by using a cascade of
gain-of-2 and gain-of-4 amplifiers where the each gain-of-2 amplifier output
distributes its output to two gain-of-4. This breakdown will keep the gain-
bandwidth constant, as shown in Table 4.1. However, the second bank of residue
amplifiers prior to the third quantizer consists of a gain-of-2 amplifier cascaded with
a gain-of-4 amplifier, both operating at 50MHz. Here, an incomplete settling is no
longer a source of inaccuracy in the final 4b quantizer. And at the last gain-of-4
amplifier, a binary-weighted array of small capacitors injects programmable
Table 4.1 Gain-bandwidth of linear component
close loopgain
operatingfrequency
S/H 1 100 MHz
Gain-of-2 RA 2 50 MHz
Gain-of-4 RA 4 25 MHz
71
June 3, 1996
correction charges derived from a DC reference into the input of gain-of-4
amplifiers for correction of inter-channel offset. Since the gain-of-4 amplifiers in
the first residue amplifier bank operate at 25MHzl, there will be one more tone at
fs/4 in addition to fs/2. However, the offset mismatch between two gain-of-4-
amplifiers in the first gain-of-8 residue amplifier bank is reduced by the gain of the
gain-of-2 amplifier so that the input referred offset mismatch in the two gain-of-4-
amplifiers is negligible. The tone at fs/4 was less than -70 dBc from the
measurements on a test chip, so an offset cancellation circuit is added only to reduce
a fs/2 tone.
Since the second and third 4-bit quantizers operate at half of the full speed,
50MHz, the bandwidth of the preamplifiers before the comparators may be reduced
in principle. In general, if the output load is fixed, the bandwidth linearly depends
on the size of the device. Unfortunately, this is not possible in practice. The random
offsets of the comparators depend on the size of the input differential pair. Instead
of scaling the preamplifier, the input capacitance of the quantizer can be reduced to
almost half, and the power dissipation at the preamplifier can be reduced
significantly, by utilizing a interpolation scheme in the first stage preamplifier
output. In addition, the offset variation of the comparator with interpolation
becomes less than that of the comparator without interpolation. However, since
each preamplifier has to drive a larger capacitive load, the settling time of the
preamplifier can be longer.
72
June 3, 1996
Each quantizer encodes its output as Gray code, and one bit of the output is
dedicated to error-correction between quantizers. The 4-bit digital output obtained
from the first quantizer is interleaved in the two digital paths. In each digital path,
the two additional 4-bit digital outputs emerging from the second and third
quantizers are merged into the error correction circuit (ECC), in addition to the
4-bits digital output obtained from the first quantizer. The digital error correction
circuit uses information from the extra 2-bits and provides a digitally error-
corrected 10-bit digital output. All the error-correction logic and pipeline delay
registers are on-board.
The ADC digital outputs were provided outside of the chip with two
complementary 10-bits two 50MHz channels to make it easy to acquire the data.
Differential output buffers drive ECL logic levels into a remotely terminated logic
analyzer, without producing large data-dependent current glitches on the chip
power supply.
4.1 Timing and requirement of system
The operation of the ADC converter is best understood with a timing
diagram. Figure 4-3 illustrates the timing diagram of the ADC front end referenced
to a 100 MHz conversion rate. A capacitor and switch acquires a sample of the
balanced input voltaget = 5 ns, and att = 10 ns, the capacitor connects in feedback
around the S/H op amp. The first 4-bit quantizer follows the S/H output fromt =10
73
June 3, 1996
to 15 ns, and is then strobed. The quantizer output code, which is ready at about
t= 16 ns, is stored in the master flip-flop and the slave flip-flop selects one tap from
a 4-bit resistor ladder DAC to reconstruct itself as an analog threshold at20 ns.
Meanwhile, over t=10 to 20 ns, the gain-of-2 amplifier, for example, in channel 2 is
in reset mode while its input capacitor is following the S/H op amp output. At
t=20 ns, this capacitor connects to the reconstruction DAC output, and the op amp
goes into amplify mode, thus amplifying the different charges, which constitutes the
residue. Over this duration, the corresponding amplifier in channel 1 settle to 2
sampleamplify
T H T H T H T H T H
sample amplify sample amplify sample amplify
sampleamplify sampleamplify
S/Hwave form
S/H
Comp.
DAC
Ch1Residue Amp
Ch2Residue Amp
Figure 4-3 Timing Diagram of ADC front end
10 nsA
cqui
re n
ew s
ampl
e
Tran
sfer
new
sam
ple
t = 0ns t = 20nst = 10ns t = 30ns t = 40ns
74
June 3, 1996
times the previous sample’s residue, and then starts to follow the next S/H output.
The 10-bit ADC requires that the output of input S/H be linear to better than
10-bit, and the 15 thresholds of the first reconstruction DAC should be at least 10-
bit accurate. There is no strict requirement on gain accuracy of the input S/H,
because a variable gain amplifier (not shown) located in front of the ADC would
adjust its gain to fully load the ADC input. Similarly, a fixed input offset of the ADC
is tolerable.
Figure 4-4 (a) illustrates the block diagram of the first residue amplifier
bank. The residue signal amplified by the gain of 2 amplifiers is interleaved to the
gain of 4 amplifiers, as shown in Figure 4-4 (b). Therefore, the clock period of the
gain-of-4 amplifier can be two times longer than that of the gain-of-2 amplifier and
4 times longer than that of the S/H amplifier. Although each amplifier output returns
to zero for offset cancellation, the multiplexed output of the gain-of-4 stages
amplifier bank does not return to zero.
The gain of the first bank of residue amplifiers is sufficiently accurate to
align its full-scale output voltage with the reference of the subsequent quantizer
within ± 1/2 LSB at 7-bits. Although their input-referred offset may be any
reasonable value, the difference in these offsets between the channels should be less
than 1/2 LSB at 10-bits to avoid a noticeable fixed-pattern at the output. As
mentioned before, there is a provision for programmable correction for an inter-
channel offset difference at the last residue amplifier.
75
June 3, 1996
Figure 4-5 (a) illustrates the block diagram of the 7-bit pipeline
subconverter block in each channel. The second and third 4-bit quantizers use
interpolation to reduce their input capacitance. The quantizer input capacitance and
the wiring capacitance are the only load to the previous gain-of-4 amplifier during
the first half of 20 ns, from 0 ns to 10 ns, while the following amplifier is in amplify
4
2
4Settling Time < 10ns
From S/H
DAC
To 2nd
Settling Time < 20ns
Quantizer
S A S A S A S A S A S A
Sample Sample SampleAmp Amp Amp
Amp Sample Sample SampleAmp Amp
20 ns 10 ns
2
4
4
(a)
(b)
Figure 4-4 First residue amplifier bank (a) Block diagram(b) Timing diagram
76
June 3, 1996
mode during the first half of each 50 MHz clock cycle, as shown in Figure 4-5 (b).
Therefore, the output of the first residue amplifier bank can settle quickly during the
first half of the 20 ns period because the sampling capacitor of the gain-of-2
A S A S A S A S A S
A S A S A S A S AS
24
44b 4b
4 4b2
4b
4-bits 4-bits
From1st residue
2nd residue
(a)
amplifier bank
Firstresidue amp.
bank waveform
2nd quant. latch
DAC
X 2
X 4
3rd quant. latch
(b)
Figure 4-5 7 bit pipeline converter(a) block diagram (b) timing diagram
20ns 20ns
2nd quantizer 3nd residueamplifier bank
3rd quantizer
77
June 3, 1996
amplifier in the third stage does not capacitively load the gain-of-4 amplifier in the
second stage. During the second half of the period, the following gain-of-2
amplifier in the third stage is switched in and samples the output of the gain-of-r
amplifier in the second stage. After the gain-of-4 amplifier in the first residue
amplifier bank, the timing diagram of the second and subsequent quantizers are
similar to that of the first quantizer except the clock is running at half of the full-
speed, 50 MHz.
This chip requires only one 100 MHz clock from the externally-supplied
clock generator, and it internally generates two non-overlapping phases at this
frequency, as well as two phases at one-half and one-fourth this frequency.
4.2 Non-resetting Sample-and-Hold amplifier
The input sample-and-hold (S/H) must provide a balanced, non-reset
output, and must be capable of acquiring a new sample every 10ns. Let’s assume
that a resetting S/H is used with a 50% duty cycle. Within a 5 ns period, the S/H
amplifier should settle to a sampled output. This sampled output has to drive a
preamplifier of the comparator whose output should settle at least 4-bit resolution,
and the latch has to regenerate a thermometer code from this preamplifier output, as
shown in Figure 4-6 (a) [42][61]. This idle time (during sampling period) of the S/H
amplifier is shortened by introducing an analog double sampled pipeline scheme by
the cascading of two conventional resetting unity-gain S/H amplifiers where the
78
June 3, 1996
S/H
AD DA
VinADC
resetting
H X H X H
S/H-1
AD DA
VinADC
resetting
S/H-2
resetting
H X H X H X HX
XH H H X H XX
S/H
AD DA
VinADC
non-reset
H H H H
(a)
(b)
(c)
resetting S/H output
Latch
resetting S/H-1 output
resetting S/H-2 output
non-resetting S/H output
Latch
Latch
acquiring new sample
Figure 4-6 Block diagram and timing diagram of (a) resetting S/H(b) double resetting S/H (c) non-resetting S/H
79
June 3, 1996
latter one is delayed by a half clock cycle as shown in Figure 4-6 (b) [50]. The
output of the first S/H drives the first quantizer, while the output of the second one
drives the residue amplifier.
These two resetting S/H amplifiers can be replaced by a non-resetting S/H
circuit [64] which allows a full 10 ns period for the following amplifier to sample
and cancel an offset from itself using an auto-zeroing scheme, as shown in Figure
4-6 (c). The fully differential non-resetting S/H amplifier is realized with 6
capacitors, unlike the 2 capacitors in the resetting amplifier shown in Figure 4-7.
The capacitor values of C3(C4) should be equal to that of C5(C6), while the
capacitor values of C1(C2) can be different from C3(C4) and C5(C6). The
operation of the S/H amplifier can be explained in three different stages, even
though its operation repeats every two clock phase.
Vin+
Vin-
Vout+
Vout-
s1(φ1) s2(φ2)
s9(φ2) s11(φ1)
s3(φ1) s4(φ2)
s5(φ1) s6(φ2)
s7(φ1) s8(φ2)
s10(φ2) s12(φ1)
C2
C1C3
C4
C6
C5
top platebottom plate
Vbin
Vbo
Vbo
Figure 4-7 Non-resetting sample and hold amplifier
80
June 3, 1996
Vout +[nT]
Vout -[nT]
s11(f1)
s12(f1)
C3
C4
C6
C5
Vbo
Vbo
Vout +[(n+ )T]
s2(φ2)
s9(φ2)
s4(φ2)
s6(φ2)
s8(φ2)
s10(φ2)
C2
C1C3
C4
C6
C5
12_
Vout -[(n+ )T]
Vin+[nT]
Vin-[nT]
s1(f1)
s3(f1)
s5(f1)
s7(f1)
C2
C1
Vbin
12_
(a)
(b)
Figure 4-8 Non-resetting sample and hold Amplifier: (a) atφ1, (b) atφ2
Sample Period Hold Period
Transfer Period
81
June 3, 1996
1. Sampling period (Figure 4-8 (a)): s1(s3) and s5(s7) are closed, s2(s4) and
s6(s8) are open, and Vin+[nT] (Vin-[nT]) is sampled in capacitor C1(C2).
2. Transfer period (Figure 4-8 (b)): C1(C2) is switched into a feedback path,
C5(C6) is connected to the input of the amplifier. C5(C6) is used so that the
sampled charge on C1(C2) can be transferred to the output without
interference by the holding capacitor C3(C4). The charge from the holding
capacitor C3(C4) will be cancelled by that of C5(C6), and C3(C4) will be
charged up to the new value, Vin+[nT] (Vin-[nT]).
3. Holding period (Figure 4-8 (a)): The C1(C2) and C5(C6) are
disconnected from the feedback path of the amplifier and the C3(C4) is
holding the charge from the last phase. Therefore, the output value of the
amplifier will be the same as the last phase output Vin+[nT] (Vin-[nT]). The
C1(C2), which is disconnected from the amplifier, is sampling the next
available input Vin+[(n+1)T](Vin-[(n+1)T]).
These operations can be explained by the following equation. During(φ2)
(4.1)
Since ,
C1 C3+( ) Vout+
n12---+
T⋅ C5 Vout-
n12---+
⋅+
C1 Vin+
nT[ ]⋅ C3 Vout+
nT[ ]⋅+=
C5 Vout-
nT[ ]⋅+
Vout Vout+
V– out-
= =
82
June 3, 1996
(4.2)
and ,
(4.3)
During φ1
. (4.4)
Therefore, the eq. (4.3) and (4.4) demonstrate that the output of the non-resetting
S/H is held constant fromφ2 toφ1, as shown in Figure 4-3.
A switch-capacitor passive circuit tracks and samples the input (passive
sampling). Because the bandwidth is determined by the on-resistance of the switch
and the sampling capacitor, the passive sampling circuit has been successfully
demonstrated that it can sample the 900 MHz signal [6][7]. Here, the bandwidth of
the passive sampling circuit has been chosen to be 300MHz, which is adequate to
capture the 50 MHz Nyquist input signal.
The major disadvantage of a non-resetting S/H amplifier scheme is that the
hold (C3, C4) and dummy (C5, C6) capacitors in Figure 4-7 not only lower the
feedback factor (β), but also act as the capacitive loading at the output, as mentioned
in section 3.4.3. Therefore, the non-resetting S/H amplifier has to have larger gm at
the input differential pair than the conventional resetting S/H amplifier. Figure 4-9
Vout n12---+
TC1
C1 C3 C5–+---------------------------------- Vin nT[ ]⋅=
C3 C5–C1 C3 C5–+---------------------------------- Vout nT[ ]⋅+
C3 C5=
Vout n12---+
T Vin nT[ ]=
Vout n 1+( ) T[ ] Vout n12---+
T Vout nT[ ]= =
83
June 3, 1996
illustrates the feedback configurations of non-resetting S/H and resetting S/H in
Figure 4-6 (b) where two resetting S/H are used. Assume the resetting amplifier has
been down scaled by half of the non-resetting amplifier so that total power
dissipation in the front end are equal. Therefore, the following equation can be
assumed;
Vout-
C1
C2
C2d
Vout+
Cp
gmNR
CL
Vout-
C1
Vout+
Cp
gmR
CL
(a) Non-resetting S/H
τΝR ≅ βNR⋅gmNR / CL
NNRo≅ NNRi / βNR
τR ≅ βR⋅gmR / CL
NNRo≅ NRi / βR
(b) Resetting S/H
Figure 4-9 Feedback capacitor configuration of non-resetting S/Hand resetting (conventional) S/H
84
June 3, 1996
(4.5)
wheregmNR andgmR are the transconductance of differential pair of non-resetting
S/H and resetting S/H, andNNRi andNRi are the input referred noise in non-resetting
S/H and resetting S/H, respectively. The feedback constant of non-resetting S/H and
resetting S/H are represented as follows;
(4.6)
Assume the feedback capacitorsC1, C2, C2d, andCp are equal value for simplicity,
the eq. (4.6) becomes
(4.7)
The settling time constant of non-resetting S/H and resetting S/H,τNR andτ R, are
(4.8)
From eq. (4.5),τNR andτ R are equal if the load capacitor CL is much greater than
the feedback capacitors, which is true in most cases. The output noise of the non-
gmNR 2 gmR⋅=
NNRi1
2------- NRi⋅=
βNR
C1
C1 C2 C2d Cp+ + +-----------------------------------------------=
βR
C1
C1 Cp+-------------------=
βNR14---≅
βR12---≅
τNR βNR gmNR CL⁄⋅=14--- gmNR CL⁄⋅=
τR βR gmR CL⁄⋅=12--- gmR CL⁄⋅=
85
June 3, 1996
resetting S/H is given byNNRo while the output noise of the resetting S/H is given
by NRo. Both values are calculated by taking the input referred noise and dividing
it by the feedback factor of the amplifier,β. This is shown in eq. (4.9). As the
feedback is decreased, the gain and the output referred noise of the amplifier
increase.
(4.9)
Using simple models of the two sample and hold circuits, it can be shown that the
input referred noise of the resetting and the non-resetting S/H are equal. Since
, due to the gm argument in eq. (4.5), andβNR is smaller, as
given in eq. (4.6), the S/H input referred noise of the non-resetting S/H is 40% more
than that of the resetting S/H during the first half of the period. During the second
half period, the feedback configurations are equal but once again
. Therefore, during the second half of period, the noise of the
resetting S/H is 40% more than that of the non-resetting S/H. In the non-resetting
S/H, the holding capacitor C3 (C4), shown in Figure 4-8, samples the output noise
during the transfer period, and sums up the output noise during hold period in a rms
fashion. Therefore, the total ADC input referred noise of the non-resetting S/H is
similar to the total input referred noise of the resetting S/H. Additionally, the
resetting S/H output is valid only for 5 ns with a 100 MHz conversion rate, it is very
difficult for the following residue amplifier to sample the S/H output while it is
NNRo NNRi βNR⁄= 4 NNRi⋅=
NRo NRi βR⁄= 2 NRi⋅=
NNRi1
2------- NRi⋅=
NNRi1
2------- NRi⋅=
86
June 3, 1996
canceling the offset. A summary of the non-resetting S/H is given in Table 4.2.
The on-resistance of S1 and S3 in Figure 4-7 can introduce a harmonic due
to the variation of the input voltage. This distortion can be minimized by choosing
a large switch size or by selecting a proper PMOS and NMOS switch size ratio so
that the on-resistance of the CMOS switch is constant in the maximum input signal
range. The other source of distortion is the voltage dependant clock feedthrough.
This distortion is eliminated to the first order, providing a 2 phase clock with a
delayed edge is used for bottom-plate sampling.
4.3 A 4-bit AD-DA
The 4-bit AD-DA block consists of a differential 4-bit quantizer, two
resistor ladders, a bank of differential DAC switches, and a 4-bit Gray code
encoder, as shown in Figure 4-10. The 4-bit quantizer is made of 15 comparators
Table 4.2 Simulation summary of non-resetting S/H amplifier at 70oC
Parameter Value
Differential input full scale ± 1.0 Vp-p
Input capacitance 2.2 pF
Single end output range 2.1 ~ 3.3 V
Sampling bandwidth 300 MHz
Power dissipation 140 mW
SDR 67.8 dB
3rd harmonic -71.5 dBc
87
June 3, 1996
and a resistor ladder. Each comparator has a 4-input preamplifier, latch, and master-
slave flip-flop (F/F). The DAC consists of a bank of NOR gates, switches and a
resistor ladder.
The sampled signal from the non-resetting S/H output is latched to 15
comparators at the middle of each period. Then the comparator output is latched to
the F/F and the latched data are converted to thermometer code. The NOR gate is
arranged so that the NOR output can select one of the 16 DAC switches based on
the thermometer code, and is fed to the input of the Gray encoder.
Figure 4-10 4 bit AD-DA Block Diagram
Res
isto
r La
dder
Preamp Latch F/F NOR
Analoginput
Enc
oder
4 bitGrayCode
DACoutput
Res
isto
r La
dder
DASW
15
16
1
2
3
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June 3, 1996
4.3.1 Comparator circuit
The fast, low latency quantizer used in all blocks comprises comparators to
amplify the difference between the balanced analog input and differential taps from
a resistor ladder. There are 3 major design issues in a comparator circuit in this ADC
architecture. The first issue is high operation speed, because it should quantize data
at full speed, 100 MHz, in the first ADDA block. The second is small kick-back to
the reference ladder. The kick-back from the latch circuit during regeneration
disturbs the resistor ladder and will cause a longer DAC output settling time. The
last consideration is to minimize offset of comparator threshold voltage.
To address these issues, the 2-stage preamplifier followed by a latch has
been designed, as shown in Figure 4-11. The advantages of using a 2-stage amplifier
are as follows. First, the offset variation due to the random device mismatch and the
asymmetry of layout in the latch circuit can be reduced by a preamplifier gain.
Therefore, the preamplifier gain is determined so that the offset contribution from
the latch is less than those from the preamplifier. The second reason is that a 2-stage
preamplifier can reduce kick-back from the latch during a regeneration period more
effectively than a single stage. A cascaded gain stage is one of the best ways to
achieve a wide-band amplifier. The last reason is that a 2-stage preamplifier can be
easily modified in layout to implement an interpolation scheme in second stage
preamplifiers and latches.
The sampled input (Vin+) and the reference voltage (Vref+) are applied to
89
June 3, 1996
one side of the differential pair and the opposite pair of the sampled input (Vin-),
and the reference voltage (Vref-) are applied to the other side of the differential pair,
as shown in Figure 4-12. The preamplifier senses the difference between two
balanced inputs by subtracting the output currents of two differential pairs, and
amplifies it by 5 times prior to the latch input. If the S/H has a -3 dB bandwidth of
200 MHz, the preamplifier should also have a 160 MHz -3 dB bandwidth so that the
Vi- Vr- Vr+ Vi+
Vo-Vo+
2nd Stage
Latch
Preamplifier
1st Stage
Preamplifier
Figure 4-11 Comparator Circuit
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June 3, 1996
preamplifier output can settle its output in± 1/2 LSB of 4-bits in 5 ns. The cascade
of two stages results in a 250 MHz preamplifier, which is sufficiently wideband to
track a full-scale Nyquist frequency input.
There are two different ways to arrange the input differential pair. One way
is by connecting balanced input, Vin+ and Vin-, in one differential pair and
balanced reference, Vref+ and Vref-, in the other pair, as shown in Figure 4-13 (a).
The other is by connecting Vin+ and Vref+ in one differential pair and Vin- and
Vref- in the other pair, as shown in Figure 4-13 (b). The advantage of using the latter
scheme is that the differential pairs in the critical comparator detecting the closest
Vin+
Vref+
Vref-
To Latch
Vin-
Figure 4-12 Preamplifier Input arrangement
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June 3, 1996
threshold to the input are always biased close to maximum gain and bandwidth. The
preamplifier at each end in the former scheme has to compare the largest reference
difference with the input. The differential pair in that preamplifier is biased so that
the only small part of the tail current flows to the one of differential pair, which
decreases the transconductance (gm) of the differential pair and the preamplifier
gain. Therefore, the input referred offset from the latch circuit becomes
unacceptably large.
The latter preamplifier is used. The output common-mode of the S/H is
slaved to the common-mode voltage of the ladder (its center tap). Any error or noise
in these common-mode values is, in any case, subtracted at the comparator output.
However, the input common-mode range of the preamp first stage must be
nominally equal to the reference full-scale.
Vi- Vr- Vr+ Vi+Vi- Vi+ Vr- Vr+
(a) (b)
Figure 4-13 First stage preamplifier schematic (a) applying differentialinput in one differential pair (b) applying differential input ineach differential. pair, respectively
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June 3, 1996
The simulated characteristics of the comparator are summarized in Table
4.3. Two type of simulation has been performed to ensure that the quantizer has a
4-bit linearity. The one type of the offset is due to the device mismatch such as
threshold (Vt), device parameter,β (= µ CoxW/L), in the MOSFET. The other type
is dynamic offset to the recovery from the overdrive. With this gain and with careful
latch design to avoid a large common-mode jump when it is strobed, the comparator
offset due to device mismatch is determined by the input differential pairs. The
Monte Carlo simulation to find a random threshold offset mismatch at the
comparator input uses the parameters specified in Table 4.4 [69]. The dynamic
offset is an overdrive value to get the correct latch output when the input is changing
from maximum to minimum in one clock period. The simulated dynamic offset in
Table 4.3 Comparator specification
Parameter Designed Value
-3dB BW > 250 MHz
DC Gain at zero-crossing > 5
Input Offset(σ) 6.8 mV
Input Cap 55.7 fF
Power Diss 5.8 mW
Table 4.4 Parameters for device mismatch
Parameter Value
∆ β (%)
∆ Vt (mV)
2 W L⋅( )⁄
15 W L⋅( )⁄
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June 3, 1996
this system is 40 mV with a full input swing of± 1.0 V.
4.3.2 Latch Circuit
The dynamic and static types of latch has been reviewed (Appendix A). The
dynamic latch (Figure 4-14 [35]) does not dissipate static power, but only power
momentarily during the phase transition. The input differential pair (M1, M2) of the
dynamic latch, which is normally off, turns on for the comparison at the phase
transition. The gate capacitance change in the differential pair will cause a
kickback, which might disrupt the exact zero-crossing information. The kickback
degrades the performance of ADC, especially for multi-bit/stage subquantizer and
Vinp Vinn
Latch
Vdd
VoutnVoutp
Figure 4-14 Schematic of dynamic latch
M3
M1 M2
M4 M5
M6M8 M9
M7
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June 3, 1996
interpolation subquantizer. However, in high speed ADC, the power dissipation
between static and dynamic latch becomes negligible. In addition, the dynamic
latch is slower in regeneration than the static one because there is time delay in
dynamic latch until all the transistors become active and start to regenerate the
output.
The static latch is used because the major concern in designing a latch
circuit as the one shown in Figure 4-15, is operation speed. During reset(φ1) period,
switches S1, S2, and S3 are on, Vout1+ and Vout1- are shorted together, and the latch
samples the preamplified error voltage through switches on two common-source
PFETs (M1, M2), which are the loads to a cross-coupled pair of NFETs (M3, M4).
During comparison mode,φ1 goes low to strobe the latch, and all the switch
F/F
φ1
φ1
Preamp
Source Follower Buffer
φ1
Preamp
F/F
Figure 4-15 Latch schematic
S1
S2 S3C1 C2
Vout+ Vout-
M1 M2
M3 M4
M5 M6
M8M7
vin- vin+
C1p C2p
C1op C2op
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June 3, 1996
S1, S2, and S3 are off. The difference of drain currents between M1 and M2 initiates
regeneration at the node Vout+ and Vout-, and the cross coupled M3 and M4
accelerate the regeneration by forming a positive feedback until the output nodes
(Vout+ and Vout-) reach the Vdd and GND. Furthermore, the bootstrap capacitor C1
and C2 speed up regeneration. The operation speed of the latch can be determined
by the regeneration time constant (τ).
, (4.10)
where ,gmn of M3 (or M4), gmp of M1 (or M2) andCtotal total
capacitance at Vout+ or Vout-. The source follower buffer (M5, M6, M7, M8)
reduces wiring capacitance and increases capacitance matching at the output node
by placing M5, M6, M7, and M8 closer to the latch output, and prevents the
kickback from the F/F. The simulated regeneration time constant of the loaded latch
is 0.27 ns. The width of S1 should be as small as possible because it adds parasitic
junction capacitances from itself to the latch output node, and can introduce
undesirable gain (Vout+/Vin-), decreasing the bit-error rate at the latch. However, its
width should be large enough to reset node Vout+ and Vout- at the end of the reset
phase, otherwise the latch will have hysteresis.
When the latch starts to reset its output, the master flip-flop (F/F)
disconnects its input from the latch output and transfers its output to the slave F/F,
as shown in Figure 4-16 (a). The master F/F not only holds the latch value while the
τCtotal
gmn α gmp⋅+--------------------------------=
α C1C1 C1p+-----------------------=
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June 3, 1996
Latch
F/FM
S
T = 1/ fs =10ns
F/F regeneration
(a)
(b)
Figure 4-16 (a) timing diagram of latch and FF (b) hysteresis of themaster slave FF (c) back-to-back inverter latch
t =0ns t =5ns t =10ns t =15ns
5ns
Master F/F out
Slave F/F out
meta-stable
T1 T2 T3
Vout-Vout+
(c)
Invaliddigital level
region
M F/F output
time
t0
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June 3, 1996
latch is resetting itself for the next sampled input, but also decreases the bit-error
rate. The master slave F/F has two meta-stable regions because it has a hysteresis
due to back-to-back inverter latches as shown in Figure 4-16 (b) (c). Assume the
master F/F output is at “0”. Even though the latch starts to build its output in a
positive direction, the master F/F output does not cross zero by at t=5ns unless the
latch output is sufficiently large that it can overcome and release the back-to-back
inverter F/F. In addition, the slave F/F has two meta-stable regions like the master
F/F. Therefore, there exists a certain initial latch input range that drives the slave
F/F output into the invalid digital output range at the end of T3 (t= 15ns), causing
the meta-stable output of the comparator. This can be estimated with the invalid
digital range and the regeneration time constant of the slave latch, in the same way
as the latch without hysteresis. During T2, the master F/F output is disconnected
from the latch output, and continuously regenerate through the back-to-back
inverter F/F, whose output derives the slave F/F. Because of a 4.5ns delay from the
slave output to the delay F/F in the error correction circuit, the digital output from
the comparator (slave F/F) has to be in a valid digital level at approximately the end
of T2 period. From the simulation results shown in Figure 4-17, the initial
differential voltageδ (0.01mV) of the master F/F output is large enough to develop
the slave output in valid digital levels at the end of the T2 period.
Simple direct calculation of the latch input referred metastable region
(LMR) by two cascaded exponential terms can be in error, since the latch output is
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June 3, 1996
buffered by the source follower, there is some delay between latch out and the
master reset state. The delay is not only from the latch buffer, but also from the
master itself because it has to erase the previous data and enter the reset state.
However, it is impossible to exactly estimate the delays caused by each
components.
The input metastable region ofδ (0.01mV) may be obtained by indirect
slope mapping from the master output to the latch output. Thisδ in the master F/F
range can be converted to the latch output range with a certain ratio depending on
the slope of the master F/F output crossing the “0” and the slope of the latch output
at the delay (td) before. The mapped metastable region (∆Vout) is estimated as
Time
Time
Master F/F out
latch out
td
0
F / FMaster
F / FSlave
Latch
Preamp
0
Wiring delay4.5ns
Metastable regionδ = 0.01 mV
Vin
slope latch
slope MFF=0.7X109
Figure 4-17 Simulation result of latch and F/F
δ
T
Metastable region latch : ∆Vout ⋅exp(-(T-t d) / τ1)
∆Vout
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June 3, 1996
follow
. (4.11)
The latch input referred metastable region (LMR) is
. (4.12)
Since the latch output (Voutlatch) and the slope of the latch at time =T-td are
(4.13)
whereVinital is the initial value set for simulation of latch, the LMR becomes
(4.14)
Therefore the latch input referred metastable region can be estimated. By indirect
slope mapping between the master flip-flop and latch, time delay becomes an
independent factor from metastable region calculation. As shown in eq.(4.14), time
delay (td) cancels out to make LMR independent oftd. The only restriction in
selectingtd is to set the latch output less than 2.0 V, because the latch output
develops exponentially when it is less than 2.0 V. The time constant of latch (τlatch)
is designed to be 0.27ns.
∆Vout
slopelatch
slopemaster---------------------------
δ⋅=
LMR ∆Vout
T 2⁄ td–
τlatch--------------------–
exp⋅=
Voutlatch Vinital t τlatch⁄( )exp⋅=
Slopelatch t T td–=τlatch Vinital T td–( ) τlatch⁄( )exp⋅ ⋅=
LMR δ=τlatch Vinital T td–( ) τlatch⁄( )exp⋅ ⋅
slopelatch------------------------------------------------------------------------------------------
T 2⁄ td–
τlatch--------------------–
exp⋅ ⋅
δτlatch Vinital⋅
slopelatch--------------------------------⋅=
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June 3, 1996
The bit error rate (BER) can be calculated from the preamplifier gain, the
latch input referred metastable region (LMR), and the 1 LSB of the quantizer as
follows:
(4.15)
From eq. (4.15), the projected bit-error rate is lower than 10-10 for the loaded time
constants of this design.
4.3.3 Interpolated Quantizer
The input capacitance of the second and third quantizers are a large fraction
of the total capacitive load on the respective residue amplifiers preceding them. As
the second and third quantizers operate at only half of the full speed (50 MHz), an
interpolation scheme has been used to reduce the input capacitance of the quantizer,
while the input differential pair size remains constant so as not to increase the offset.
The interpolation is performed by rewiring the second stage preamplifier as shown
in Figure 4-18, which reduces the input capacitance by half with a simple
modification from the first 4-bit AD-DA. As expected, the DNL of the interpolated
comparators is less than that of the comparator without interpolation.
4.3.4 Reconstruction DAC
The reconstruction DAC consists of NOR gates, selection switches, and a
BER =LMR
(Preamplifier Gain) x 1 LSB / 2
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June 3, 1996
10-bit linear resistor ladder with 16 taps. NOR gates decode the 15 latch output in
the thermometer code into a 1-of-16 selection from switches connected to a 10-bit
linear resistor ladder, and the selected tap on the resistor ladder defines the
reconstructed analog threshold.
One resistor ladder can be shared between the AD and the DA to provide
references for the AD comparators, and also to provide a DA output as shown in
Figure 4-19. The 4-bit AD-DA block can be implemented in two ways, either by
placing the resistor ladder at the input or by placing it at the output. In the former
case (Figure 4-19 (a)), each NOR output is routed back to select the corresponding
tap from the resistor ladder which is used to provide references for the AD
Vref1
Vin
Latch1st stagePre-Amp
2nd stagePre-Amp
Interpolatedpre-amp
Encoder
Interpolatedpre-amp
Interpolatedpre-amp
(Vin- Vref1)
(Vin- )
Vref2
Vref1+Vref22
(Vin-Vref2)
(Vin- ) Vref2+Vref32
(Vin- ) Vref0+Vref12
Figure 4-18 Block diagram of interpolated quantizer
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June 3, 1996
Resis
tor L
adde
rPreamp Latch F/F NOR
AnalogInput
4 bitGrayCode
DASW
DACOutput
1
2
3
14
15
16
14
15
16
1
2
3
Enco
der
Wiring Cap.
(a)
Preamp Latch F/F NOR
AnalogInput 4 bit
GrayCode
DASW
Resis
tor L
adde
r
1
2
16
3
15
DACOutput
(b)
Enco
der
Figure 4-19 Two possible layouts of AD-DA using singleresistor ladder
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June 3, 1996
comparators. The delay due to the wiring capacitance causes the gain-of-2 amplifier
to momentarily develop its output in the wrong direction until the correct selection
switch closes. After the correct switch is selected, the output starts to converge in
the correct direction. Therefore, the wiring capacitance increases the amplifier
settling time by 2 times the delay due to the wires. For the latter case (Figure 4-19
(b)) where the resistor ladder is placed at the output of the AD-DA block, the
reference signals for the comparators are easily corrupted due to the coupling of the
large digital signals traveling nearby, because the 1 LSB of the quantizer is 0.125 V
while the digital output swing is 5 V.
With 2 separate resistor ladders, the signal flows unidirectionally from the
quantizer, through the encoder, into the reconstruction DAC in Figure 4-10. A
separate ladder for the DAC therefore eliminates the problems specified above.
The reference ladder for the DAC requires a total polysilicon resistance of
150 ohm, and is wider than that for the comparator to attain 10-bit accuracy in its
tap voltages and settling time. As in the Elmore delay model for the RC ladder,
which is
(4.16)
where Ri is the summed resistance from point to driving source andCi is the
capacitance at the pointi (as shown in Figure 4-20), the first and second resistance
is more important to shortening the settling time than the latter ones in first order
estimation. The resistance of the reconstruction resistor ladder and the selection
td RiCii
∑=
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June 3, 1996
switch have to be chosen so that the -3 dB bandwidth at the gain-of-2 residue input
is wider than 200 MHz, where the required -3 dB bandwidth in the gain-of-2
amplifier during the amplifying phase is at least 100 MHz.
4.4 Residue Amplifier
The residue amplifiers must be designed to reduce interchannel offset and
settling time, and to accurately align its full-scale output voltage with the reference
of the subsequent quantizer within 1/2 LSB at 7-bit. Unlike the S/H, these amplifiers
must be autozeroed to reduce their input offset and, therefore, the inter-channel
offset. At a minimum capacitor size of about 0.25pF, the capacitor ratios are
inherently accurate enough for 7-bit. The amplifier setting time is reduced by using
pipeline and parallel architecture inside a gain-of-8 amplifier bank, as shown in
Figure 4-1.
4.4.1 Gain-of-2 Amplifier
Figure 4-21 illustrates a schematic of a gain-of-2 amplifier. During
VinVout
R1 R2 R3
C1 C2 C3
τ ≈ R1(C1+C2+C3) + R2(C1+C2) + R3C3
Figure 4-20 Elmore delay model
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June 3, 1996
sampling period(φ1), the op-amp has its inverting input terminal shorted to its
output voltage (offset voltage of op-amp) through M5(M6) and hence, the
sampling capacitor Cs1 (Cs2) charges to , while feedback capacitor
Cf1 (Cf2) charges to . Since a largegm is required to overcome the small
feedback factor during the amplifying phase, the output of the op-amp becomes
underdamped in the presence of the output load during the resetting phase. A
damping capacitor Cc1(Cc2) is added at the output node. The resetting switch
size(M5,M6) is carefully chosen to increase the phase margin. At the end of the
sampling period(φ2), M5(M6) should open first to cancel the voltage dependent
Figure 4-21 Gain of 2 residue amplifier circuit
S/H+
DA+
DA-
S/H-
M1
M4
M2
M3
M5
M6
M7
M8
M9
M10
M 11
M12
Vout +
Vout -
Cs1
Cs2
Cf1
Cf2φ1
φ1
φ1
φ2
φ2
φ1
φ1
φ2
φ2
φ1
Cc1
Cc2
top platebottom plate
Voff
Vin Voff–
V– off
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June 3, 1996
charge injection through M1(M3), and then open M1(M3), M9(M10). The opening
of M5(M6) determines the sampling moment.
During the amplifying period(φ2), M1(M2) and M7(M8) are closed. The
bottom plate of the sampling capacitor is connected to the DAC output and forms
the residue. The residue is amplified by the ratio of Cs1 and Cf1.
4.4.2 Gain-of-4 amplifier
Figure 4-22 illustrates a schematic of a gain-of-4 amplifier. The gain of 4
amplifier works exactly the same as the gain-of-2 amplifier, except the feedback
capacitor Cf1(Cf2) is connected to the input instead of to the bias during sampling
M2
φ2M1
M3
M4
φ2
φ1
φ1
φ2
φ2
φ1
φ1
φ1
φ1
φ2
φ2
Cs1
top platebottom plate
Cs2
Cf2
Cf1Cc1
Cc1
Vin+
Vin-
Vout +
Vout -
M5
M6
M7
M8
M9
M10
Figure 4-22 Gain of 4 residue amplifier circuit
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June 3, 1996
period(φ1). The sampling capacitor Cs1(Cs2) and feedback capacitor Cf1(Cf2) are
charged to during sampling period(φ1). During amplifying period(φ2),
the bottom plate of Cs1(Cs2) is connected to bias voltage and the bottom plate of
Cf1(Cf2) is connected to output. Since the gain-of-4 amplifier does not need to form
a residue, the ratio between a sampling capacitor and a feedback capacitor does not
have to correspond to the gain of an amplifier. If a feedback capacitor is precharged
to the input voltage, the ratio between the sampling capacitor and a feedback
capacitor can be 1/3 instead of 1/4 in a gain-of-4 amplifier [42]. Therefore, the gain
of 4 amplifier can have a same time constant as gain of 3 amplifier by increasing the
feed back factor(Cfb/(Cfb+Csm)) from 1/5 to 1/4.
4.5 Super cascode amplifier
The residue amplifiers must be designed to allow quantization of the residue
to 7-bit accuracy. The op amps in these SC amplifiers must therefore have a large
DC gain, and their output must settle to sufficient accuracy so that the amplified
residue aligns with the full-scale of the subsequent quantizer. As shown in Figure
4-23, the fully differential super cascode amplifier architecture is used in all residue
amplifiers in this ADC. In order to meet a requirement at a first residue amplifier
bank, a dc gain of the opamp should be larger than 70 dB, because the accuracy of
the closed loop gain of 8 should be better than 1%. Since a dc gain of single cascode
structure designed in 1.0µm CMOS technology is less than 50 dB, a cascode
Vin Voff–
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June 3, 1996
amplifier with an auxiliary amplifier attached to the cascode transistors (M3, M4,
M5, and M6) is used to improve the DC gain without losing head room [5]. From
the simulation, 76 dB DC gain is obtained. A switched capacitor common feedback
is used, because it is linear under a wide dynamic range of differential output, and
can have a different common mode output level between resetting and amplifying
phase which maximizes the dynamic range of differential output [32].
4.5.1 Different common mode output level
The offset mismatch between 2 channels will appear as fs/2 and fs/4 tone in
FFT and reduce SNDR. Therefore, an offset cancellation scheme is essential to
CMFB
Vout - Vout +
Vout + Vout -
SC
M1
M3
M5
M7
M9
M2
M4
M6
M8
M10
Figure 4-23 Super cascode amplifier
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June 3, 1996
reduce a random offset mismatch. The offset should be sampled in the sampling
node and feedback capacitors by applying unit gain feedback to the OP amp in
resetting mode (autozero mode). Because of the unit gain feedback, the output of
the op amp is shorted to the inputs, which means that the output is biased at in the
input common-mode region. In amplify-mode, on the other hand, the maximum
signal swing requires that the output be biased in the middle of the output common
mode range. These two requirements are met at different common-mode points.
Therefore, the reference in the common-mode feedback loop alternates the
common mode level between 2.1V in autozero-mode and 2.7 V in amplify-mode,
as shown in Figure 4-24. This common mode level alternation scheme is done by
precharging two pairs of capacitors (Figure 4-25) [32]. During sampling phase, one
Input common modedynamic range output dynamic range
5 V
0 V 0 V
5 V
Common-mode Level
During Amplify
During Sampling
Figure 4-24 Input and Output common mode range
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June 3, 1996
pair of capacitor are connected in a common mode feedback loop, while the other
pair is precharged to the proper value used in amplifying the phase, and vice versa.
The only requirement to this scheme is that the common-mode feedback loop must
be almost as fast as the signal feedback loop around the op amp.
4.6 Error correction circuit and output buffer
4.6.1 Error correction circuit
The error correction circuit (ECC) consists of 3 blocks as shown in Figure
4-26 (a). The 4-bit digital word coded in Gray code from each quantizer is
converted to 4-bit binary code. The total 12-bit from three quantizer is fed into the
+
_+
_ +
_+
_
CMFB CMFB
+
_
+
_
Figure 4-25 Op amp Common-mode Feedback
During sampling phase During amplifying phase
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June 3, 1996
adder circuit. Because the threshold of the comparator has been shifted 1/4 LSB at
4-bit, only additions are required in this ECC. These additions do not require the
full 4-bit to 4-bit adder. It is implemented into the circuit based on simplified
Gray Binary
4-b
Gray Binary
4-b
Gray Binary
4-bE
C A
dder
Overflow
4-b
4-b
4-b
10-b 10-b
Figure 4-26 Error correction circuit (ECC) (a) Error correctioncircuit block diagram (b) Adder in ECC
(a)
+
4-bit
4-bit
4-bit
10-bit
0 or 1carry
0 or 1
(b)
(first addition)
(second addition)
Carry
(no addition)
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June 3, 1996
version of the carry look ahead algorithm [102] because most of the inputs to the
carry look ahead adder are zeros. The first three LSBs do not require any operation,
the 4th, 5th,and 6th LSB are determined by the MSB from the binary decoded third
quantizer output, and the remaining MSB (7th ~ 10th LSB) are determined by the
results of a carry and MSB of the first addition output as shown in Figure 4-26 (b).
The detail logic is illustrated in Figure 4-27.The 10-bit of the addition circuit output
is feed into the OR gate so that the overflow can be represented as 210-1.
x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 x0
z9 z8 z7 z6 z5 z4 z3 z2 z1 z0
c0c1c2c3c4c5c6c7c8c9cout
P=x⊕yg=xyzi=pi⊕cici+1=gi+pici
c0=0c1=0c2=0c3=0c4=x3x4c5=x5x4x3c6=x6x5x4x3c7=x8x7+[(x8⊕x7)c6] =x8x7+[(x8⊕x7)x6x5x4x3]c8=x9c7 =x9x8x7+[(x8⊕x7)x9x6x5x4x3]c9=x10c8=x10x9c7 =x10x9x8x7+[(x8⊕x7)x10x9x6x5x4x3]cout=x11c9=x11x10x9c7 =x11ax10x9x8x7+[(x8⊕x7)x11x10x9x6x5x4x3]
Figure 4-27 Detail logic of simplified carry-look ahead in ECC
113
June 3, 1996
4.6.2 Output buffer
The output levels of the output buffer are compatible to that of ECL logic
where VOH > -0.8 V and VOL < -1.70 V. The differential output buffer is used to
drive ECL logic levels into a remotely terminated logic analyzer, and does not
produce large data-dependent current glitches on the chip power supplies. The
schematic of the differential output buffer is shown in Figure 4-28
4.7 Layout
The ADC was laid out by Led layout editor from Mentor Graphics. The
layout extraction and DRC check were performed using Checkmate from Mentor
Chip
Vin-Vin+
Vcc
Vout+ Vout-
Figure 4-28 Schematic of differential output buffer
M1 M2
PMOS w=10µNMOS w=4µ
PMOS w=10µNMOS w=4µ
90 Ω
400µ
100 Ω
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June 3, 1996
Graphics. The layout was checked using LVS from Tanner Research. The fully
differential balanced signal is applied to the ADC from the bottom of the chip, and
a single 100 MHz clock is applied from the top of the chip as the floor plan shown
in Figure 4-29. The effect of the digital circuit noise [3][48][49][92] has been one
of the major sources of degradation in performance in the ADC. To avoid the digital
noise coupling, the analog signal is kept away from the digital area. All the noisy
clock buffers which generate 50MHz clock signals and 25MHz clock signals, and
Digital Area
TH
x4
x4A
DD
A
EC
100M CLK
50M/25M CLK
OutputBuffer
OutputBuffer
IN
CLKIN
x2
x4
x2
AD
x4
x4A
DD
A
EC
x2
x4
x2
AD
AD
DA
Figure 4-29 Floor Plan of A/D converter
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June 3, 1996
the output buffers, are located in the top part of the chip. The clock buffers are
surrounded by p+ substrate contacts and the n-well guard ring, and the large p+
substrate contacts are added in-between the digital data output buffer and the core
circuitry. To obtain the symmetry in the layout of 2-channel, the clock signals are
distributed through the middle of the chip where the p+ substrate contacts and the
n-well guard ring also surrounds them. The noise-sensitive analog circuits, such as
the S/H and the gain-of-2 amplifier in the first residue amplifier bank, are laid out
at the bottom of the chip and the digital and less noise sensitive circuits, such as the
third quantizer, are laid at the top of the chip.
Since it is using a parallel architecture, symmetry between the layout of the
two-channels was the next biggest concern. Except for the S/H and the first 4-bit
AD-DA (which is common to both channels), all the other blocks are laid out as
mirror images. For testability, there are the monitoring points at the outputs of the
S/H, the first and second residue amplifier bank, and the reconstruction DAC,
connected to the pad by transmission gates. For low-speed testing (< 5MHz
sampling rate), the monitoring point can be turned on and the analog output can be
observed. However, at the high clock conversion rate, since the capacitance
loadings from pad, the offchip wiring, and the measuring instruments is more than
10pF, the transmission gate is turned off.
The S/H and the first 4-bit AD-DA have been laid out at the bottom of the
other subconverter block. The capacitors of two gain-of-2 amplifiers are placed
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June 3, 1996
close together to reduce an interchannel offset mismatch. The ADC is laid out in 10
x 10 mm2, however, the core area of the chip is 50 mm2, as show in Figure 4-30.
4.7.1 Gain-of-2 amplifier layout
Layout issues in the amplifier in the first residue amplifier bank are fast
Figure 4-30 Chip microphotograph of the ADC
TH
ClockEC
AD
ADDAX4
X2
X4X4
X2
ADDAInput
EC
AD
ADDAX4
X2
X4 X4
X2
CLKin
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June 3, 1996
settling time, settling accuracy, small offset, and decoupling of the digital noise
from the residue signal to obtain better than 1 LSB of 10-bit accuracy. The amplifier
has its own biasing circuit to make wiring complexity lower in the overall layout.
The detailed layout is illustrated in Figure 4-31.
The S/H output signal and the reconstruction DAC output are applied to the
Figure 4-31 Gain-of-2 residue amplifier layout
Input DA output Sampling SW
CMFB
Reset SW
Output
AX
AX
AX
AX
Main AMP
Bias
Analog
pathSignal
SamplingFeedback
Cap.
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June 3, 1996
sampling switches and the amplifying switches (M3, M4 and M1,M2 in Figure 4-
21) located left bottom. The S/H output signal is applied to the bottom plate of the
linear capacitor. The top plate of the sampling capacitor is connected to the input
differential pair of the amplifier. By this capacitor connection, the substrate noise is
decoupled into the amplifier. The linear capacitor is made of poly and N+diffusion,
whose capacitance value is 1.3 fF/µm2. The gain-of-2 amplifier in the first residue
amplifier bank can only tolerate 0.5% gain inaccuracy because the first residue
amplifier bank should have 7-bit gain accuracy. The sampling and feedback
capacitors are laid out closely to each other to get better matching and the dummy
capacitors are added at the top and bottom of the sampling and feedback capacitor
bank to minimize the boundary effect and get better matching. In addition, this
sampling and feedback capacitors are surrounded by the P+ and N- substrate
contacts to reduce clock noise propagated through the surface of the substrate.
All the clock signal are located in the right bottom side of the corner to make
a wide separation between the analog signals and the digital signals as the analog
signals pass through the middle of the amplifier. The layout of the current source
devices, the differential pair devices (M1, M2 and M7, M8 in Figure 4-23), and the
reset switch (M5, M5 in Figure 4-21) use common centroid layout to minimize the
offsets, so that it can also minimize the offset mismatch between the channels. In
addition, the reset switches have been laid out so that the source and drain of the
switch device face the same direction, to minimize the offset from threshold. Ions
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June 3, 1996
are implanted in the silicon surface several degree off from right angle during P and
N ion implantation. Therefore, the threshold is sensitive to the direction. The four
auxiliary amplifiers for gain boosting are placed close to the cascode devices. The
damping capacitor connecting to the output during reset phase is located at the right
upper conner.
4.7.2 4-bit AD-DA
The 4-bit coarse quantizer and the reconstruction DAC can be separated as
analog parts consisting of the first and second preamplifier, resistor ladders for
comparator reference and the reconstruction DAC, the 15 DAC output selection
switches, and the digital part consisting of the latch, master slave F/F and NOR
gates, as shown in Figure 4-32. A common centroid layout is used in the first and
the second preamplifier to minimize systematic offsets. One of the worst offset
sources in the comparator might be the unbalanced coupling from the switches in
the latch circuit. Because of the positive feedback during the regeneration phase in
the latch circuit, the initial condition at the beginning of phase transition to
regeneration determines the output. Therefore, the unbalanced charge injection at
the phase transition will generate the systematic offset on top of the random offset.
The measured mean and standard deviation of comparator threshold for the first
prototype is shown in Figure 4-33. The means of the systematic comparator offset
are about 18 mV which comes from the asymmetry layout. Since the complete
cancellation of the charge injection due to switch clock is impossible, balanced
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June 3, 1996
injection is the solution. Simply say that the preamplifier gain is large enough to
overcome this offset differential pair input in the preamplifier (See 4.3.1)
Figure 4-32 4-bit AD-DA layout
DAC switch
Latch
FFNOREncoder
Preamplifier1st stage
2nd stagePreamplifier Comp. Reference
DAC switch select
DAC out Vin
Encode DoutDigital Analog
Resistor Ladder
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June 3, 1996
The 10-bit linearity of the first reconstruction DAC is essential to obtain 10-
bit resolution in the pipeline ADC. The followings are the rules needed for our
resistor ladder test chip to get 10-bit linearity, as shown in Figure 4-34. The first two
taps at each end are discarded to eliminate edge effects and the width of 80µm or
larger poly-resistor ladder is used to decrease the nonlinearity. In addition, the poly-
metal1 contacts to the DAC selection switch have to be kept out of the main resistor
ladder so as not to interrupt the current flow. The variation of the contact resistance
would not encounter any problems because there is no current flows through the SC
-8 -4 0 4 80.0
20.0
40.0
60.0
80.0
Mean Offset of chips
Std Offset of chips
Comparator Index
Mean & Std (mv)
Figure 4-33 Measured mean and standard deviation of comparatorthreshold offset from 1st quantizer in first version
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June 3, 1996
amplifier when the DAC output settles.
4.8 Simulations
4.8.1 Input referred noise analysis
The input referred noise of ADC is simulated in Figure 4-35. The noise
contributions from the wide-band S/H in both HoldI and HoldingII, gain-of-2
residue amplifier, are dominant than KT/C noise. The total noise referred to the
input of ADC is about 280µV (rms). This analysis was based on the second version
and the schematic of the op amp (resize=1) is shown in Figure A-29.
4.8.2 Performance simulation
The circuit was verified with Hspice from the Meta-Software. The model
used in the simulation was the MOS level 28 from HP. The SPICE netlists were
generated by Powerview from Viewlogic. The input file for the simulation was
prepared with extracted wiring capacitor at each block output. Digital data was
Dummy Dummy
> 80mm
Figure 4-34 Layout of resistor ladder for reconstruction DAC
to selection switch
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June 3, 1996
Sampling
60 µV (rms)
HoldI
165 µV (rms)
Hold II (non-reset)
150 µV (rms)2
from gain of 2 RA
170 µV (rms)2 4
from gain of 4 RA
44 µV (rms)4
Figure 4-35 Input referred Noise in ADC
1.2pF1.2p
30_30
20_30 represents the switch NMOS 20 µm, PMOS=30µm
0.90.9
30_30
resize 2
S/H
S/H
0.9p
30_30
0.9p
75_0
1.2p
15_9 0
resize 1.5
resize 1
300Ω
45_4550_0
1.0p
16_320.6p
1.2p
15_30
0.75p
0.25p0.4p
resize1 represents op amp used in second stage RAs
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June 3, 1996
obtain from the full-chip simulation for 32 points along a sinewave, which shows
the -74 dBc noise floor.
The number of digital output from the simulation determine the extent of the
observed spurious free dynamic range. Let’s assume 2N number of digital data was
obtained from the 1 period of sinusoid input. Since the SNR of the ideal 10-bit ADC
is 62 dB, the magnitude of the noise floor (xn) is represented as
(4.17)
Therefore
(4.18)
Since the Spurious Free Dynamic Range (SFDR)= ,
(4.19)
and the number of point required in FFT is 2N. For example, to resolve the harmonic
whose magnitude is 74 dBc, from eq. (4.19). The
minimum number of points required are 25=32 as shown in Figure 4-36.
2N 1–
xn2⋅ 10
6210------–
=
N10 xn
2log10⋅ 62+
10 2log10⋅----------------------------------------- 1+–=
10– xn2
log10⋅
NS– FDR 62+
3------------------------------- 1+–≈
N74– 62+
3----------------------– 1+≈ 5=
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June 3, 1996
0 dB
Figure 4-36 Noise floor in 2N point FFT of ideal 10-bit ADC
Magnitude
2N-1
Index
-62- (N-1)⋅3 (dB)
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June 3, 1996
Chapter 5
Testing Summary
Three prototypes of the ADC have been fabricated. In the first version, the
measured resolution was only 8-bit with a low conversion rate. The poor resolution
was traced to the 4-bit quantizer not having enough resolution (Figure 4-33).
Furthermore, the slow conversion rate was due to excessive wiring capacitance at
the output of most of the amplifiers. Finally, the effects of self-heating were not
properly accounted for. In the second version, the resolution of the 4-bit quantizer
was increased by first scaling the device sizes to reduce the random offset in the
preamplifier. Second, the inputs to the differential pairs of the preamplifiers were
re-arranged so that the preamplifier closest to the zero-crossing has the largest gain.
The gain in the preamplifier suppresses the random offsets in the latch devices and
the systematic offset due to asymmetric charge injection. In addition, the symmetric
layout reduces the source of systematic offsets in the latch. To obtain the target
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June 3, 1996
conversion speed, the extracted capacitance was used to estimate the loading
capacitance instead of using an estimated capacitance. Also, the design was
centered at 700C instead of room temperature. The is the estimated junction
temperature with an estimated power dissipation of 1.0 W and a package thermal
resistance of 35oC/W. Finally, the preamplifier bandwidth was increased, and gain
was reduced until the input referred random offsets of latch circuit were comparable
to that of the preamplifier circuit.
In the second version, 10-bit resolution was achieved, and the maximum
conversion rate is 50 MHz. The conversion rate was less than expected due to a
seriously underestimated junction capacitance in the FET model. Most of the test
results in this chapter are from the third version of the ADC with some results from
the second version.
5.1 DC test using a monitoring pin
As mentioned in the layout, the monitoring pins are connected to the output
of the S/H, reconstruction DACs, and the residue amplifiers through transmission
gates. By turning on this monitoring transmission gate, the output of points can be
measured using a high impedance probe and will provide very precise information
at low conversion rates, typically less than 5MHz. Because the extra devices adds
an unacceptable amount of capacitive loading to the output of the monitoring point,
all the monitoring points are disconnected from these devices at high conversion
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June 3, 1996
rates.
5.1.1 Resistor DAC test result
The linearity requirement at the first reconstruction DAC in pipeline ADC
should be better than that of the ADC. The various shapes of the resistor DAC as
shown in Figure 5-1 were fabricated to determine the shape of the resistor linearity.
The 60-µm wide straight resistor ladder has the best linearity in four of the
prototypes. In the ADC, the actual resistor linearity has been measured by turning
on monitoring points. The input DC voltage is increased to read each threshold with
DVM readout. Figure 5-2 illustrates the test setup for the reconstruction DAC
linearity test. The resistor ladder used in this test is made of 120µm X 1500µm
straight polysilicon. The worst resistor ladder INL measured from 17 chips is 0.6
LSB of 10-bits, which is linear enough to use as a reconstruction DAC in a 10-bit
pipeline ADC, as shown in Figure 5-3. The 10-bit DAC with 0.3 INL using resistor
ladder was reported by Brigati [4] and Pelgrom [70].
Figure 5-2 DAC linearity testing setup
TH ADDA
ADC chip
DVM
HP 3478A
DAout
129
June 3, 1996
5.1.2 Comparator offset
The comparator offset has been measured using the same setup as used for
measuring the reconstruction DAC output. The input voltage to the ADC is
Figure 5-1 Captured layout of resistor ladder DACs
(a) 40µm wide straight resistor ladder
(b) 60µm wide straight resistor ladder
(c) 40µm wide parallel resistor ladder
(d) 20µm wide folded resistor ladder
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June 3, 1996
increased until the voltage of the reconstruction DAC is equal to the average of the
two adjacent DAC levels. This voltage was measured with a DMV and is defined
as .
(5.1)
At this trigger point, the reconstruction DAC output is very sensitive to the input.
The comparator offset is calculated from the input of ADC by eliminating the S/H
amplifier’s effect. The x-axis in Figure 5-4 shows a comparator index which is
numbered 0 at the middle where , is numbered positive where
and numbered negative where .
The measurement summary1 from the 1st quantizer of the random input offsets of
the 15 comparators illustrates a mean value of about 2.5 mV, with a standard
1. This measurement is performed on second version ADC
0.2 0.4 0.6 0.8
2
4
6
# of chips
INL (LSB of 10 bit)1.0
Total 17 chips
Figure 5-3 Resistor DAC testing result
DACOmean
DACOmean
DACn 1– DACn+
2-------------------------------------------=
where n= -8, -7,........., 6, and 7
Vref+
Vref–
=
Vref+
Vref–> Vref
+Vref
–<
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June 3, 1996
deviation of 9 mV for every comparator in the array under the± 0.75 V full scale
reference voltage. At the third version of the ADC, the same circuit has been used
for the comparator. The 6σ of each comparator offset in 4-bit quantizers satisfies
requirements on an accuracy of± 1.0 V full scale. This means that the offsets within
the quantizers in all the ADCs will be less than± 62.5 mV, which is±0.5LSB at 4-
-8.0 -4.0 0.0 4.0 8.0-10.0
-5.0
0.0
5.0
10.0
15.0
20.0
+0.5 VFS
-0.5 VFS+0.5 Vin
-0.5 Vin
01
23
45
Comparator Index
Offset Mean
Comparator Index
Mean & Std (mv)
1 LSB of 4-bit = 47 mV
Offset Std
Figure 5-4 Measured mean and standard deviation of comparator thresholdoffset from 1st quantizer
Full scale =± 0.75V
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June 3, 1996
bit of ± 1.0 V input full scale.
5.2 Testing Setup
The dynamic testing setup for A/D converter chips is illustrated in Figure
5-5. Two very low phase noise frequency synthesizers are locked to each other by
a 10 MHz reference. One synthesizer is used to generate balanced fully differential
analog inputs, and the other is used to generate a low jitter clock pulse. The first
synthesizer output is connect to low pass filter by a SMA cable and is low pass
filtered by a 5th order Chebyshev filter1 to suppress 2nd and higher order harmonics
1. The model numbers are LC5-(passband frequency)-50-613A from TTE, and passbandfrequencies are 100K, 200K, 500K, 1M, 2M,..., 50M, and 100 MHz.
HP 8643A
Figure 5-5 A/D converter test setup
DUT
HP 8643A
Synthesized S.G.
Synthesized S.G.
HP 8130A
Pulse Gen.
Colby PG 1000A
Pulse Gen.
LPF power splitter
HP 1663A
Logic Analyzer
Analog Input
Clock2X10
HP 6625A
Power Supply
Vdd, reference bias
10 M
Hz
refe
renc
e
To PC
133
June 3, 1996
to less than -80 dBc. The following 1800 phase splitter can generate the fully
differential outputs from the output of the low pass filter. These outputs directly
drive the input pins of the ADC. The input matching is performed by 50Ω
termination resistor between input pad and the GND pad inside the chip. The 50Ω
termination resistor is made of polysilicon (25Ω/). The pads have no ESD
protection. The common mode of the input differential signal is set to GND to
provide the clean input signal. Therefore, the prototype ADC is biased with +2.2 V
and -2.8 V instead of 5 and 0 V. The other synthesizer output is fed to a very low
phase jitter pulse generator (Colby PG 1000A) to generate a short rise and fall time
and a 50% duty cycle to drive a clock for the ADC. The synthesizer output is also
fed to a general purpose clock pulse generator to add a proper delay between a clock
input to the ADC and a digital logic analyzer, so that the digital logic analyzer1 can
be strobed to collect converted data. Furthermore, the Colby pulse generator can
provide variable duty cycle. To decouple the digital noise from the analog signal
and to make clean Vdd, Vss, and GND, an 8 layer PCB board has been used. In
addition, the isolation transformer supplies clean power to the synthesizer for
analog input to the power supply providing an analog Vdd and Vss, and
programmable power supply for reference generation. The 20 digital outputs at 50
MHz from the ADC are not multiplexed, so the logic analyzer comfortably collects
and stores the converted digital data into its memory. The stored data are down
1. HP 1663A logic analyzer: 2 channel, 4K/channel memory depth and 100 MHz stateanalysis capability
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June 3, 1996
loaded using GPIB to a PC for post processing. GPIB is controlled by the PC
program written in Visual Basic. Matlab in PC analyzed the data up to 1K, and
Matlab in a SUN workstation analyzed the 4K data.
The detailed description of an 8 layer PCB board now follows. The analog
input signal lines are drawn on the top of the first layer and the digital output lines
are drawn at the bottom of the 1st and 8th layer to minimized the digital signal
coupling into the analog input signal line. The types of each layer are summarized
in Table 5.1. The components and the signal line layout is illustrated in Figure 5-6.
The signal-to-distortion and noise ratio (SNDR), the total harmonic
distortion (THD), and the spurious free dynamic range (SFDR) have been measured
by performing the Fast Fourier Transform (FFT) on digitized waveforms generated
from the ADC’s digital output [23]. In addition, the histogram test was used to
obtain the integral nonlinearity (INL) and the differential nonlinearity (DNL) for
Table 5.1 Signals in different layers
Layer number Signal type
1 Signals
2 GND
3 Analog VDD
4 Digital VDD
5 Analog VSS
6 Digital VSS
7 GND
8 Signals
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June 3, 1996
Figure 5-6 PCB board (a) component location (b) signal line layout at top plate
(a)
Differential input
(b)
Clock input Digital outputsDigital outputs
Power (Vdd, GND, Vss)
Reference Voltage Monitor SW
Leadless Ferrite CoreDecoupling capacitor
Monitoring point
136
June 3, 1996
the different input and sampling frequencies [13].
5.3 DC performance
5.3.1 Input referred interchannel offset
Figure 5-7 illustrates the histogram of the offset mismatch among the
channels extracted from the digitized data, when a 421 KHz input is sampled at a 4
MHz clock. The data are generated from the each channel in sequence such as
channel 1-a, channel 2-a, channel 1-b, channel 2-b, channel 1-a, channel 2-a,….
After data are downloaded, and statistics are calculated on the interleaved set of
data.
The spreads of offset mismatches between channel 1a-2a and 1a-2b are
larger than that between 1a-1b and 2a-2b. Because the offset mismatch from the
gain-of-4 amplifier is decreased by gain of the gain-of-2 amplifier, the offset
mismatch between the gain-of-2 amplifier is the dominant factor for the tone in the
spectrum rather than gain-of-4 offsets.
Figure 5-8 illustrates histograms of the amplitude of fs/2 tone in (a) and the
histogram of sum of combined fs/2 and fs/4 tone in (b). These fs/2 and fs/4 tones
are extracted from the FFT spectrum with measured digitized data at the± 0.5V
input full scale. The measurement is performed on the first version ADC allowing
only ± 0.5V input full scale due to the comparator architecture (Figure 4-13 (a)).
With ±1.0 V input full scale, the fs/2 and fs/4 tones will be decreased by 6 dB. As
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June 3, 1996
-2.0 -1.0 0.0 1.0 2.00.0
4.0
8.0
12.0
-2.0 -1.0 0.0 1.0 2.00.0
4.0
8.0
12.0
-2.0 -1.0 0.0 1.0 2.00.0
4.0
8.0
12.0
Channel 1a-1b
(mV)
(mV)
(mV)
Channel 1a-2a
Channel 1a-2b
(mV)
Measured from ADC Digital output
-2.0 -1.0 0.0 1.0 2.00.0
4.0
8.0
12.0
Channel 2a-2b
24
4
24
4
TH
DA
chan. 1a
chan. 2a
chan. 1b
chan. 2b
fsm=4 MHz fin=420KHz
Figure 5-7 Histogram of measured input referred inter-channel offsetmismatch
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June 3, 1996
Figure 5-8 (a) Histogram of fs/2 tone(b) histogram of RMS sum of fs/2 and fs/4 tonereferred to± 1 V, measured in ± 0.5 V input full scale
-85.0 -75.0 -65.0 -55.0fs/2 Tone (dBc)
0
2
4
6
8
Num
ber
of c
hips
-85.0 -75.0 -65.0 -55.0RMS sum of fs/2 and fs/4 tone (dBc)
0
2
4
6
8
Num
ber
of c
hips
(a)
(b)
139
June 3, 1996
shown in Figure 5-7 and Figure 5-8, fs/2 is one of the major sources of lower the
signal-to-distortion ration (SDR), and this fs/2 will be suppressed later to - 65 dBc
by an offset cancelling circuit. The tones at fs/2 are consistent with measured
offsets.
5.3.2 Reconstructed spectrum at low input frequency
The fine details of the output spectrum are best understood from digitizing
a low input frequency (421 KHz) at a modest sampling rate (4 MHz) as shown in
Figure 5-9. This reconstructed spectrum results from 4K point FFT. The 4K points
0.0 0.5 1.0 1.5 2.0 2.5 3.0Frequency Bin Number (x10 3)
-100.0
-75.0
-50.0
-25.0
0.0R
elat
ive
Am
plitu
de (
dBc)
Figure 5-9 Reconstructed spectrum from measurement at500 KHz input frequency and 4 MHz conversionrate
2nd4th
fs/2
aliased 3 rd9th 3rd
SNDR = 59.5dB4K point FFT
fs/4
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June 3, 1996
are the maximum memory depth of the logic analyzer we have. The SNDR of the
ADC at this frequency is 59.5 dB and the THD is -69 dB. As expected, the tone
appears at half the conversion rate (fs/2) due to offset mismatches between the two
residue amplifier channels following the input sample-and-hold (S/H), and the tone
at 1/4th of the conversion rate (fs/4) due to offset mismatches among the four
gain-of-4 amplifiers. In general, the fs/2 tone can be as large as 55 dBc from the
previous test result, but in this case the fs/2 tone is negligible. Harmonics of the
input signal are below -74 dBc.
5.4 Dynamic Performance
The SNDR measured while varying the conversion rate at low input
frequency (500 KHz) is illustrated in Figure 5-10 (a). The SNDR of 59.5 dB is
obtained at the 4 MHz conversion rate. This test result shows that the SNDR at the
low input frequency is above 9-effective bits up to a maximum conversion rate of
95MHz. The total harmonic distortion (THD) is calculated by power summation
from the second to the 20th harmonic. The THD and spurious free dynamic range
(SFDR) is illustrated in Figure 5-10 (b). Normally, the SFDR is determined by fs/2
tone. However, in this particular chip, the fs/2 tone and fs/4 tone are much lower
than -70 dBc, and the offset calibration designed to suppress fs/2 below -65 dBc was
not necessary. The largest distortion is the 3rd harmonic in this chip and the
magnitude of the 3rd harmonic is illustrated at SFDR plot in Figure 5-10 (b).
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June 3, 1996
Figure 5-10 (a) Measured signal-to-distortion ratio (b)measuredtotal harmonic distortion (THD) and spurious freedynamic range (SFDR) where input signalfrequency is fixed 500 KHz
1.0 10.0 100.0Sampling Frequency (MHz)
50.0
52.0
54.0
56.0
58.0
60.0
SN
DR
(dB
) effective 9-bit
1.0 10.0 100.0Sampling Frequency (MHz)
-80.0
-75.0
-70.0
-65.0
-60.0
TH
D (
dBc)
(a)
(b)
80.0
75.0
70.0
65.0
60.0
SF
DR
(dB
c)THD
SFDR
142
June 3, 1996
The SNDR at 4MHz, 50MHz, and 95MHz conversion rates with various
input frequencies are plotted in Figure 5-11. The SNDR of a 95 MHz conversion
rate is reduced by 3 dB below that of 4 MHz conversion rate at low input frequency.
The SNDR at a 95 MHz sampling rate is better than effective 8-bits up to a Nyquist
input frequency.
One method to test the performance of the sampling circuit is by
subsampling. An input signal whose frequency is higher than a Nyquist is applied
to the ADC while it is converting samples at low or moderate frequency. Because
ADC is operated in a low sampling rate, all components settle completely, except
Figure 5-11 Measured signal-to-distortion and noise ratio at 4 MHz, 50MHz and 95MHz conversion rate
0.1 1.0 10.0 100.0Input Frequency (MHz)
45.0
50.0
55.0
60.0S
ND
R (
dB)
4 MHz
50 MHz
95 MHz
Measured with synthesizer
applied to clock input
at fs=4M Hz & fin = 50MHz
143
June 3, 1996
possibly the sampling circuit. Therefore, the distortions in converted data are a
result from the sampling circuit. Timing jitter in the sampling point degrades the
performance of ADC. The total distortion (Ep) [3] due to the jitter is represented as
follows;
(5.2)
whereA is amplitude of input signal andω is input frequency, and στ is a phase
noise. In high frequency input signal, phase noise is one of the major source of
distortion.
At a 4 MHz conversion rate, another measurement without the pulse
generator for chip clock input (Figure 5-5) result in SNDR of 55.4 dB at 50MHz
input frequency and 4 MHz sampling frequency which is more than 4 dB better than
the one with a pulse generator for chip clock input. At a 4 MHz sampling rate with
50 MHz input frequency, all the components settle, except the sampling capacitor
which might introduce a third harmonic due to ON resistance variation of the
sampling switch. Therefore, after accounting for the harmonic distortion due to the
sampling switch, we can extract the additive phase noise from the pulse generator
by the SNDR difference of this two experiment. The SNDR plot of the 4 MHz
conversion rate with the pulse generator can be reproduced by power sum of the
following factors: the measured noise and distortion power at low input and low
sampling frequency, the measured 3rd harmonic, and the 8 ps of phase noise at the
Ep
A2ω2σt
2
2-------------------=
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June 3, 1996
chip clock input. The projected SNDRwithout this phase noise is illustrated in
Figure 5-12. The major improvement in SNDR is at high input frequencies,
especially at 50MHz, because the noise power due to phase jitter increases with
input frequency as shown in eq. (3.37).
The reconstructed spectrum from 4 K point FFT of 2 MHz input frequency
at 95.2 MHz conversion rate is illustrated at Figure 5-12. All harmonics are still
lower than -60 dBc, and the fs/2 tone due to the interchannel offset mismatch
remains at a low level.
Plots of DNL and INL calculated from the histogram technique [13] at a 2
MHz input frequency and a 90 MHz conversion rate are shown in Figure 5-14 and
0.1 1.0 10.0 100.0Input Frequency (MHz)
45.0
50.0
55.0
60.0S
ND
R (
dB)
95 MHz
4 MHz
Figure 5-12 Projected SNDR at 95 MHZ conversion rate
SNDR w/pulse gen.
SNDR w/opulse gen.
ProjectedSNDR
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June 3, 1996
Figure 5-15. The DNL is between + 0.6 LSB and -0.33 LSB and the INL is worse
than 1 LSB in some codes higher than 900.
5.5 Power dissipation and test summary
Figure 5-16 illustrates the power dissipation vs. sampling frequency. The
analog circuit dissipates 850 mW and the digital circuit dissipates 250 mW at 95
MHz. The average power dissipation of the chip at 95 MHz is about 1.1 W from the
single 5 V power supply, excluding the power dissipation from the off chip logic
driver. The breakdown of the power dissipation of each block is illustrated in the
fs/4
0.0 10.0 20.0 30.0 40.0 50.0
Frequency (MHz)
-100.0
-75.0
-50.0
-25.0
0.0R
elat
ive
Am
plitu
de (
dBc)
3rd
2nd
9th
7th
fs/4-fin
15th
19th 22th fs/2
fs/4+fin
Figure 5-13 Reconstructed spectrum from measurement at2 MHz input frequency and 95.2 MHz conversion rate
SNDR = 55.6dB4K point FFT
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June 3, 1996
pie-chart in Figure 5-17. The largest portion of power dissipation is the residue
amplifiers. This is the price of converting 3-bits/stage over 1-bit/stage.
The tested A/D converter characteristics are summarized in Table 5.2.
0 256 512 768 1024Digital Code
-1.0
-0.5
0.0
0.5
1.0D
NL(
LSB
)
Figure 5-14 Differential nonlinearity from 2 MHz input frequencyat 90 MHz conversion rate
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June 3, 1996
0 256 512 768 1024Digital Code
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0D
NL(
LSB
)
Figure 5-15 Integral nonlinearity from 2 MHz input frequency at90 MHz conversion rate
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June 3, 1996
0 20 40 60 80 100Sampling Frequency (MHz)
800
900
1000
1100
1200P
ower
dis
sipa
tion
(mW
)
Figure 5-16 Power dissipation vs. sampling frequency
TH
Residueamp
AD-DA
Digital Total power dissipation
≈1.1W @ 95MS/s
Figure 5-17 Power dissipation at 95 MHz sampling rate
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June 3, 1996
a. After on-chip offset cancellation
Table 5.2 Summary of ADC characteristic
Parameter
Resolution 10 bit
Max Sampling Rate 95 MHz
Input Range ± 1.0 V
Signal/(Noise+Distortion)
sampling freq 50 MHz 95 MHz
at fin= 0.5 MHz 57.7 dB 56.5 dB
at fin= 20 MHz 56.7 dB 54.3 dB
Thermal Noise 0.4 mV(rms)
fs/2 tone < 65 dBca
Power supply + 5V
Power Dissipation 1.1 W
Active Area 50 mm 2
Technology 1.0µm CMOS (N-Well) with linearCap.
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June 3, 1996
Chapter 6
Conclusions
6.1 Summary of research
The research successfully demonstrated the 1µm CMOS 10-bit ADC with
the maximum sampling rate of up to 95 MHz. It attains 59.5 dB SNDR at a low
conversion rate, and more than 50 dB SNDR at a 50MHz input frequency with 95
MHz conversion rate. By using a simple offset calibration, the fs/2 tone can be
suppressed below -65 dBc. The simulated bit-error rate is less than 10-10. The ADC
is implemented in fully differential circuits using a 2-channel 3-stage pipeline
architecture. Each stage converts 4-bits, and 1-bit in the first and second stages is
used for digital error correction. Because all the digital clock signals are generated
from the on-chip clock buffer, the circuit requires only a single external full speed
clock signal. The active chip area is 50 mm2 and the ADC dissipates 1.2 W from a
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June 3, 1996
single 5 V power supply.
Several architectural and circuits which enabled the ADC are described in
this report. The techniques used to obtain the performance are listed below.
• Two channels pipelined ADC are utilized to increase the thoughput
from the single pipeline ADC.
• A single sample-and-hold amplifier operating at full speed provides
held outputs to the ADC. Therefore, the nonuniform sampling of the
analog input into the two channels is not an issue.
• Two channels share a single reconstruction resistor DAC, which meets
stringent requirement of 10-bit accuracy and matching. Therefore, the
gain mismatch due to IR drop in the metal line connecting to the ends of
the resistor ladder is not an issue.
• The 4-bit/stage conversion (effective 3-bit/stage) relaxes the gain
requirement of the residue amplifier and eliminates the effects of the gain
mismatch between the channels.
• The residue signal is amplified by one gain-of-2 amplifier operating at
half of the clock speed and the amplified residue signal is interleaved to
the two gain-of-4 amplifiers at 1/4th of the full clock speed. This
breakdown is based on equal gain-bandwidth products to increase
throughput rate.
• A simple offset cancellation circuit is inserted at the last residue
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June 3, 1996
amplifier.
• A single full speed external clock is required and all the clocks, i.e.
complementary clock with delay for one 100 MHz, one 50 MHz, and two
25 MHz, are generated on chip for proper synchronization and testability.
A non-resetting sample-and-hold amplifier has been optimized so that it can operate
at full speed. The rationale to design the non-resetting functions are:
• The conversion time at the front-end of the ADC is determined by the
sum of the S/H delay, coarse quantizer delay, and delay of the latch. This
delay has been reduced by utilizing a double-sampled pipeline scheme
using two cascaded resetting S/Hs.
• The non-resetting S/H output provides a full clock period for the
following residue amplifier to perform autozero.
The required linearity and settling speed in the reconstruction resistor ladder DAC
are achieved by the following techniques;
• Dummy cells at both ends of the resistor ladder improve a resistor DAC
linearity to more than 10-bit.
• Optimizing a selection switch size and a resistor ladder size can obtain
the required time constant for DAC settling.
The 4-bit quantizer consists of a preamplifier, a latch, and a master slave F/F. It has
been laid out for the signal to flow in one direction using two resistor ladders. The
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June 3, 1996
comparator circuit has been selected and designed with the following criteria:
• The 2-stage preamplifier provides a wide dynamic range with proper
gain to reduce an offset from the latch circuit and prevents a kickback
from the latch to the input reference resistor ladder and reconstruction
resistor DAC.
• The differential inputs and references have been arranged so that they
can maximize the gm of differential pairs detecting the closest threshold
to input.
• The feed forward latch architecture and boosting capacitors in the latch
have been used to maximize the conversion speed.
• Since the second and third quantizers operate at half speed, the
interpolation scheme (which is a simple elimination of half of the first
preamplifier) was utilized to reduce input capacitance. And further
reduction of input capacitance can be done at the second preamplifier if
settling time allows.
6.2 Performance Analysis
There are some limiting factors that do not allow the prototype ADC to
reach or exceed a 100 MHz conversion rate.
The first reason is that the S/H requires a longer settling time when the
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June 3, 1996
capacitive loading from the extracted layout is taken into account, compared to
earlier simulations with an estimated load. Therefore, at high conversion rate, the
noise floor increases due to the first quantizer error. The conversion rate can be
improved by re-optimizing the clock driver circuitry, or by re-sizing the hold non-
resetting S/H.
Another performance limiting factor is residue amplifier gain errors.
Another is the DC-type gain error at the low conversion rate where all the blocks in
the ADC fully settle. When a single reference voltage is applied to the first, second
and third reference ladders, and the metal line connecting the ladder end points off-
chip been carefully sized to avoid any significant IR drops, only a 57 dB of SNDR
is achieved. The external reference voltage must be tapered down by 1% per stage
to obtain the best SNDR at a low sampling rate. It also must be tapered down by an
additional 1% to compensate for the incomplete settling in the first residue amplifier
bank at 95MHz conversion rate.
The active area may be reduced by more aggressively scaling down some of
the later quantizers, or better yet, by using a more efficient implementation such as
folding architecture [20][21][62][63][73] in the two channels following the full
speed front-end. The folding architecture demonstrates 8-bit resolution up to 80
MHz conversion rate[63]. However, the primary goal of this work was to
demonstrate the viability of an architecture, and therefore the high performance, but
large, front-end blocks are re-used in the subsequent stages.
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June 3, 1996
Appendix A
Comparators
A.1 Bipolar comparator
One common method of implementing the comparator latch is to make a
dual connection of two transistors by cross connecting a base of one transistor to the
collector of the other, as illustrated in Figure A-1. The first stage, consisting of Q1,
Q2, and Q5, amplifies the input signal to node Voutp and Voutn with a gain of
gmQ1(Q2)x RL, when the latch signal goes high (amplifying period). When the latch
signal goes low (regeneration period), the current flowing through Q5 switches to
Q6, and this current is steered to Q3 and Q4 where positive feedback results in a
latch function disabling the input signal from effecting the differential output
voltage. An advantage of this current steering technique is that no additional bias
current is necessary to implement the latch function. However, the input transistor
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June 3, 1996
pair (Q1 and Q2) is cut off in the regeneration period and is turned on in the
amplifying period, which causes a large base charging current flow. This can result
in the “kickback” of clock noise to the input and reference, which can corrupt the
conversion process accuracy.
The comparator with “high-level” clocking (as shown in Figure A-2) can
reduce a kickback substantially by cascoding the clock switches such as Q3, Q4,
Q5, and Q6 [73]. Because the input differential pairs are on all the time, there is no
instantaneous base charge current. In addition, the input capacitance is reduced
because there is no miller capacitance due to the cascode of the clock switch.
However, this comparator requires a greater number of transistors.
Vinp Vinn
Vb
Latch Latch
Voutp
Voutn
Figure A-1 Basic bipolar comparator circuit
Q1 Q2 Q3 Q4
Q5 Q6
Q7
RL RL
RE
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June 3, 1996
A.2 CMOS comparators
The comparators consist of a preamplifier and a latch stage. Several types of
comparators have been reviewed and the schematic of comparators with static
latches are illustrated in Figure A-3, A-4, A-5, A-6, and A-7, and the schematic of
comparators with dynamic latches in Figure A-8, A-9, and A-10. In general, the
dynamic latch has a larger amount of kickback than the static latch to preceding
circuits such as preamplifier output and input to the comparator or the reference
ladder in worse case. The dynamic latch, however, dissipates less power than the
Vinp Vinn
Vb
Latch
Latch
VoutpVoutn
Figure A-2 Bipolar comparator with high-level clocking
Q1 Q2
Q3 Q4 Q5 Q6
Q7 Q8
Q9
RL RL
RE
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June 3, 1996
static latch, even though the difference is negligible at high clock rates, because the
dynamic latch does not dissipate any power during the resetting period.
The schematic of the comparator reported by Nauta is illustrated in Figure
A-3. With a low latch signal, the comparator is in its pre-amplification period (reset
period). The gain of the comparator at this period is determined by the
transconductance of M1,2 and resistors RL. At the rising edge of the latch signal,
the cross-coupled transistors M7 and M8 make a positive feedback latch. Since M7
and M8 are at the its threshold during pre-amplification period, the latch start to
regenerate the output right after the latch signal goes high, compared with other
latch whose output is reset to either Vdd or ground. The regeneration time constant
is decided only by the transconductance of M7,8 and output capacitance. The major
Vinp Vinn
Vb
Latch
Vdd
Latch
Figure A-3 Comparator schematic from Nauta, 1996 [63]
M3
M1 M2
M4M5
M7 M8
M9
M6
RLRL
Latch
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June 3, 1996
advantages of the comparator are compactness (preamplifier & latch combined) and
low kickback. M1 and M2 are always on, and kickback from output resetting is
reduced by M3 and M4 by fixing the gate nodes to either low or high latch signal.
However, the comparator cannot deliver standard CMOS logic levels and it requires
the following full swing latch, which makes it improper to be used as a inter-stage
sub-quantizer in a pipeline architecture due to timing. Another disadvantage is slow
resetting time, compared to a latch with output reset to either Vdd or ground.
The schematic of the comparator reported by Fiedler is illustrated in Figure
A-4. When the latch signal is high, M10 and M11 discharge the latch output nodes.
When the latch signal goes low, the drain current difference between M8 and M9
appears as the output voltage difference. The cross-connected M12 and M13 form
Vinp Vinn
Vb
Latch
Vdd
Voutn Voutp
Figure A-4 Comparator schematic from Fiedler, 1981 [16]
M3
M1 M2
M4
M6 M7
M5
M8M9
M12M10 M11M13
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June 3, 1996
a positive feedback and results in a latch. There are two disadvantages in this
scheme. One is that there is some delay because M11 and M12 has to wait until
either side of the output voltage becomes larger than Vt. The other is that there is a
static current in the comparators which are close to the threshold after the output is
fully developed. Assume the potential of Voutp node is higher than that of Voutn
node. After the short period, M11 turns off and the potential of Voutp becomes Vdd,
however, since M12 is in a linear region, the static current from M8 will drain
during the regeneration period.
Figure A-5 illustrates the schematic of the comparator designed by Song.
When the latch signal is high (resetting period), the diode-connected transistors
M10 and M11 are fully turned on to reset the output. In addition, it works as a gain
Vinp Vinn
Vb Vdd Latch
Vdd
Voutn Voutp
Figure A-5 Comparator schematic from Song, 90 [88]
M3
M1 M2
M4
M6
M7
M5
M8 M9 M11M10
M13M12
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June 3, 1996
amplifier with the gain approximately
(A.1)
where gm of M8 and M9 acts as the negative transconductance. However, this gain
has to be optimized so that the latch output can be reset at the given clock rate. Once
the latch signal goes low, the diode-connected transistors M10 and M11 are turned
off and the amplifier becomes a positive feedback latch due to the cross-coupled
transistors M8 and M9. The disadvantage of this comparator is that it dissipates
power at the latch circuits where the input of the comparator is close to the threshold
after the latch output is fully developed. The output of the latch seems to reach its
full-scale output faster than that of the previous latch [16] because the cross-
coupled transistors, M8 and M9, are in an active region at the moment when the
latch signal goes off and starts the regeneration with initial amplified output voltage
from the end of the resetting period.
Figure A-6 illustrates the schematic of the comparator designed by Lewis
[42]. The circuit consists of a folded-cascode amplifier (M1-M7) where the load has
been replaced by a current-triggered latch (M8-M10). When the latch signal is high
(resetting period), M10 shorts both the latch outputs. In addition, the on-resistance,
R, of M10 can give an extra gain (Areset) at the latch output, approximately
, (A.2)
Areset
gm1 2,gm9 10, gm10 11,–---------------------------------------=
Areset
gm1 2, R⋅2 gm9 8, R⋅–------------------------------=
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June 3, 1996
which speed up the regeneration process. However, the on-resistance, R, should be
chosen such that it can meet the following,
(A.3)
in all process corner and should be small enough to reset the output at the clock rate.
Since all transistors are in active region, the latch can start regenerating right after
the latch signal goes low. The one disadvantage of this scheme is the large kickback.
Either node A or B has to jump up to Vdd in every clock cycle since the latch output
does the full swing. Because of this, there are substantial amounts of kickback into
the inputs through the gate-drain capacitor of M1 and M2 (Cgd1, Cgd2). To reduce
kickback, the clamping diode has been inserted at the output nodes [62]. The other
Vinp Vinn
Vb
Latch
Vdd
Voutn Voutp
Vb1
Vb2
Figure A-6 Comparator Schematic from Lewis, 1992 [42]
M3
M1 M2
M4
M6 M7
M5
M8 M9
M10
Cgd1 Cgd2
A B
gm8 9, R 2<
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June 3, 1996
disadvantage is that the static power is dissipated after the regeneration is
completed, similar to the previous CMOS comparator in Figure A-4 and A-5.
Figure A-7 illustrates the schematic of the comparator designed by Robert.
When the latch signal is low (resetting period), the amplified input signal is stored
at node A and B (gate of M8, M9) and M12 shorts both Voutp and Voutn. The extra
gain can be obtain by sizing M12 as shown in eq. (A.2). When the latch signal goes
high, the cross-coupled transistors M10 and M11 make a positive feedback latch. In
addition, the positive feedback capacitors, C1 and C2, boost up the regeneration
speed by switching M8 and M9 from an input dependant current source during
resetting period to a cross-coupled latch during the regeneration period. Because of
C1 and C2, the M8~ M11 work like a cross-coupled inverter so that the latch does
Figure A-7 Comparator schematic from Robert, 87 [75]
Vinp Vinn
Vb
Vdd
LatchVoutn Voutp
Latch
M3
M1
M4
M6
M7
M5
M8
M9
M10 M11
M2 M12C1 C2Latch
M13
A
B
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June 3, 1996
not dissipate the static power once it completes the regeneration period. However,
there is a large amount of kickback through the positive feedback capacitors, C1 and
C2. The switches (M6, M7, M13) have been added to isolate the preamplifier from
the latch. Therefore, the relatively large chip area is required due to the positive
feedback capacitors (C1, C2), isolation switches (M7, M8, M13), and
complementary latch signals.
Figure A-8 illustrates the schematic of the comparator modified from the
comparator designed by Yukawa. The NMOS and PMOS transistors have been
swapped for the various performance comparisons. The dynamic latch consists of
discharge transistors (M6, M7), a PMOS flip-flop (M8, M9) with PMOS transfer
gates (M10, M11) for strobing, NMOS discharging transistors (M12, M13), and
Figure A-8 Comparator schematic modified from Yukawa,1985 [108]
Vinp Vinn
Vb
Latch
Vdd
Voutp Voutn
M3
M1
M4M6 M7
M5
M8 M9
M10
M2
M11
M14M12 M15 M13
A B
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June 3, 1996
NMOS flip-flop (M14, M15). When the latch signal is high (resetting period), the
node A and B voltage go to Vdd and the output nodes are discharged to GND.
Therefore, no static currents are flowing though these transistors (M6~M15). Once
the latch signal goes high, the cross-coupled transistors M8, M9 and M14, M15 start
regenerating the output. Because the node A and B have to discharge to Vdd-Vt to
activate the M8 and M9 and the node Voutp and Voutn have charge up to Vt to
activate the M14 and M15, there will be a small delay between the latch signal and
the time that the four cross-coupled transistors start to develop the latch output.
However, both transconductance (gm) of NMOS and PMOS in the cross-coupled
four transistors are added so that the regeneration time constant is fairly short.
During the regeneration period, there is a static current in the latch where the input
is close to the threshold, but there is no static current where the input difference is
large so that one of the input differential pair is turned off.
Figure A-9 illustrates the schematic of the comparator designed by Sutarja.
When the latch signal is low (resetting period), M6 and M7 turn off so that no static
current flows through the latch and the bias voltage Vb and Vb1 are set so that
PMOS M4 and M5 are in the linear region. At the end of resetting period, the
voltage of node D becomes Vt less than that of node A and B. Therefore, the NMOS
M9 and M10 immediately go into the active region and start regenerating the latch
outputs right after the latch signal goes high. The disadvantages of this scheme are
that the latch dissipates a large amount of power after the latch output is fully
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June 3, 1996
developed, and the fully developed latch outputs do not swing rail-to-rail so that the
inverter buffers are required to obtain a rail-to-rail swing. In addition, since the
output of the latch is connected to the drain of the input differential pair of the
comparator, there is a large kickback.
Figure A-10 illustrates the schematic of the dynamic latch designed by
Kobayashi. The dynamic latch consists of precharge transistors M12 and M13,
cross-coupled inverter M6~M9, differential pair M10 and M11, and switch M14
which prevent the static current flow at the resetting period. When the latch signal
is low (resetting period), the A and B node voltages are Vdd-Vt and the C node
voltage is Vt below the latch input common mode voltage. Therefore, once the latch
signal goes high, the NMOS transistors M7, M9, M10, and M11 immediately go
Vinp Vinn
Vb
Latch
Vdd
Voutn
Voutp
Latch
Figure A-9 Comparator Schematic from Sutarja, 1988 [94]
M3
M1
M4
M6
M7
M5
M8
M9
M10
M11M2
Vb1
Reset
A B
C
D
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June 3, 1996
into the active region. Because each transistor in one of the cross-coupled inverters
turns off, there is no static power dissipation from the latch once the latch outputs
are fully developed.
The summary of the comparator schematics is tabulated in Table A.1 [38].
Vinp Vinn
Vb
Vdd
Latch
VoutnVoutp
Figure A-10 Comparator schematic from Kobayashi, 1993 [35]
M3
M1
M4
M7
M6
M5
M2
M9
M8
A B
C
M10 M11
M12 M13
M14
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June 3, 1996
a. This results may not be fully optimized from the author’s design point.b. The latch is modified.
Table A.1 Summary of comparator performancea
Latch type Speed Kickback
Nauta static fair excellent
Fiedler [16] static fair excellent
Song [88] static good good
Lewis [42] static fair poor
Yukawab [108] dynamic fair good
Sutarja [94] dynamic fair poor
Robert [75] static excellent good
Kobayashi [35] dynamic excellent good
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June 3, 1996
Appendix B
Glossary
ADC Analog-to-digital converter
BER Bit error rate
Bi-CMOS Bipolar and CMOS combined (technology)
CMOS Complementary Metal Oxide Silicon (technology)
Cox Oxide capacitance
DAC Digital-to-analog converter
DNL Differential non-linearity
DUT Device under test
FFT Fast Fourier transform
ECL Emitter-coupled logic
HDTV High definition television
INL Integral non-linearity
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MOS Metal-oxide semiconductor
MOSFET Metal-oxide semiconductor field effect transistor
NTSC National Television systems committee
RA Residue amplifier
S/H Sample-and-hold
SNR Signal-to-noise ratio
SFDR Spurious-free dynamic range
SNDR Signal-to-noise-plus-distortion
THD Total harmonic distortion
Vt Threshold voltage
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Appendix C
Distortion in RC sampling circuit
The passive sampling with MOSFET and driving capacitor is modeled as
RC network (Figure A-11). The differential equation for the RC network is
1
1 ωτ( )2
+
------------------------------
Figure A-11 Steady state response of RC network
Vo(t)Vi(t)
Vi(t)
t
Amp.
Vo(t)
1
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represented as follows,
(A.4)
If input signalVi(t) is
(A.5)
then
, (A.6)
where
. (A.7)
Therefore, the steady state output,Vos(t), is represented as
(1.8)
which is pure sinewave.
Now, let find out the magnitude of error (∆V) between the sample-and-hold output,
VSHo, and the steady state output as shown in Figure A-12. Because,
(A.9)
whereε is the error between S/H output and the steady state output (Vos) at the
RCtd
dVo t( ) Vo t( )+ Vi t( )=
Vi t( ) ωtcos=
Vo t( ) Aet τ⁄– ωt φ–( )cos
1 ωτ( ) 2+
-------------------------------+=
RC τ=
φ ωτ( )atan=
A initial value=
Vos t( ) ωt φ–( )cos
1 ωτ( ) 2+
-------------------------------=
VSHo t0( ) Vos= t0T2---–
ε+
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June 3, 1996
sampling time, which is negligible to the amplitude ofVos with reasonableτ. The
distortions added to the steady state output are dependent upon the difference
between the sample-and-hold output,VSHo, and the steady state output,∆V,
(A.10)
ε
-T/2 T/2 3T/2
VSHo(t)
Vi(t)
Vos t( ) ωt φ–( )cos
1 ωτ( ) 2+
-------------------------------=
Amp.
t0 T
T
Figure A-12 Sample-and-hold output of RC networkwheret0= 0
where
V t0T2---+
∆ω t0
T2---–
φ+ cos ωt0 φ–( )cos–
eT 2τ⁄–
1 ωτ( ) 2+
----------------------------------------------------------------------------------------------------------------=
2≤ eT 2τ⁄–
1 ωτ( ) 2+
------------------------------⋅
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June 3, 1996
The relative error (Rerror) 0.01% in each sampling is sufficient to obtain total
distortion less than -62 dB, where
(A.11)
For 100 MHz sampling rate, T=10ns, the required RC time constant (τ) is about
0.5ns, equivalent to f-3db =300 MHz.
In contrast to a typical single pole role-off response of a RC network, the
modulation of the MOS resistance due to the sampling clock, causes the sinx/x
effect. This can intuitively be seen as follows. During the time(τ) when the gate of
the MOS resistor start to turn off until the gate level reachesVcm+Vt, the frequency
response is dependent on the input frequency. Since a RC network can be viewed
as an integrator, we can integrate the input wave form up to the time(τ) in order to
characterize the response in the frequency domain. The frequency over 50 MHz
doesn’t need to be considered. The input sinusoid whose frequency corresponds to
1/τ is blocked, and thus appears as a null in the frequency domain. The resistance
modulation doesn’t introduce distortion. Diode bridge track and hold does have
distortion. [9]
RerrorV t0
T2---+
∆
Amplitude of steady state output-------------------------------------------------------------------------------=
2 eT 2τ⁄–⋅=
104–≤
175
June 3, 1996
Appendix D
Detail schematic of ADC
D.1 Schematic of top
1. Figure A-13 illustrates the non-resetting S/H and 4-bit ADDA.
2. Figure A-14 illustrates the block diagram of one of 2 channel
D.2 Schematic of non-resetting S/H
3. Figure A-15 illustrates the schematic of S/H
4. Figure A-16 illustrates the schematic of S/H op amp
5. Figure A-17 illustrates the schematic of auxiliary amplifier for PMOS
cascade device
6. Figure A-18 illustrates the schematic of auxiliary amplifier for NMOS
cascode device
7. Figure A-19 illustrates the schematic of CMFB of non-resetting S/H
176
June 3, 1996
T/H amp
THOP
THIP
THIN
SPHI2_B
SPHI2
SPHI1_B
SPHI1
FPHI2_B
FPHI2
FPHI1_B
FPHI1
THON
Version 3
THON
th_clk
SPHI2_B
SPHI2
FPHI2_B
FPHI2
FPHI1
FPHI1_B
SPHI1
SPHI1_B
CLK100
CLK100B
ADP2
CLK100B
ADP1B
ADP1
CLKB
CLK
adclk
CLK100
RESET
DAON
DAOP
DB3
DB3B
DB2
DB2B
DB1
DB1B
DB0
DB0B
FBL
VRL
VRH
FBH
VDDA
CLK
CLKB
ADINN
ADINP
AD100
THOP
cpload100f
cpload100f
cpload100f
cpload100f
cpload100f
cpload100f
cpload100f
cpload100f
DAON
DAOP
DB0
DB0B
DB1
DB1B
DB2
DB2B
DB3
DB3B
FBH
FBL
PHI1PHI1B
PHI2
VDDA
VINN
VINP
VRH
VRL
ADDAH
100M
RESET
Figure A-13 Non-resetting S/H and 4-bit ADDA
177
June 3, 1996
RESET
DB0
DB0B
DB1
DB1B
DB2
DB2B
DB3
DB3B
FBH
FBL
PHI1PHI1B
PHI2
VDDA
VINN
VINP
VRH
VRL
AD V5
50M
RSA101
RSA202
RSA201
SEL
OUT1
OUT0
IN1
IN0
sel=H out=in
sel=L out=GND
selH
RSA102
VRH3
VRL3
PHI2
PHI1
PHI1B
CLK
CLKB
DAMNL
DAMPL
SELDAL
CLK
CLKB
HD0
HD0B
HD1
HD1B
HD2
HD2B
HD3
HD3B
LD0
LD0B
LD1
LD1B
LD2
LD2B
LD3
LD3B
MD0
MD0B
MD1
MD1B
MD2
MD2B
MD3
MD3B
Q0
Q0B
Q1
Q10
Q10B
Q11
Q11B
Q1B
Q2
Q2B
Q3
Q3B
Q4
Q4B
Q5
Q5B
Q6
Q6B
Q7
Q7B
Q8
Q8B
Q9
Q9B
RESET
DELAY REGISTER
G8N
G8P
SELG8
G4N
G4P
SELG4
G2N
G2P
THN
THP
DAHN
DAHP
OD9
OD9B
OD8
OD8B
OD7
OD7B
OD6
OD6B
OD5
OD5B
OD4
OD4B
OD3
OD3B
OD2
OD2B
OD1
OD1B
OD0
OD0B
HD0B
HD0
HD1B
HD1
HD2B
HD2
HD3B
HD3
VRL2
VRH2
VRL3
VRH3
VDDA
VDDA
AD50
FP1G2
FP1BG2
SP1G2
SP1BG2
FP2G2
FP2BG2
SP2BG2
SP2G2
FP1G4
SP1G4
SP1BG4
FP2G4
SP2G4
SP2BG4
FP2G2
FP1G2
CLK
CLKB
DAON
DAOP
DB0
DB0B
DB1
DB1B
DB2
DB2B
DB3
DB3B
FBH
FBL
VDDA
VINN
VINP
VRH
VRL
ADDA V5
50M
Version 5
Using Choi’s ECC
CLK
CLKB
D0
D1
D10
D11
D2
D3
D4
D5
D6
D7
D8
D9
OD0
OD0B
OD1
OD1B
OD2
OD2B
OD3
OD3B
OD4
OD4B
OD5
OD5B
OD6
OD6B
OD7
OD7B
OD8
OD8B
OD9
OD9B
RESET
ERROR CORRECTION
10BDA1
10BDA2
7BDA1
7BDA2
FPHI1B_G2
FPHI1_G2
FPHI1_G4
FPHI2B_G2
FPHI2_G2
FPHI2_G4
IN1
IN2
OREFH
OREFL
RSA1O1
RSA1O2
RSA2O1
RSA2O2
SEL_G4
SEL_G8
SLG2O1
SLG2O2
SLG4O1
SLG4O2
SLG8O1
SLG8O2
SPHI1B_G2
SPHI1B_G4
SPHI1_G2
SPHI1_G4
SPHI2B_G2
SPHI2B_G4
SPHI2_G2
SPHI2_G4
ver 5
resdueAmps
Figure A-14 Block diagram of one of 2 channel
178
June 3, 1996
VDDA
B220
VDD
b220
bias 220
SPHI1
SPHI1_B
SPHI1_B
SPHI1
THIN
D
PHI
PHIBAR
S
sw_40_120
D
PHI
PHIBAR
S
sw_40_120
THIP
SMPLP
THOP
B220
VDD
b220
bias 220
VDDA
D
PHI
PHIBAR
S
sw_60_60
D
PHI
PHIBAR
S
sw_60_60
D
PHI
PHIBAR
S
sw_60_60
D
PHI
PHIBAR
S
sw_80_80
D
PHI
PHIBAR
S
sw_60_60 D
PHI
PHIBAR
S
sw_60_60
D
PHI
PHIBAR
S
sw_80_80
D
PHI
PHIBAR
S
sw_60_60
D
PHI
PHIBAR
S
sw_60_60
D
PHI
PHIBAR
S
sw_60_60
B220
B220
SPHI1
SPHI1_B
SPHI2_B
SPHI2
FPHI1
FPHI1_B
SPHI2
SPHI2_B
FPHI2
FPHI2_B
FPHI2_B
FPHI1_B
FPHI1
FPHI2
SPHI2_B
SPHI2
FPHI2
FPHI2_B
FPHI1_B
FPHI1
FPHI1
FPHI1_B
FPHI2_B
FPHI2
THON
INBP
INPAMP
INNAMP
INBN
SMPLN
2.2P
C2
1.2P
C3
C4
1.2P
1.2P
C5
C6
1.2P
BO220
BO220
BO220
C1
2.2P
Updated 6-95
Non-Reset T/H
2121
22
4 5
SPHI1
SPHI1_B
SPHI2
SPHI2_B
opamp-th
Figure A-15 Schematic of non-resetting S/H
179
June 3, 1996
W=1000U
M9
12
VDDA
VDDA
VDDA
VDDA
VDDA
vout2
T/H Main OP amp
54
SPHI2
SPHI1
SPHI1_B
SPHI2_B
8
76
32
PHILP
PHILP
T_BIAS
PHILN
PHILN
vout1
5
PHIN
PHO
PH_BIN
T_BIAS
VDD
auxn_TH
T_BIAS
99
PHIN
PHO
PH_BIN
T_BIAS
VDD
auxp_TH
PHIN
PHO
PH_BIN
T_BIAS
VDD
auxp_TH
22vin2
21
vin1
T_BIASN
cmfb
4
1 2
SPHI2_B
SPHI2
SPHI1_B
SPHI1
CMFB4
CMFB3
CMFB2
cmfb th (v5)
M2
W=2240U
M1
W=2240U
M4
W=1200U
M3
W=1200U
M5
W=720U
M6
W=720U
M7
W=1600U
M8
W=1600U
VDDA
PHILP
T_BIASN
PHILN
9
CNTL_B
T_BIAS
11
2 3
6CNTL_BVDDA
cont_bias
philn
philp
t_bias
b_9
bias_g2main
T3
T_BIASN
PHIN
PHO
PH_BIN
T_BIAS
VDD
auxn_TH
Updated 6-95
Figure A-16 Schematic of non-resetting S/H op amp
180
June 3, 1996
VDD
PHIN
PHO
PH_BIN
2
3
6
4
PMOS auxiliary amp for TH
W=40U
MPHP8
T_BIAS
W=40U
MPHP9
W=100U
MPHP4
W=100U
MPHP6
W=100U
MPHP5
W=100U
MPHP3
W=40U
MPHP1
W=40U
MPHP2
W=100U
MPHP7
Scaled 400%
Figure A-17 Auxiliary amplifier for PMOS cascode devicein non-resetting S/H
181
June 3, 1996
W=200U
MPHN5
T_BIAS
PHIN
PH_BIN
PHO
3 4
VDD
NMOS auxiliary amp for TH
Scaled 400%
MPHN3
W=100.2U
MPHN4
W=100.2U
W=200U
MPHN6
MPHN7
W=200U
Figure A-18 Auxiliary amplifier for NMOS cascode devicein non-resetting S/H
182
June 3, 1996
common mode feedback for TH
CMFB10
cmfb9
cmfb10
CMFB9
CMFB10
CMFB10
SAM8
SAM6
SAM7
SAM5
AMP7
AMP8
AMP5
CMFB10
SPHI1_B
SPHI2_B
SPHI1
SPHI2
SPHI1_B
SPHI2_B
SPHI1
SPHI2
SPHI2_B
SPHI1_B
SPHI2
SPHI1
SPHI2_B
SPHI1_B
SPHI2
SPHI1
CMFB2
SPHI1
SPHI2
SPHI1_B
SPHI2_B
SPHI1
SPHI2
SPHI1_B
SPHI2_B
SPHI2
SPHI1
SPHI2_B
SPHI1_B
SPHI1
SPHI2
SPHI2_B
SPHI1_B
PHIBAR
PHI
DS
sw_20_20
PHIBAR
PHI
DS
sw_20_20
CMFB4
CMFB3
CMFB2
AMP6
CMFB10
CMFB9
PHIBAR
PHI
DS
sw_20_20
PHIBAR
PHI
DS
sw_20_20
PHIBAR
PHI
DS
sw_20_20
PHIBAR
PHI
DS
sw_20_20
PHIBAR
PHI
DS
sw_20_20
PHIBAR
PHI
DS
sw_20_20
PHIBAR
PHI
DS
sw_20_20
PHIBAR
PHI
DS
sw_20_20
PHIBAR
PHI
DS
sw_20_20
PHIBAR
PHI
DS
sw_20_20
PHIBAR
PHI
DS
sw_20_20
PHIBAR
PHI
DS
sw_20_20
PHIBAR
PHI
DS
sw_20_20
cmfb10
cmfb9
cmfb10
cmfb10
cmfb2cmfb3
cmfb3
cmfb2
cmfb4
CMFB3
CMFB9
CMFB9
VDD
CMFB9
cmfb9
cmfb9
PHIBAR
PHI
DS
sw_20_20
MCB1
W=12U
W=48U
MCB2
W=12.8U
MCB3
400F
CCM1
CCM2
400F
CCM3
400F
400F
CCM4
Scaled 400%
Version 3
Figure A-19 Schematic of CMFB of non-resetting S/H
183
June 3, 1996
D.3 First ADDA
1. Figure A-20 illustrates the block diagram of first ADDA (100 MHz)
2. Figure A-21 illustrates the block diagram of comparator circuit in first4-
bit quantizer
3. Figure A-22 illustrates the schematic of pre-amplifier in first 4-bit
quantize
4. Figure A-23 illustrates the schematic of latch in first 4-bit quantize
D.4 First residue amplifier
1. Figure A-24 illustrates the block diagram of first residue amplifier
2. Figure A-25 illustrates the schematic of gain-of-2 residue amplifier in
first residue amplifier bank
3. Figure A-26 illustrates the schematic of gain-of-2 residue amplifier in
first residue amplifier bank
D.5 Second residue amplifier
1. Figure A-27 illustrates schematic of gain-of-2 in second residue amplifier
2. Figure A-28 illustrates the schematic of gain-of-4 in second residue
amplifier
3. Figure A-29 illustrates the schematic of gain-of-4 in second residue
amplifier
184
June 3, 1996
1st Quantizer
for 1st DA
S14P
VREF
DOUT
VOUT
4bit DAC
ver 5
VD9P
VD9N
VD8P
VD8N
VD7P
VD7N
VD6P
VD6N
VD5P
VD5N
VD4P
VD4N
VD3P
VD3N
VD2P
VD2N
VD1P
VD1N
VD16P
VD16N
VD15P
VD15N
VD14P
VD14N
VD13P
VD13N
VD12P
VD12N
VD11P
VD11N
VD10P
VD10N
S9P
S8P
S7P
S6P
S5P
S4P
S3P
S2P
S1P
S16P
S15P
S13P
S12P
S11P
S10P
DAOP
DAON
for 1st Quant
ver 5
R Ladder
VREF
VRL
VRH
V9
V8
V7
V6
V5
V4
V31
V30
V3
V29
V28
V27
V26
V25
V24
V23
V22
V21
V20
V2
V19
V18
V17
V16
V15
V14
V13
V12
V11
V10
V1
FBL
FBH
ver 5
PHI2
100M
DOUT
VREF
4bit ADC
VIN
CLK
VINP
VINN
VI9P
VI9N
VI8P
VI8N
VI7P
VI7N
VI6P
VI6N
VI5P
VI5N
VI4P
VI4N
VI3P
VI3N
VI2P
VI2N
VI1P
VI1N
VI15P
VI15N
VI14P
VI14N
VI13P
VI13N
VI12P
VI12N
VI11P
VI11N
VI10P
VI10N
VDDA
D9P
D9N
D8P
D8N
D7P
D7N
D6P
D6N
D5P
D5N
D4P
D4N
D3P
D3N
D2P
D2N
D1P
D1N
D15P
D15N
D14P
D14N
D13P
D13N
D12P
D12N
D11P
D11N
D10P
D10N
ADDA version 5
PHI2
DB0BDB0
DB1BDB1
DB2BDB2
DB3B
DB3
V30
V2V28
V4V26
V6V24
V8V22
V10
V20
V12
V18
V14
V16
V16
V14
V18
V12
V20
V10
V22
V8V24
V6V26
V4V28
V2V30
FBL
FBH
V3
V27
V29
V5
V25
V7
V23
V9
V21
V11
V19
V13
V17
V15
V15
V17
V13
V19
V11
V21
V9
V23
V7
V25
V5
V27
V3
V11
V12
V31
V29
V1
V31
FBL
FBH
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
VRL
VRH
DAON
DAOP
VINN
VINP
VDDA
AE2
DB0B
DB1B
DB2B
DB3B
AE11
AE12
AE13
AE15
AE16
IN
ENCODER
OUT
AE14
AE9
AE8
AE7
AE6
AE5
AE4
AE3
DB3
DB2
DB1
DB0
AE1
AE10
PHI1
PHI1B
D10N
D10P
D11N
D11P
D12N
D12P
D13N
D13P
D14N
D14P
D15N
D15P
D1N
D1P
D2N
D2P
D3N
D3P
D4N
D4P
D5N
D5P
D6N
D6P
D7N
D7P
D8N
D8P
D9N
D9P
PHI1
PHI1B
S10N
S10P
S11N
S11P
S12N
S12P
S13N
S13P
S14N
S14P
S15N
S15P
S16N
S16P
S1N
S1P
S2N
S2P
S3N
S3P
S4N
S4P
S5N
S5P
S6N
S6P
S7N
S7P
S8N
S8P
S9N
S9P
v5
DIN
DAC SEL DOUT
CLK
100 M
Figure A-20 Block diagram of first ADDA (100 MHz)
185
June 3, 1996
ICNTL
V5
DINN
DINP
DOUTN
DOUTP
PHI2
--
++
4bit ADC version5
V5VDDA
VINN
VINP
VREFN
VREFP
- +
+
--
+ACOP
ACON
ICNTL
V5
DINN
DINP
DOUTN
DOUTP
PHI2
--
++
V5
DINN
DINP
DOUTN
DOUTP
PHI2
--
++
V5VDDA
VINN
VINP
VREFN
VREFP
- +
+
--
+ACOP
ACON
ICNTL
V5VDDA
VINN
VINP
VREFN
VREFP
- +
+
--
+ACOP
ACON
ICNTL
V5VDDA
VINN
VINP
VREFN
VREFP
- +
+
--
+ACOP
ACON
ICNTL
V5VDDA
VINN
VINP
VREFN
VREFP
- +
+
--
+ACOP
ACON
ICNTL
V5VDDA
VINN
VINP
VREFN
VREFP
- +
+
--
+ACOP
ACON
ICNTL
V5VDDA
VINN
VINP
VREFN
VREFP
- +
+
--
+ACOP
ACON
ICNTL
V5VDDA
VINN
VINP
VREFN
VREFP
- +
+
--
+ACOP
ACON
ICNTL
V5VDDA
VINN
VINP
VREFN
VREFP
- +
+
--
+ACOP
ACON
ICNTL
V5VDDA
VINN
VINP
VREFN
VREFP
- +
+
--
+ACOP
ACON
ICNTL
V5VDDA
VINN
VINP
VREFN
VREFP
- +
+
--
+ACOP
ACON
ICNTL
V5VDDA
VINN
VINP
VREFN
VREFP
- +
+
--
+ACOP
ACON
ICNTL
V5
DINN
DINP
DOUTN
DOUTP
PHI2
--
++
V5
DINN
DINP
DOUTN
DOUTP
PHI2
--
++
V5
DINN
DINP
DOUTN
DOUTP
PHI2
--
++
V5
DINN
DINP
DOUTN
DOUTP
PHI2
--
++
V5
DINN
DINP
DOUTN
DOUTP
PHI2
--
++
V5
DINN
DINP
DOUTN
DOUTP
PHI2
--
++
V5
DINN
DINP
DOUTN
DOUTP
PHI2
--
++
V5
DINN
DINP
DOUTN
DOUTP
PHI2
--
++
V5
DINN
DINP
DOUTN
DOUTP
PHI2
--
++
V5
DINN
DINP
DOUTN
DOUTP
PHI2
--
++
VI1P
VI1N
D1P
D1N
VI2P
VI2N
D2P
D2N
VI3P
VI3N
D3P
D3N
VI4P
VI4N
D4P
D4N
VI5P
VI5N
D5P
D5N
VI6P
VI6N
D6P
D6N
VI7P
VI7N
D7P
D7N
VI8P
VI8N
D8P
D8N
VI9P
VI9N
D9P
D9N
VI11P
VI11N
D11P
D11N
VI12P
VI12N
D12P
D12N
VI13P
VI13N
D13P
D13N
VI14P
VI14N
D14P
D14N
VI15P
VI15N
D15P
D15N
VI10P
VI10N
D10P
D10N
VINP
PHI2
V5VDDA
VINN
VINP
VREFN
VREFP
- +
+
--
+ACOP
ACON
ICNTL
V5VDDA
VINN
VINP
VREFN
VREFP
- +
+
--
+ACOP
ACON
ICNTL
V5
DINN
DINP
DOUTN
DOUTP
PHI2
--
++
V5
DINN
DINP
DOUTN
DOUTP
PHI2
--
++
V5VDDA
VINN
VINP
VREFN
VREFP
- +
+
--
+ACOP
ACON
ICNTL
VDDA
VINN
Figure A-21 Block diagram of comparator circuit in first4-bit quantizer
186
June 3, 1996
W=160U
M34
M33
W=40U
M36
L=1U
W=12U
M35
L=1U
W=12U
VDDA
VDDA
VREFN
VINN
W=3U
M11
M12
W=3U
W=3U
M14
M9
L=1U
W=12U
M10
L=1U
W=12U
W=20U
M13
M5
W=20U
M7
W=20U
W=80U
M6
M8
W=80U
VREFP
VINP
Analog COMP(100M)
ACOP_1
ACON
ACON_1
M1
L=1U
W=40U
M2
L=1U
W=40U
M3
L=1U
W=40U
M4
W=40U
L=1U
ICNTL
M31
L=1U
W=14.4U
M32
L=1U
W=14.4U
Updated 6-95
ACOP
Figure A-22 Schematic of pre-amplifier in first 4-bit quantizer
187
June 3, 1996
Figure A-23 Schematic of latch in first 4-bit quantize
DOUTN_1
DOUTP_1
M21
W=6U
C2
20F
C1
20F
PHI2
PHI2
M17
W=8U
W=4U
M22
M23
W=4U
DINP
DINN
PHI2
W=8U
M18
DOUTP_1
DOUTN_1
D COMP
VDD
DOUTN
DOUTP_1
DOUTN_1
DOUTP
M19
W=8U
W=8U
M53
M52
W=8U
W=8U
M54
100 uA
W=8U
M20
Updated 6-95
W=8U
M51
188
June 3, 1996
Figure A-24 Block diagram of first residue amplifier
G42_OUT2
G42_OUT1
G41_OUT2
G41_OUT1
SS_BPHI2_G2
SS_PHI2_G2
SS_BPHI1_G2
SS_PHI1_G2
FF_BPHI1_G2
FF_PHI1_G2
SS_BPHI1_G4
SS_BPHI1_G4
SS_PHI1_G4
SS_PHI1_G4
PHIBAR
PHI
DS
sw_40_80
PHIBAR
PHI
DS
sw_40_80
PHIBAR
PHI
DS
sw_40_80
FF_PHI1_G4
G2_OUT2
G2_OUT1
PHIBAR
PHI
DS
sw_40_80
G8_OUT1
G8_OUT2
SS_PHI1_G4
SS_BPHI1_G4
gain4amp
SPHI2_B
SPHI2
SPHI1_B
SPHI1
FPHI1
5431
32
SS_BPHI2_G4
SS_PHI2_G4
FF_PHI2_G4
SS_PHI2_G4
SS_BPHI2_G4
SS_BPHI1_G4
SS_PHI1_G4
SS_PHI2_G4
SS_BPHI2_G4
SS_PHI2_G4
SS_BPHI2_G4
DAC1
DAC2
IN2
IN1
gain4amp
SPHI2_B
SPHI2
SPHI1_B
SPHI1
FPHI1
5431
32
32
31
gain2amp
SPHI2_B
SPHI2
SPHI1_B
SPHI1
FPHI1_B
FPHI1
DAC2
DAC1
54
M=1
189
June 3, 1996
D
PHI
PHIBAR
S
sw_24_135
1.80P
C1
1.80P
C2
0.9P
C2F
SD
PHI
sw_75.2
0.9P
C1F
CCOMP2
4.5P
4.5P
CCOM1
Gain of 2 amp
opamp-gain2
2121
22
4 5
SPHI1
SPHI1_B
SPHI2
SPHI2_B
B260
B260
VDD
bias 260
b260
2
VDD
B260
32
SPHI1_B
SPHI1
SPHI1
SPHI1_B
31
D
PHI
PHIBAR
S
sw_44.8_44.8
D
PHI
PHIBAR
S
sw_44.8_44.8
SPHI2_B
SPHI2
DAC1
40
22
21
PHI
DS
sw_30PHI
DS
sw_30
PHIBAR
PHI
D S
sw_12_24
PHIBAR
PHI
D S
sw_12_24
SPHI2_B
SPHI2
FPHI1
FPHI1_B
sw_10_20
PHIBAR
PHI
DS
FPHI1
FPHI1
SPHI2
SPHI2_B
SPHI1
SPHI1_B
SD
PHI
sw_75.2
sw_10_20
PHIBAR
PHI
DS
SPHI2
SPHI2_B
FPHI1
FPHI1
4
FPHI1_B
FPHI1
42
5
34
SPHI2
SPHI2_B
DAC2
33
D
PHI
PHIBAR
S
sw_24_135
125% size Increase
Version 5
Figure A-25 Schematic of gain-of-2 residue amplifier in first residue amplifier bank
190
June 3, 1996
D
PHI
PHIBAR
S
sw_24_48D
PHI
PHIBAR
S
sw_24_48
PHIBAR
PHI
DSsw_8_16
C1F
0.5P
0.5P
C2F
1.505P
C2
1.505P
C1
B260
B260
Gain of 4 amp
SPHI1_B
SPHI1
SPHI1_B
SPHI1
SPHI2
SPHI2_B
PHIBAR
PHI
D S
sw_4_8
SPHI2
SPHI2_B
D
PHI
PHIBAR
S
sw_24_48
21
22
4
FPHI1
PHI
DS
sw_50
FPHI1
PHI
DS
sw_50
B260
D
PHI
PHIBAR
S
sw_24_48
34
40
S
PHI
D
sw_24
SPHI2_B
SPHI2
SPHI2
SPHI2_B
FPHI1
FPHI1
33
SPHI1
SPHI1_B
SPHI2
SPHI2_B
31
42
32
5
SPHI1_B
SPHI1
SPHI1
SPHI1_B
PHIBAR
PHI
D S
sw_4_8
PHIBAR
PHI
DSsw_8_16
VDD
21
22
4 5
SPHI1
SPHI1_B
SPHI2
SPHI2_B
1 2
opamp-gain2
v5
50% size increased
CCOM1
3.6P
3.6P
CCOMP2
bias 260
b260
2
VDD
S
PHI
D
sw_24
Version 3
Figure A-26 Schematic of gain-of-2 residue amplifier in first residue amplifier bank
191
June 3, 1996
Gain of 2 amp in 2RA
SPHI2_B
SPHI2
SPHI1_B
SPHI1
54
22
21
1 2
opamp-gain2
D
PHI
PHIBAR
S
sw_10_60
33
DAC2
SPHI2_B
SPHI2
CCOM1
3.0P
3.0P
CCOMP2
34
5
42
FPHI1
FPHI1_B
4
FPHI1
FPHI1
SPHI2_B
SPHI2 PHIBAR
PHI
DSsw_7_14
PHI
DS
sw_50
SPHI1_B
SPHI1
SPHI2_B
SPHI2
FPHI1
FPHI1
PHIBAR
PHI
DSsw_7_14
FPHI1_B
FPHI1
SPHI2
SPHI2_B
S
PHIBAR
PHI
D
sw_6_12
S
PHIBAR
PHI
D
sw_6_12
PHI
DS
sw_20PHI
DS
sw_20
22
40
DAC1
SPHI2
SPHI2_B
SD
PHI
PHIBAR
sw_30_30
SD
PHI
PHIBAR
sw_30_30D
PHI
PHIBAR
S
sw_10_60
31
SPHI1_B
SPHI1
SPHI1
SPHI1_B
32
B260
bias 260
b260
2
VDDVDD
B260
B260
21
PHI
DS
sw_50
C1
0.80P
C2
0.80P
C1F
0.40P
C2F
0.40P
Figure A-27 Schematic of gain-of-2 in second residue amplifier
192
June 3, 1996
B260
CLK BUFFIN1
IN2
OUT1
OUT2
SPHI2
SPHI1
CNTL1
CNTL2
CNTL3
IN
OPAMPIN
REF
SPH1
SPH2
OFF Cont Sw
REFL
LH
INLA
INHB
INHA
SEL
OUT1
OUT0
INLB
select
22
Gain of 4 amp at 2nd RA
D
PHI
PHIBAR
S
sw_3_6
0.752P
C2
0.752P
C1
B260
B260
PHI
DS
sw_20
3.0P
CCOMP2
CCOM1
3.0P
SPHI1_B
SPHI1
SPHI1_B
SPHI1
SPHI2
SPHI2_B
SPHI2
SPHI2_B
PHIBAR
PHI
DS
sw_12_24
4
C1F
0.25P
0.25P
C2F
FPHI1
PHI
DS
sw_50
FPHI1
PHI
DS
sw_50
B260
S D
PHI
PHIBAR
sw_15_30
34
40
PHI
DS
sw_20
SPHI2_B
SPHI2
SPHI2
SD
PHI
PHIBAR
sw_15_30
SPHI2_B
FPHI1
FPHI1
33
SPHI2_B
SPHI2
SPHI1_B
SPHI1
54
22
21
1 2
opamp-gain2
SPHI1
SPHI1_B
SPHI2
SPHI2_B
42
5
PHIBAR
PHI
DS
sw_12_24
SPHI1_B
SPHI1
SPHI1
SPHI1_B
D
PHI
PHIBAR
S
sw_3_6
PHIBAR
PHI
DSsw_4_8
PHIBAR
PHI
DSsw_4_8
bias 260
b260
2
VDDVDD
CNTL1
CNTL2
CNTL2
CNTL3
CNTL3
CNTL1
CNTLSGN
31
32
CNTL1
CNTL2
CNTL3
IN
OPAMPIN
REF
SPH1
SPH2
OFF Cont Sw
B260
REFH
21
LB_SPH2
LB_SPH1
Figure A-28 Schematic of gain-of-4 in second residue amplifierwith simple offset control switch
193
June 3, 1996
B_CASN
B_CASP
B_SOU
PHIN
PHO
PH_BIN
T_BIAS
VDD
auxp_fold_st2g2
W=560U
M1
VDD
VDD
PHILN
B_CASN B_CASP
B_SOU
PHIN
PHO
PH_BIN
VDD
auxn_fold_st2g2
B_CASN
B_CASP
B_SOU
7
B_CASN
B_CASP
B_SOU
PHIN
PHO
PH_BIN
VDD
auxn_fold_st2g2
PHILN
VDD
B_CASN
B_CASP
B_SOU
6
B_CASN
B_CASP
B_SOU
T_BIAS
PHILP
VDD
VDD
2
PHILP
B_CASP
B_CASN
B_SOU
T_BIAS
bias_g2main(v3)
11
2 3
6
VDD
philn
philp
t_bias
b_9
W=400U
M8
vin1
vin2
VDD
99
vout1
vin2
W=560U
M2
W=300U
M3
W=300U
M4
W=180U
M6
W=180U
M5
W=400U
M7
9
T_BIAS
PHILN
PHILP
VDD
cmfb
3
4 5
SPHI2_B
SPHI2
8
M9
W=250U
Gain of 2 Main OP amp
SPHI1_B
SPHI1
Version3
CMFB2
CMFB3
CMFB4
SPHI1
SPHI1_B
SPHI2
SPHI2_B
21
cmfb_2RA_g2(v3)
B_CASN
B_CASPB_SOU
PHIN
PHO
PH_BIN
T_BIAS
VDD
auxp_fold_st2g2
B_SOU
B_CASP
B_CASN
V3
Bias for AUXNP
B_SOU
VDD
B_CASP
B_CASN
2RA
IC=2.0
21
IC=2.0
22
IC=2.7
4
IC=2.7
5
IC=1.4
12
Figure A-29 Schematic of op amp in second residue amplifier bank
194
June 3, 1996
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