an1997 usb-to-gpio bridging with microchip usb3.1 gen1 hubs application...

AN1997USB-to-GPIO Bridging with Microchip USB3.1 Gen1

Hubs

INTRODUCTION

The USB-to-GPIO Bridging feature of Microchip’s USB 2.0 hubs provides system designers expanded system control and potential BOM reduction. General Purpose Input/Outputs (GPIOs) may be used for any general 3.3V-level digital control and input functions. This feature is available on the Microchip USB5734 and USB58xx/USB59xx USB3.1 Gen 1 Hubs.

Commands may be sent from the USB Host to the internal Hub Feature Controller device in the Microchip hub to per-form the following functions:

• Set the direction of the GPIO (input or output)

• Enable a pull-up resistor

• Enable a pull-down resistor

• Read the state

• Set the state

SECTIONS

Section 1.0, General Information

Section 2.0, Part Number-Specific Information

Section 3.0, Microchip Software Solutions

Section 4.0, Manual Implementation

Section 5.0, Examples

Section 6.0, GPIO Default States

Section 7.0, GPIO Control via SMbus Interface

REFERENCES

Consult the following documents for details on the specific parts referred to in this document.

• Microchip USB5734 Data Sheet








• Microchip AN1903 Configuration Options for the USB5734 and USB5744

• Microchip AN2316 Configuration Options for the USB58xx and USB59xx

Author: Andrew RogersMicrochip Technology Inc.

2015-2019 Microchip Technology Inc. DS00001997C-page 1

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1.0 GENERAL INFORMATION

Microchip hub USB-to-GPIO Bridging features in Microchip hubs work via host commands sent to a Hub Feature Con-troller embedded within the hub located on an additional internal USB port. In order for the bridging features to work correctly, this internal Hub Feature Controller must be enabled by default. Table 1 provides details on default Hub Fea-ture Controller setters by device.

TABLE 1: DEFAULT SETTINGS FOR THE HUB FEATURE CONTROLLER ENABLE

Part Number Part SummaryHub Feature Controller Default

Setting

USB5734 4-Port USB3.1 Gen 1 Hub Enabled by default

USB5806 6-Port USB3.1 Gen1 Hub Enabled by default

USB5807 7-Port USB3.1 Gen1 Hub Not available (Note 1)

USB5816 6-Port USB3.1 Gen1 Hub with Type-C™ Support on 1 Downstream Port

Enabled by default

USB5826 6-Port USB3.1 Gen1 Hub with Type-C Support on 2 Downstream Ports

Enabled by default

USB5906 6-Port USB3.1 Gen1 Hub with Type-C Support on the Upstream Port

Enabled by default

USB5916 6-Port USB3.1 Gen1 Hub with Type-C Support on the Upstream Port and 1 Downstream Port

Enabled by default

USB5926 6-Port USB3.1 Gen1 Hub with Type-C Support on the Upstream Port and 2 Downstream Ports

Enabled by default

Note 1: The USB5807 does not have an internal Hub Feature Controller device. The USB-to-GPIO functionality is not available on this device, but GPIO control is still available through the SMBus slave interface.

The Hub Feature Controller is a USB2.0 generic USB class device (WinUSB drivers are used in Windows® systems) connected to an extra internal USB2.0 port in the hub. For example, in a four-port hub, the Hub Feature Controller is connected to Port 5 of the USB2.0 portion of the hub. The Product ID (PID) for the Hub Feature Controller is 0x2740 on USB5734, and 0x2840 on USB58xx/USB59xx. All bridging commands are addressed to the Hub Feature Controller, not the Hub.

FIGURE 1: MICROCHIP HUB CONTROLLER EXAMPLE

USB Host

MicrochipUSB5734 GPIO

I2CUARTSPI

prt4prt1 prt2 prt3

prt5

UpstreamPort

Hub FeatureController

DownstreamPort

DownstreamPort

DownstreamPort

DownstreamPort

U S B D e v i c e s

VID = 0x0424PID = 0x2740

See Figure 1 and Figure 2.

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FIGURE 2: MICROCHIP HUB CONTROLLER EXAMPLE

USB Host

MicrochipUSB5806 GPIO

I2C

SPI

prt5prt2 prt3 prt4

prt7

UpstreamPort

Hub FeatureController

DownstreamPort

DownstreamPort

DownstreamPort

DownstreamPort

U S B D e v i c e s

VID = 0x0424PID = 0x2840

prt1

DownstreamPort

prt6

DownstreamPort

The following GPIO Functions are supported:

• Set the GPIO Direction (Input or Output)

• Enable GPIO Internal Pull-up Resistor

• Enable GPIO Internal Pull-down Resistor

• GPIO Read State (Input Mode)

• GPIO Set State (Output Mode)

1.1 Set the GPIO Direction (Input or Output)

Each GPIO can be configured as either a Schmitt-triggered input or output with an 8 mA sink/source.

1.2 Enable GPIO Internal Pull-up Resistor

Each GPIO can be enabled with a 50 μA (typical) internal pull-up resistor. Internal pull-up resistors prevent unconnected inputs from floating. The pull-up is only 67k, so it may not be strong enough to drive a load of less than 100k. When connected to a load that must be pulled high, an external resistor must be added.

1.3 Enable GPIO Internal Pull-down Resistor

Each GPIO can be enabled with a 50 μA (typical) internal pull-down resistor. Internal pull-down resistors prevent uncon-nected inputs from floating. The pull-down is only 67k, so it may not be strong enough to drive a load of less than 100k. When connected to a load that must be pulled low, an external resistor must be added.

1.4 GPIO Read State (Input Mode)

Read a 0: GPIO is below 0.9V

Read a 1: GPIO is above 1.9V

Note: When configured as an input, the GPIOs are digital Schmitt-triggered inputs. The range 0.8V to 2.0V is an indeterminate input state, so 3.3V-to-2.5V signaling is supported.

1.5 GPIO Set State (Output Mode)

Set to 0: GPIO Drives to 0.0V. When driven low, an 8 mA sink is enabled driving the pin to 0.4V or lower.

Set to 1: GPIO Drives to 3.3V. When driven high, an 8 mA source is enabled driving the pin to VDD33 – 0.4V or higher.


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2.0 PART NUMBER-SPECIFIC INFORMATION

2.1 Part Summary

Table 2 summarizes the total number of available GPIOs by part number. Many of the GPIOs on the hub are only avail-able after configuration. The following methods may be used to configure the hub:

• MPLAB Connect: If configuring via internal One-Time Programmable (OTP) memory, or if configuring via EEPROM with a base firmware file.

• SMBus/I2C Configuration: If using an embedded SoC/I2C EEPROM to configure the hub at each startup/reset.

• Pin Strapping: Many of the GPIOs are made available by specific pin strapping or by simply not populating an SPI EEPROM device.

TABLE 2: GPIO AVAILABILITY SUMMARY

USB5734 USB5806 USB5807 USB5816 USB5826 USB5906 USB5916 USB5926

GPIOS Available By Default

7 1 1 3 3 3 3 3

Maximum Available GPIOs

16 25 25 25 25 25 25 25

Note 1: USB5807 does not have an internal Hub Feature Controller device. GPIOs may only be configured and operated via the SMBus slave interface for this device.


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2.2 USB5734 GPIO Pins

TABLE 3: USB5734 GPIO AVAILABILITY AND CONFIGURATION REQUIREMENTS

Pin # Name Primary Function Configuration Required

7 GPIO7 PROG_FUNC7/GPIO Set CFG_STRAP to Mode 4.

34 GPIO20 Port 4 Port Power Control

Disable Port 4 and Disable Port Power 4 Output + OCS 4 InputorSet hub into Port Power Ganged Mode and Disable Port Power 4 Output + OCS 4 Input.







39 GPIO2 PROG_FUNC2/GPIO Set CFG_STRAP to Mode 1 or 4.

40 GPIO3 PROG_FUNC3/GPIO Set CFG_STRAP to Mode 1 or 4.

41 GPIO16 VBUS_DET Disable VBUS_DET function.

42 GPIO4 SPI_CLK Do not use SPI ROM (Note 1), UART, or I2C interface.

43 GPIO5 SPI_DO Do not use SPI ROM (Note 1), UART, or I2C interface.

44 GPIO9 SPI_DI Do not use SPI ROM (Note 1).

45 GPIO7 SPI_CE_N Do not use SPI ROM (Note 1).

46 GPIO6 PROG_FUNC4/GPIO Set CFG_STRAP to Mode 4.

47 GPIO8 PROG_FUNC5/GPIO Set CFG_STRAP to Mode 4 or Mode 5.



Note 1: SPI Data pins will oscillate at 30/60 MHz for a short period at startup to detect the presence of an SPI Flash device with a valid firmware image signature. There is no way to disable this toggling. Only use these pins as GPIOs if toggling at power on can be tolerated by the system.




20 GPIO12 CFG_STRAP Custom firmware required to remove FW control of pin (Note 2)

21 GPIO10 FLEX_CMD Custom firmware required to remove FW control of pin (Note 2)

22 GPIO72 FLEX_STATE Custom firmware required to remove FW control of pin (Note 2)

50 GPIO65 SPEED_IND5 Custom firmware required to remove FW control of pin (Note 2)

51 GPIO22 PRT_CTL6 Disable Logical Port 6 and Disable Logical Port Power 6 Output + OCS 6 InputorSet hub into Port Power Ganged Mode and Logical Disable Port Power 6 Output + OCS 6 Input.


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53 GPIO23 HOST_TYPE0 Custom firmware required to remove FW control of pin (Note 2)



57 GPIO20 PRT_CTL4/GANG_PWR

Disable Logical Port 4 and Disable Logical Port Power 4 Output + OCS 4 Input.






65 GPIO4 SPI_DO/C_ATTACH3 Do not use SPI ROM (Note 1), Custom firmware required to remove FW control of pin (Note 2).

66 GPIO5 SPI_DI/C_ATTACH2 Do not use SPI ROM (Note 1), Custom firmware required to remove FW control of pin (Note 2).

69 GPIO69 GPIO69 GPIO69 by default



73 GPIO1 C_ATTACH1 Custom firmware required to remove FW control of pin (Note 2)

74 GPIO6 SMBDATA Custom firmware required to remove FW control of pin (Note 2)

75 GPIO8 SMBCLK Custom firmware required to remove FW control of pin (Note 2)


77 GPIO68 SUSP_IND Custom firmware required to remove FW control of pin (Note 2)


2: Customized firmware can be supported on the Microchip USB5734 and USB58xx/USB59xx devices through either an application of a patch to the default firmware loaded from internal ROM or by executing an entirely separate firmware image from an attached SP Flash device. Development of customized firm-ware is assessed on a case-by-case basis and requires support from Microchip developers. Contact your Microchip sales representative to discuss the possibility of customized firmware.




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21 GPIO10 FLEX_CMD Custom firmware required to remove FW control of pin (Note 2)

22 GPIO72 FLEX_STATE Custom firmware required to remove FW control of pin (Note 2)

50 GPIO65 SPEED_IND5/BC_IND5

Custom firmware required to remove FW control of pin (Note 2)


















65 GPIO4 SPI_DO/C_ATTACH3 Do not use SPI ROM (Note 1). Custom firmware required to remove FW control of pin (Note 2).

66 GPIO5 SPI_DI/C_ATTACH2 Do not use SPI ROM (Note 1). Custom firmware required to remove FW control of pin (Note 2).



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21 GPIO10 NC Custom firmware required to remove FW control of pin (Note 2)


50 GPIO65 AB1/ATTACH_MUX1B











61 GPIO71 CC_POL Custom firmware required to remove FW control of pin (Note 2)


63 GPIO70 ALT_MUX_EN Custom firmware required to remove FW control of pin (Note 2)

65 GPIO4 SPI_DO/C_ATTACH3 Do not use SPI ROM (Note 1). Custom firmware required to remove FW control of pin (Note 2).

66 GPIO5 SPI_DI/C_ATTACH2 Do not use SPI ROM (Note 1). Custom firmware required to remove FW control of pin (Note 2).




73 GPIO1 C_ATTACH1/ATTACHMUX1A






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50 GPIO65 AB1/ATTACH_MUX1B


51 GPIO22 PRT_CTL4 Disable Logical Port 4 and Disable Logical Port Power 4 Output + OCS 4 InputorSet hub into Port Power Ganged Mode and Logical Disable Port Power 4 Output + OCS 4 Input

52 GPIO21 PRT_CTL3 Disable Logical Port 3 and Disable Port Power 3 Output + OCS 3 InputorSet hub into Logical Port Power Ganged Mode and Logical Disable Port Power 3 Output + OCS 3 Input.







58 GPIO19 PRT_CTL2 Disable Logical Port 2 and Disable Logical Port Power 2 Output + OCS 2 InputorSet hub into Port Power Ganged Mode and Disable Logical Port Power 2 Output + OCS 2 Input.





65 GPIO4 SPI_CLK Do not use SPI ROM (Note 1).

66 GPIO5 SPI_DO Do not use SPI ROM (Note 1).


70 GPIO17 PRT_CTL1 Disable Port 1 and Disable Port Power 1 Output + OCS 1 InputorSet hub into Port Power Ganged Mode and Disable Port Power 1 Out-put + OCS 1 Input.

71 GPIO66 AB2/ATTACHMUX2B GPIO66 by default








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22 GPIO72 NC Custom firmware required to remove FW control of pin(Note 2)









58 GPIO19 PRT_CTL3 Disable Logical Port 3 and Disable Logical Port Power 3 Output + OCS 3 InputorSet hub into Port Power Ganged Mode and Disable Logical Port Power 3 Output + OCS 3 Input

60 GPIO3 AB0/ATTACHMUX0B Custom firmware required to remove FW control of pin (Note 2)







70 GPIO17 PRT_CTL1 Disable Port 1 and Disable Port Power 1 Output + OCS 1 InputorSet hub into Port Power Ganged Mode and Disable Port Power 1 Output + OCS 1 Input.








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63 GPIO70 ALT_MUX_EN Custom firmware required to remove FW control of pin2

65 GPIO4 SPI_CLK Do not use SPI ROM (Note 1)

66 GPIO5 SPI_DO Do not use SPI ROM (Note 1)











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52 GPIO21 PRT_CTL3 Disable Logical Port 3 and Disable Port Power 3 Output + OCS 3 InputorSet hub into Logical Port Power Ganged Mode and Logical Disable Port Power 3 Output + OCS 3 Input
























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3.0 MICROCHIP SOFTWARE SOLUTIONS

Microchip currently offers two publicly available software solutions to facilitate USB-to-GPIO Bridging in USB5734 and USB58xx/USB59xx USB3.1 Gen 1 Hubs on Windows and Linux.

3.1 MPLAB Connect Configurator Package (For Windows)

The MPLAB Connect Configurator (MPLABCC) package consists of both GUI-based and CLI-based tools which support USB-to-GPIO Bridging in a standalone form. In addition to these, it contains a Dynamically Linked Library (DLL) for Win-dows which can be used for implementing USB-to-GPIO Bridging feature in custom applications using C programming language. The MPLABCC DLL consists of the following:

User's guide: A detailed description of how to use the DLL API to call each function

Release notes

Library files: A .dll and a .lib file

Example code

3.2 Application Code Examples (For Linux)

For implementing USB-to-GPIO Bridging on Linux, you can use the following USB5734 and USB58xx/USB59xx Linux® Application Code Example (ACE):

ACE009 USB-to-GPIO Bridging: This ACE demonstrates how to use the GPIO Master interface of the hub to perform read/write operations. It also allows the user to select from a range of GPIO clock frequencies.

This application example uses libusb library for Linux to build and send USB packets as described in Manual Implemen-tation. It is a full-feature code example that consists of:

Example code with minimal abstraction and in-line comments describing the various steps involved:

A Makefile

README

This ACE can be used as a standalone application and can be integrated into existing applications.


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4.0 MANUAL IMPLEMENTATION

The USB-to-GPIO Bridging features may be implemented at the lowest level if you have the ability to build USB packets. This approach is required if you are not using a Windows or Linux host system and cannot use the SDK.

All USB-to-GPIO Bridging commands are accomplished with internal register writes and reads. Further details can be found in Microchip application note AN1903 Configuration Options for the USB5734 and USB5744 or AN2316 Config-uration Options for the USB58xx and USB59xx. All USB-to-GPIO Bridging commands must be sent directly to Endpoint 0 of the Hub Feature Controller connected to the last downstream port of the Microchip hub (i.e. located on Port 5 of a four-port hub).

For details on the register read and write USB SETUP packets, refer to Section 4.1, "Register Read" and Section 4.2, "Register Write", respectively. The configuration register addresses and contents are detailed in Section 4.3, "GPIO Configuration Register Map for USB5734" and Section 4.4, "Register Definitions for USB5734".

4.1 Register Read

To read the state of a GPIO, a register read with the USB SETUP packet in Table 11 must be used.

TABLE 11: REGISTER READ USB SETUP COMMAND

SETUP Parameter Value Description

bmRequestType 0xC1 Device-to-host, vendor class, targeted to interface

bRequest 0x04 Register read command: CMD_REG_READ

wValue Register Address Valid Address Range: <0x0000> to <0xFFFF> [64KB]

wIndex 0x0000 Reserved

wLength Data Length Length of the data bytes to be retrieved

4.1.1 REGISTER READ USB TRANSACTION SEQUENCE

Command Phase: Hub Feature Controller receives the SETUP packet with the parameters specified in Table 11.

Data Phase: Hub Feature Controller sends the data bytes of length wLength from the specified address.

Status Phase: Hub Feature Controller sends ACK on successful completion of register read.

4.2 Register Write

To configure the direction of a GPIO, pull-up/pull-down resistor settings, or set the output state of a GPIO, a register write command with the USB SETUP packet in Table 12 must be used:

TABLE 12: REGISTER WRITE USB SETUP COMMAND

SETUP Parameter Value Description

bmRequestType 0x41 Host-to-device, vendor class, targeted to interface

bRequest 0x03 Register read command: CMD_REG_WRITE

wValue Register Address Valid Address Range: <0x0000> to <0xFFFF> [64KB]

wIndex 0x0000 Reserved

wLength Data Length Length of data bytes to write

4.2.1 REGISTER WRITE USB TRANSACTION SEQUENCE

Command Phase: Hub Feature Controller receives the SETUP packet with the parameters specified in Table 11.

Data Phase: Hub Feature Controller receives the data bytes of length wLength to be written to the register starting from the specified address.

Status Phase: Hub Feature Controller sends ACK on successful completion of register write.


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4.3 GPIO Configuration Register Map for USB5734

TABLE 13: USB5734 GPIO CONFIGURATION REGISTER MEMORY MAP

Addr. R/W Name Function Default

082Ch R/W GPIO_1_7_PD USB5734 GPIO 1-7 Pull-down Register 00h

082Dh R/W GPIO_8_11_PD USB5734 GPIO 8-11 Pull-down Register 00h

082Eh R/W GPIO_16_20_PD USB5734 GPIO 16-20 Pull-down Register 00h

0830h R/W GPIO_1_7_DIR USB5734 GPIO 1-7 Direction Control Register 00h



0834h R/W GPIO_1_7_OUT USB5734 GPIO 1-7 Output Register 00h



0838h R/W GPIO_1_7_IN USB5734 GPIO 1-7 Input Register 00h

0839h R/W GPIO_8_11_IN USB5734 GPIO 8-11 Input Register 00h

083Ah R/W GPIO_16_20_IN USB5734 GPIO 17-20 Input Register 00h

083Ch R/W GPIO_1_7_PU USB5734 GPIO 1-7 Pull-up Register 00h

083Dh R/W GPIO_8_11_PU USB5734 GPIO 8-11 Pull-up Register 00h

083Eh R/W GPIO_16_20_PU USB5734 GPIO 16-20 Pull-up Register 00h

0880h R/W GPIO_1_7_IN_EN USB5734 GPIO 1-7 Input Enable Register 00h



4.4 Register Definitions for USB5734

TABLE 14: USB5734 GPIO 1-7 PULL-DOWN REGISTER

GPIO_1_7_PD(082Ch)

GPIO 1-7 Pull-down Register

BIT Name R/W Description

7 GPIO_7_PD R/W Set bit to enable GPIO7 Pull-down resistor.







0 Reserved R Reserved


GPIO_8_11_PD(082Dh)



7:4 Reserved R Reserved






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GPIO_16_20_PD(082Eh)









TABLE 17: USB5734 GPIO 1-7 DIRECTION CONTROL REGISTER

GPIO_1_7_DIR(0830h)

GPIO 1-7 Direction Control Register


7 GPIO_7_DIR R/W Set bit to configure GPIO7 as an output.Clear bit to configure GPIO7 as an input.









GPIO_8_11_DIR(0831h)









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GPIO_16_20_DIR(0833h)









TABLE 20: USB5734 GPIO 1-7 OUTPUT REGISTER

GPIO_1_7_OUT(0834h)

GPIO 1-7 Output Register


7 GPIO_7_OUT R/W Access to the GPIO7 Output Register. Sets state of output pin.









GPIO_8_11_OUT(0835h)









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GPIO_16_20_OUT(0836h)









TABLE 23: USB5734 GPIO 1-7 INPUT REGISTER

GPIO_1_7_IN(0838h)

GPIO 1-7 Input Register


7 GPIO_7_IN R/W Access to the GPIO7 Input Register. Reads state of input pin.









GPIO_8_11_INP_BUF(0839h)









GPIO_17_20_INP_BUF(083Ah)










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TABLE 26: USB5734 GPIO 1-7 PULL-UP REGISTER

GPIO_1_7_PU(083Ch)

GPIO 1-7 Pull-up Register


7 GPIO_7_PU R/W Set bit to enable GPIO7 Pull-up resistor.









GPIO_8_11_PU(083Dh)









GPIO_16_20_PU(083Eh)










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TABLE 29: USB5734 GPIO 1-7 INPUT ENABLE REGISTER

GPIO_1_7_IN_EN(0880h)

GPIO 1-7 Input Enable Register


7 GPIO7_IN_EN R/W Set bit to configure GPIO7 as an input.






1 GPIO1_INP_EN R/W Set bit to configure PIO1 as an input.



GPIO_8_11_IN_EN(0881h)




3 GPIO_11_IN_EN R/W Set bit to configure GPIO11 as an input.





PIO_16_20_IN_EN(0882h)










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4.5 GPIO Configuration Register Map for USB58x/USB59xx

TABLE 32: USB58XX/USB59XX GPIO CONFIGURATION REGISTER MEMORY MAP

Addr. R/W Name Function Default

082Dh R/W GPIO_16_23_PD USB58xx/USB59xx GPIO 16-23 Pull-down Register 00h

082Eh R/W GPIO_8_12_PD USB58xx/USB59xx GPIO 8-12 Pull-down Register 00h

082Fh R/W GPIO_1_7_PD USB58xx/USB59xx GPIO 1-7 Pull-down Register 00h

0831h R/W GPIO_16_23_DIR USB58xx/USB59xx GPIO 16-23 Direction Control Register

00h


00h

0833h R/W GPIO_1_7_DIR USB58xx/USB59xx GPIO 1-7 Direction Control Reg-ister

00h

0835h R/W GPIO_16_23_OUT USB58xx/USB59xx GPIO 16-23 Output State Con-trol Register

00h

0836h R/W GPIO_8_12_OUT USB58xx/USB59xx GPIO 8-12 Output State Control Register

00h

0837h R/W GPIO_1_7_OUT USB58xx/USB59xx GPIO 1-7 Output State Control Register

00h

0839h R/W GPIO_16_23_IN USB58xx/USB59xx GPIO 16-23 Input State Read Register

00h

083Ah R/W GPIO_8_12_IN USB58xx/USB59xx GPIO 8-12 Input State Read Register

00h

083Bh R/W GPIO_1_7_IN USB58xx/USB59xx GPIO 1-7 Input State Read Reg-ister

00h

083Dh R/W GPIO_16_23_PU USB58xx/USB59xx GPIO 16-23 Pull-up Register 00h

083Eh R/W GPIO_8_12_PU USB58xx/USB59xx GPIO 8-12 Pull-up Register 00h

083Fh R/W GPIO_1_7_PU USB58xx/USB59xx GPIO 1-7 Pull-up Register 00h

096Eh R/W GPIO_72_PD USB58xx/USB59xx GPIO 72 Pull-down Register 00h

096Fh R/W GPIO_64_71_PD USB58xx/USB59xx GPIO 64-71 Pull-down Register 00h

0972h R/W GPIO_72_DIR USB58xx/USB59xx GPIO 72 Direction Control Reg-ister

00h


00h

0976h R/W GPIO_72_OUT USB58xx/USB59xx GPIO 72 Output State Control Register

00h

0977h R/W GPIO_64_71_OUT USB58xx/USB59xx GPIO 64-71 Output State Con-trol Register

00h

097Ah R/W GPIO_72_IN USB58xx/USB59xx GPIO 72 Input State Read Reg-ister

00h

097Bh R/W GPIO_64_71_IN USB58xx/USB59xx GPIO 64-71 Input State Read Register

00h

097Eh R/W GPIO_72_PU USB58xx/USB59xx GPIO 72 Pull-up Register 00h

097Fh R/W GPIO_64_71_PU USB58xx/USB59xx GPIO 64-71 Pull-up Register 00h


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4.6 Register Definitions for USB58x/USB59xx

TABLE 33: USB58XX/USB59XX GPIO 16-23 PULL-DOWN REGISTER

GPIO_16_23_PD(082Dh)












GPIO_8_12_PD(082Eh)




4 GPIO_12_PD R/W —






GPIO_1_7_PD(082Fh)












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TABLE 36: USB58XX/USB59XX GPIO 16-23 DIRECTION CONTROL REGISTER

GPIO_16_23_DIR(0831h)



7 GPIO_23_DIR R/W Set bit to configure GPIO16 as an output. Clear to set as Input.









GPIO_8_12_DIR(0832h)










GPIO_1_7_DIR(0833h)











TABLE 39: USB58XX/USB59XX GPIO 16-23 OUTPUT STATE CONTROL REGISTER

GPIO_16_23_OUT(0835h)

GPIO 16-23 Output State Control Register


7 GPIO_23_OUT R/W Sets the state of GPIO23 when configured as an output


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GPIO_8_12_OUT(0836h)










GPIO_1_7_OUT(0837h)











TABLE 42: USB58XX/USB59XX GPIO 16-23 INPUT STATE READ REGISTER

GPIO_16_23_IN(0839h)

GPIO 16-23 Input State Read Register


7 GPIO_23_IN R Reads back the state of GPIO23 when configured as an input




GPIO_16_23_OUT(0835h)




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GPIO_8_12_IN(083Ah)










GPIO_1_7_IN(083Bh)



7 GPIO_7_IN R/W Reads back the state of GPIO7 when configured as an input.




3 GPIO_3_IN R Reads back the state of GPIO3 when configured as an input.




TABLE 45: USB58XX/USB59XX GPIO 8-12 PULL-UP REGISTER

GPIO_16_23_PU(083Dh)











GPIO_16_23_IN(0839h)




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GPIO_8_12_PU(083Eh)










GPIO_1_7_PU(083Fh)











TABLE 48: USB58XX/USB59XX GPIO 72 PULL-DOWN REGISTER

GPIO_72_PD(096Eh)

GPIO 72 Pull-down Register





GPIO_64_71_PD(096Fh)






GPIO_16_23_PU(083Dh)




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TABLE 50: USB58XX/USB59XX GPIO 72 DIRECTION CONTROL REGISTER

GPIO_72_DIR(0972h)

GPIO 72 Direction Control Register





GPIO_64_71_DIR(0973h)











TABLE 52: USB58XX/USB59XX GPIO 72 OUTPUT STATE CONTROL REGISTER

GPIO_72_OUT(0976h)

GPIO 72 Output State Control Register





GPIO_64_71_OUT(0977h)






GPIO_64_71_PD(096Fh)




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TABLE 54: USB58XX/USB59XX GPIO 72 INPUT STATE READ REGISTER

GPIO_72_IN(097Ah)

GPIO 72 Input State Read Register





GPIO_64_71_IN(097Bh)











TABLE 56: USB58XX/USB59XX GPIO 72 PULL-UP REGISTER

GPIO_72_PU(097Fh)

GPIO 72 Pull-up Register



0 GPIO_72_PU R/W Set bit to enable GPIO72 Pull-up resistor


GPIO_64_71_PU(097Fh)






GPIO_64_71_OUT(0977h)




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GPIO_64_71_PU(097Fh)




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5.0 EXAMPLES

5.1 Read the Direction State of all GPIOs on USB5734 via USB Command

1. Command Phase (SETUP Transaction): Send the following SETUP Register Read Command to Endpoint 0 of the USB5734 Hub Feature Controller to read the contents of registers 0x830, 0x831, 0x832, and 0x833 which contain the direction control settings for all GPIOs. (See Table 58 and Figure 3.)

TABLE 58: REGISTER READ SETUP COMMAND EXAMPLE

SETUP Parameter Value Note

bmRequestType 0xC1 —

bRequest 0x04 —

wValue 0x0830 First register in a series of consecutive registers to read from

wIndex 0x0000 —

wLength 0x0004 Four consecutive registers are to be read.

FIGURE 3: REGISTER READ SETUP TRANSACTION EXAMPLE

2. Data Phase (IN Transaction): Hub Feature Controller sends the data bytes of length wLength starting from the specified address after receiving an IN packet. (See Figure 4.)

FIGURE 4: REGISTER READ IN TRANSACTION EXAMPLE

3. Status Phase (OUT Transaction): Host sends an OUT packet to complete the USB Transfer. Hub Feature Con-troller responds with a zero length data packet. (See Figure 5.)

FIGURE 5: REGISTER READ OUT TRANSACTION EXAMPLE


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5.2 Write Registers to Set GPIO10 as an output on the USB5734 via USB Command

1. Command Phase (SETUP Transaction): Send the following SETUP Register Write Command to Endpoint 0 of the USB5734 Hub Feature Controller to write the contents of registers 0x830, 0x831, 0x832, and 0x833 which contain the direction control settings for all GPIOs. In this example, GPIO10 will be set as an output, all other GPIOS will remain at the default input state. (See Table 59 and Figure 3.)

TABLE 59: REGISTER WRITE SETUP COMMAND EXAMPLE

Setup Parameter Value Note

bmRequestType 0x41 —

bRequest 0x03 —

wValue 0x0830 First register in a series of consecutive registers to write from.

wIndex 0x0000 —

wLength 0x0004 4 consecutive registers are to be read.

FIGURE 6: REGISTER WRITE SETUP TRANSACTION EXAMPLE

2. Data Phase (OUT Transaction): Host sends the four data bytes to set 0x830 = 0x00, 0x831 = 0x04, 0x832 = 0x00, and 0x833 = 0x00 from the specified address after sending the OUT packet. (See Figure 7.)

FIGURE 7: REGISTER WRITE OUT TRANSACTION EXAMPLE

3. Status Phase (OUT Transaction): Host sends an IN packet to complete the USB Transfer. Hub Feature Con-troller responds with a zero length data packet. (See Figure 8.)

FIGURE 8: REGISTER WRITE IN TRANSACTION EXAMPLE


AN1997

6.0 GPIO DEFAULT STATES

Many applications may require particular a default state (such as input with a pull-up or pull-down enabled, or output with drive high or drive low). If particular GPIO default states are required, these can be assigned to the pin via OTP configuration patch.

Use the following simplified guide to manually create an OTP patch.

Step 1. String together as many register WRITE_BYTE, SET_BIT, or CLEAR_BIT commands as required for the appli-cation. (See Table 60, Table 61, and Table 62.)

TABLE 60: WRITE_BYTE COMMAND

SET ADDRESS COMMAND

REGISTER ADDRESS

CMD LENGTH VALUE(S)

80h XXh XXh FEh 00h 01h XXh

The WRITE_BYTE command sets all bits within the register to the exact value selected.

TABLE 61: SET_BIT COMMAND

SET ADDRESS COMMAND

REGISTER ADDRESS

CMD LENGTH VALUE(S)


The SET_BIT command on works as a mask which sets the bits = 1 within the register, and leaves bits = 0 untouched.

The CLEAR_BIT command on works as a mask which clears the bits = 1 within the register, and leaves bits = 0 untouched.

TABLE 62: CLEAR_BIT COMMAND

SET ADDRESS COMMAND

REGISTER ADDRESS

CMD LENGTH VALUE(S)


Note: Refer to Microchip AN1903 Configuration Options for the USB5734 and USB5744 or Microchip AN2316 Configuration Options for the USB58xx and USB59xx for a more complete explanation of the OTP com-mand structures.

Step 2. Add one “FFh” byte at the end of all of the commands to terminate the sequence of commands.

Step 3. The patch can be saved in basic binary format with a ‘.cfg’ file extension

Step 4. Program configuration file to the hub using MPLAB Connect Configurator tools.

EXAMPLE 1: SET GPIO 1 TO OUTPUT AND DRIVE HIGH BY DEFAULT FOR USB5806

USB5806 GPIO1 Direction Register is 0833h and bit offset is 1. Use the SET_BIT command to ensure that other bits within the register are not affected.

80 08 33 FE 01 01 02

USB5806 GPIO1 Output Register is 0837h and bit offset is 1. Use the SET_BIT command to ensure that other bits within the register are not affected.

80 08 37 FE 01 01 02

Complete OTP Patch binary data:

80 08 33 FE 01 01 02 80 08 37 FE 01 01 02 FF

Note: The order of these two register commands is not critical; the end result is the same if they are reversed.


AN1997

7.0 GPIO CONTROL VIA SMBUS INTERFACE

GPIOs may be controlled from an embedded MCU/SoC through the hub SMBus slave interface. Note that the hub must be specifically configured to enable the SMBus slave interface; not all configuration modes have an available SMBus slave interface.

The GPIOs can be controlled in either the Configuration stage (SOC_CFG) or during the hub runtime stage, after issuing the AAh 56h 00h command within the SOC_CFG stage which instructs the hub to enter the active runtime stage with the SMBus slave interface still active. The SMBus address during SOC_CFG is 2Dh, while the address during runtime is 2Ch.

Note: OTP memory is loaded after the SOC_CFG stage, while the hub is transitioning into the runtime stage. Any changes made to registers will be over-written if those same registers are manipulated in OTP configura-tion.

Refer to Microchip AN1903 Configuration Options for the USB5734 and USB5744 or Microchip AN2316 Configuration Options for the USB58xx and USB59xx for a more complete explanation of the SMBus command structures.

EXAMPLE 2: USB5806 SET GPIO 1 TO OUTPUT AND DRIVE HIGH (DURING RUNTIME STAGE)Send ‘USB Attach with SMBus’ command to exit configuration stage and enter hub runtime stage

5A AA 56 00, Slave address 2Dh

GPIO1 Direction Register is 0833h and bit offset is 1.

58 00 00 05 00 01 08 33 02 // Write 0833h = 02h, Slave address 2Ch

58 99 37 00 // Register Access Command, Slave address 2Ch

GPIO1 Output Register is 0837h and bit offset is 1.



EXAMPLE 3: USB5806 SET GPIO 1 TO INPUT AND READ INPUT STATE (DURING RUNTIME STAGE)

Send ‘USB Attach with SMBus’ command to exit configuration stage and enter hub runtime stage

5A AA 56 00, Slave address 2Dh

GPIO1 Direction Register is 0833h and bit offset is 1.



GPIO1 Input Register is 083Bh and bit offset is 1.

58 00 00 04 01 01 08 3B // Read 083Bh, Slave address 2Ch


58 00 04 // Return value is placed in hub memory offset 00h 04h

59 80 XX // Read return value, Slave address 2Ch, Ignore the 80h Byte, XXh is the returned value.


AN1997

APPENDIX A: APPLICATION NOTE REVISION HISTORY

TABLE A-1: REVISION HISTORY

Revision Level & Date Section/Figure/Entry Correction

DS00001997C (1-10-19) All Added information on USB5807 throughout docu-ment.

Section 1.0 Minor clarification on the Hub Feature Controller usb device class within the text.

Table 2 “Total Available GPIOs” changed to “Maximum Available GPIOs”.

Table 4 to Table 10 Significant revision to tables adding more detail, additional options, and corrections.

Section 3.0 Revised entire section. All mentions of “ProTouch2” are changed to “MPLAB Connect”.

Section 6.0 Added (new content)

Section 7.0 Added (new content)

DS00001997B (12-07-16) All Fixed references to AN2316 Configuration Options for the USB58xx and USB59xx throughout.

Trademark and Sales Listing pages updated.

Updated minor formatting and grammar issues throughout.

DS00001997A (09-10-15) All Initial release.


AN1997

NOTES:


AN1997


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Note the following details of the code protection feature on Microchip devices:

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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

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QUALITYMANAGEMENTSYSTEMCERTIFIEDBYDNV

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an1997 usb-to-gpio bridging with microchip usb3.1 gen1 hubs application...

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