an3082 is2066b wireless stereo technology reference design application...

AN3082 IS2066B Wireless Stereo Technology Reference Design

Application Note

Introduction

This application note describes the reference design of Microchip IS2066B chip down base applicationwhich includes Bluetooth® Wireless Stereo Technology (WST) for earbud/headphone.

© 2019 Microchip Technology Inc. Application Note DS00003082A-page 1

Table of Contents

Introduction......................................................................................................................1

1. Hardware Guidelines................................................................................................. 41.1. Placement and Routing Guidelines..............................................................................................41.2. Power and Ground....................................................................................................................... 41.3. RF Traces and Components........................................................................................................ 41.4. Interference Guidelines................................................................................................................ 51.5. Antenna Guidelines......................................................................................................................51.6. Reference PCB............................................................................................................................ 51.7. Buck Layout Guide.......................................................................................................................61.8. Bypass Capacitor Placement and Routing...................................................................................91.9. Crystal Oscillator Routing and Placement..................................................................................101.10. Audio/Voice Interface Routing.................................................................................................... 111.11. Analog Microphone Inputs..........................................................................................................111.12. WST Earbud Block Diagram...................................................................................................... 121.13. Charger Box Block Diagram.......................................................................................................141.14. Auto Embedded Mode Description.............................................................................................151.15. Manual Embedded Mode Description........................................................................................ 151.16. Host MCU Mode Description......................................................................................................151.17. General Purpose Input Output................................................................................................... 151.18. IS2066B Power Tree.................................................................................................................. 161.19. Conductive RF Measurement Setup.......................................................................................... 16

2. Antenna Note...........................................................................................................182.1. Antenna Return Loss..................................................................................................................182.2. Antenna Placement....................................................................................................................19

3. Reference Circuit.....................................................................................................20

4. Mass Production Test Board Design....................................................................... 234.1. MP Tool Flow for IS2066B..........................................................................................................234.2. MPBT DUT Test Board Design...................................................................................................244.3. MPMF 1X2 Fixture..................................................................................................................... 28

5. Appendix A - Edgar III Board Circuit........................................................................32

6. Document Revision History..................................................................................... 33

The Microchip Web Site................................................................................................ 34

Customer Change Notification Service..........................................................................34

Customer Support......................................................................................................... 34

Microchip Devices Code Protection Feature................................................................. 34

Legal Notice...................................................................................................................35

AN3082


Trademarks................................................................................................................... 35

Quality Management System Certified by DNV.............................................................36

Worldwide Sales and Service........................................................................................37

AN3082


1. Hardware GuidelinesThis section provides hardware guidelines to achieve the best performance.

1.1 Placement and Routing GuidelinesTo achieve the best RF performance, ensure the following recommendations are followed:

• The board must have a solid ground plane. The center ground pad of the device must be firmlyconnected to the inner layer ground plane by using vias.

• It is recommended to use four or more layer PCB.• To avoid electromagnetic field blocking, keep the antenna on the board at a safe distance from large

metal objects.• Do not enclose the PCB antenna within metal shielding.• Keep any components which radiate noise or signals within the 2.4 GHz to 2.5 GHz frequency band

far away from the antenna, or better, shield those components. Any radiated noise from the mainboard in this frequency band degrades the sensitivity of the system.

1.2 Power and GroundOne inner layer is suggested as a ground plane. Make sure that the ground layer does not get broken byrouting. Power can run on all layers except the ground layer. Power rails must be widened to ensure thelowest inductance and resistance. The power pins of the core IC must have a via direct connect to thepower plane as close to the pin as possible. Decoupling capacitors must have a via right next to thecapacitor pin and this via must go directly down to the power plane; that is, the capacitor must not routeto the power plane through a long trace. The ground side of the decoupling capacitor must have a viaright next to the pad, which goes directly down to the ground plane. Each decoupling capacitor must haveits own via directly to the ground plane and power plane right next to the pad. The decoupling capacitorsmust be placed as close to the pin for filtering.

1.3 RF Traces and ComponentsThe RF traces from the RF_RTX pin of the IS2066B to the antenna must be 50 Ohm controlledimpedance trace. The recommended routing and placement for the RF section layout design (RF_RTXconnections) is shown on the reference design layout. These controlled impedance traces must referencea ground plane on a lower layer and to be adjusted, depending on the dielectric and copper weight used.No other traces must route through the RF area on layers between the RF traces and the groundreference plane. Do not route any other traces in the RF area on any layer. This ground reference planemust extend entirely under the tuner.

Be sure to add as many ground vias as possible. Connect all the ground layers together (groundstitching) along the RF traces and throughout the area where the RF traces are routed. Add at least twoground vias for every ground pad around the RF components. Place all the ground vias along the RFtraces on either side.

Connect the center ground pad of the IS2066B to the inner ground layer, using at least four vias, withpreferably one via per one ground ball and putting it close to the ground ball. The ground path going fromthe ground pad down to the ground plane must be as low impedance as possible.

AN3082Hardware Guidelines


Do not use thermal relief pads for the ground pads of all components in the RF path. These componentpads must be filled with the ground copper.

Ensure that the trace from the antenna to IS2066B is as short as possible and is completely isolated fromall other signals on the board. No signals must route under this trace on any layer of the board. Ensurethat all the digital signals which are toggled are placed away from the antenna when IS2066B is active.The digital signals must not be placed near the antenna. All the digital components and switchingregulators on the board must be shielded to avoid the noise generated by the antenna.

1.4 Interference GuidelinesThe interference affects the RF receiver performance on the board radiating noise into the antenna orcoupling into the RF traces.

• Ensure that there is no noise circuit placed anywhere near the antenna or the RF traces. All the noisegenerating circuits must be shielded, therefore, they do not radiate noise that is picked up by theantenna.

• Ensure that no traces are routed underneath the RF portion of IS2066B input.• Ensure that no traces route underneath the RF traces from the antenna to the IS2066B. This applies

to all layers.• Even if there is a ground plane on a layer between the RF route and another signal, the ground

return current flows on the ground plane and couples into the RF traces.

1.5 Antenna GuidelinesTo achieve the best RF performance, ensure the following recommendations are followed:

• Be sure to choose an antenna that covers the frequency band between 2.4 GHz to 2.5 GHz.• Ensure that the PCB pad of the antenna is connected and designed with 50 Ohm impedance. The

antenna vendor must specify the pad dimensions, the spacing from the pad to the ground referenceplane, and the spacing from the edges of the pad to the ground fill on the same layer as the pad.Since the ground reference plane for the 50 Ohm trace is connected from the antenna pad toIS2066B, it may be on a different layer than the ground reference for the antenna pad. Ensure thatthe pad design contains a proper transition from the pad to the 50 Ohm trace.

• Ensure that the antenna matching components are placed as close to the antenna pad as possible.The antenna cannot be matched if the matching components are placed far away from the antenna.

1.6 Reference PCBThe recommended Printed Circuit Board (PCB) for four layer is 0.8 mm of PCB thickness is illustrated inthe following table.

Table 1-1. PCB Making Specification

Parameter Value

SM solder mask 0.01 mil

Top Cu+Plating 1 OZ/1.4 mil

Prepreg FR4 8.8mils



...........continuedParameter Value

Metal 1 1 OZ/1.4 mil

Core 2 Substrate FR4 8.8 mil (adjustable based on total thickness)

Metal 2 1 OZ/1.4 mil

Prepreg FR4 8.8 mil

Bottom Cu+Plating 1 OZ/1.4 mil

SM solder mask 0.01 mil

Total thickness 31.4mils = 0.8mm

1. FR4, four layers, PCB thickness is 0.8 mm2. 2.4 GHz top layer and bottom layer with 50 Ohm Trace width is 6 mil3. 2.4 GHz top layer and bottom layer with 50 Ohm Gap width is 6 mil

1.7 Buck Layout GuideTo achieve the best Buck output voltage performance, ensure that the following recommendations arefollowed:

• The inductor and capacitor of the Buck circuit must be placed in the same layer and close toIS2066B.

• Buck trace width must be at least 10 mils.• Buck Input: Refer to Figure 1-1 and Figure 1-2. Place the buck input capacitance C27 and C25 as

close as possible to pin C9 (SYS_PWR) and F4 (SYS_PWR). The buck input routing path sequenceis from SYS_PWR to C27 and C25, then connect C27 and C25 to pin C9 and F4 respectively. Do notconnect SYS_PWR directly to pin C9 and F4 without connecting with the capacitor.

• Buck Output: Refer to Figure 1-1 and Figure 1-2. Pin E9 (BK2_O) as example, the buck outputrouting path sequence is BK2_LX, L3, C16, BK2_O and must be as short as possible. Trace of buckoutput to load must be connected from C16.

• Keep no ground trace under inductor L4 and L3 on top layer.• Place the solid ground plane on the second layer. The ground path from C16 and C26 to IS2066B

ground C4-6 and D4-6 must be short and direct without interruption by other traces. The capacitorsC16 and C26 must be connected to a ground plane through ground vias to reduce the groundimpedance.



Figure 1-1. Recommended Buck Layout Scheme



Figure 1-2. Recommended Routing and Placement of Buck Circuit

GND C27

L3

C16

C26

L4

C25

To ensure the Buck output voltage quality, the wire wound coil high current inductor is recommended forBuck inductor. The following figure is an example considered from Taiyo. The 10 uH wire wound inductor(CBMF1608T100K) with high IDC and low DCR are recommended.Note: Multi-layer Ceramic Inductor (MLCI) is not recommended to use as L10 inductor, as it may notstart the chip stably. Also, the poor yield rate affects the quality of voltage.



Figure 1-3. 10uH Wire Wound Inductor Example

1.8 Bypass Capacitor Placement and RoutingThe bypass capacitor on the power tree trace of IS2066B must be placed close to the input or output pin,as the red marked parts show in the following figure.



Figure 1-4. Bypass Capacitor Placement on the Power Tree

1.9 Crystal Oscillator Routing and PlacementTo achieve low noise and frequency precision, follow the crystal oscillator layout placement guidelines aslisted below:

1. The crystal trace (XO_N & XO_P) must be as short as possible and the width must be wider than 7mils.

2. The ground plane at the ground layer must larger than the crystal size and the external loadcapacitor’s ground must be connected to ground plane through vias directly.

3. The external load capacitors must be placed as close as possible to the crystal.



Figure 1-5. Recommended Routing and Placement of Crystal Oscillator

1.10 Audio/Voice Interface RoutingFor capless analogy audio interface layout, the following rules ensure better audio noise rejection.

• Width of each trace and the gap must be >5 mil.• The gap of each trace must be 1W width.• The clearance of AOHPL and AO HPR with parallel running trace should be a must as possible.

Figure 1-6. PCB Routing for Capless Speaker Output

1.11 Analog Microphone InputsThe following figure explains the differential microphone input circuit and the placement rules are listed asbelow:

• The DC blocking capacitors (C9 and C11) are placed as close as possible to IS2066B.• The MIC_BIAS filtering components (C6 and R12) are placed close to the microphone.



• The microphone and signal paths of microphone must be routed on same layer.• The component on differential path (MICP1 and MICN1) must be placed close to each other to

reduce common mode noise.Note: If single microphone unit is used, please refer to the datasheet from the microphonemanufacturer for the R12 resistance value.Connect MIC+ with microphone positive side and MIC- to microphone ground.

Figure 1-7. Reference Analogy Microphone Inputs Schematic and PCB Routing

1.12 WST Earbud Block DiagramThe following is the WST earbud block diagram:



Figure 1-8. WST Earbud Block Diagram

1.12.1 WST Earbud Features• Pairing

– Simplified pairing process– Automatic pairing to sniffing device (option)

• A2DP Mode– Switch between L/R or L+R audio– AAC support

• HSP/HFP Mode (Phone call) – TWS voice– Switchable microphone between primary and secondary unit– Perform Voice Sync between primary and secondary

• Link Loss Management– Out-of-range or no power management

• Continuous Talk Mode– Allows customer to use one earbud at a time– Call transfer from active unit to idle unit– Allows continuous talk time extension– UI Tool selection option



1.13 Charger Box Block DiagramThe following is the charger box block diagram:

Figure 1-9. Charger Box Block Diagram

1.13.1 Charger Box Features• Earbud detection with two charging ports• Only two charging point per earbud• Auto power-on with earbud in-box detection• Charge internal battery through USB

Note: 1. It is recommended to follow reference design charging box circuit for charging box design of WST

earbud. The charging input power turns off automatically after the charging completes (low currentdetection).

2. For IS2066B, configure a shorter "charge complete delay off time” than the charging box lowcurrent detection off time. This helps to maintain the correct in-out box behavior.

3. Reference charger box solution is implemented with IP5305-DE-3. The particular part is able todetect loading current at 6~8mA to shut down 5V output to IS2066B.For the detailed charging profile of IS2066B, see the IS2066B datasheet.



1.14 Auto Embedded Mode DescriptionThe Embedded mode is defined to improve the user experience by reducing the number of operations onthe manual press button with additional design requirements on the charging box.

• Earbud – auto power on and reconnected to peer earbud when the charging box is opened, andearbud(s) are taken out. Earbuds parked in the charging box exchange information and then startcharging until charging is completed, then turn off. Three manual buttons are defined. These threebuttons can be configured with multiple functions: MFB for ON, OFF, play, pause, pick up call, endcall function, and microphone select. There are two buttons for vol+/FF and vol-/REV.

• Charging box – requires an additional feature that the 5V on charging port must be available whenthe charging box is opened.

1.15 Manual Embedded Mode DescriptionThe Manual Embedded mode has similar features of the Auto mode except the following:

• Earbud turn on/off using the press button• Charging box does not require an additional feature

1.16 Host MCU Mode DescriptionThis mode is designed to implement features which cannot be achieved on IS2066B Auto/ManualEmbedded mode, such as advanced handover behavior, BLE communication with a mobile application orother device, and connections to the external sensor.

1.17 General Purpose Input OutputThe following table explains General Purpose Input Output (GPIO) pin names and their functions.

Table 1-2. GPIO Pin Description

Pin Name Pin Description

MFB

• Multi-function button (Btn 0) and power-on key

• UART RX_IND, active-high (used by host MCU to wake up the Bluetoothsystem)

P1_3 EEPROM SDA: EEPROM slave data, external 4.7k pull-up resistor is needed

P1_5 Out_Ind_1 (UART_TX_IND)

P0_0 Optional in-out box detection

P0_3 Optional charging completed event

P0_2 Button configuration

P2_0 System configuration for Test mode and Application mode

P2_7 Button configuration



1.18 IS2066B Power TreeThe following is the IS2066B Power Tree diagram:

Figure 1-10. IS2066B Power Tree

1.19 Conductive RF Measurement SetupThis section describes the Conductive RF test procedure of hardware and the tool setting.

1.19.1 Hardware Test Connection1. Remove the antenna matching and solder RF coaxial cable from RF test point.2. Connect the test interface of IS2066B DUT (ADAP_IN, VBAT, GND, HCI_TX, HCI_RX and P2_0) to

Edgar III board (USB to UART Converter Board) (5V, BAT, GND, HTX, HRX and P2_0). See thefollowing figure.

3. Connect the Edgar III to the PC USB port and connect the DUT to the RF Tester.4. Set the P2_0 of SW1 to ON on Edgar III (P3_4 of DUT pull low).

Note: Refer to the Figure 5-1 for the Edgar III board circuit, customer can contact a Microchip FAEfor getting Edgar III boards.

Figure 1-11. RF Test Mode Connection

5. Use the ISRT tool to configure the RF test parameter.6. Test using the RF equipment and verify RF Tx/Rx performance.



1.19.2 ISRT Tool Test ProcedureThe ISRT tool is generally used for regulatory approval such as Bluetooth SIG/QDID, FCC ID, CE and soon. For more details on the ISRT tool setup procedure, refer to the ISRT User Manual in the ISRTpackage details: https://www.microchip.com/wwwproducts/en/IS2066



https://www.microchip.com/wwwproducts/en/IS2066

2. Antenna Note

2.1 Antenna Return LossFor stable antenna performance, it is suggested the antenna matching circuit must achieve the curve ofAntenna S11 < -10 dB from 2402 MHz to 2480 MHz. The following figures illustrate the return loss ofantenna (S11) and the criteria.

Figure 2-1. Suggested Antenna Return Loss from 2402 MHz to 2480 MHz (Left Side Earbud)

Figure 2-2. Suggested Antenna Return Loss from 2402 MHz to 2480 MHz (Right Side Earbud)

AN3082Antenna Note


2.2 Antenna PlacementThe following figure shows the antenna placement.Figure 2-3. Antenna Placement

AN3082Antenna Note


3. Reference CircuitThe following figures illustrate the reference schematics of the IS2066B with MCU Audio Bluetooth WSTearbud and charging box Reference Circuit.

Figure 3-1. IS2066B with MCU Audio Bluetooth WST Earbud Reference Circuit (Right)

1UF

6V3 0201

C13GND

MICNMICPMICBIAS

1UF6V3

0201

C14GND 1V2

P1_31UF6V3 0201

C15RST_NP1_5HCI_RXDHCI_TXD

GND

1UF6V30201

C27 1UF6V30201

C22

GND

1UF6V30201

C23

GND

SYS_

PWR

ADAP

_IN

1UF6V30201

C24

GND

BAT_

INAM

B_DE

T

GND

SYS_

PWR

GND

BK1_

OUT

GND

1K02011%

R24

GND

MFB

LED2

LED1

P0_0P0_3

1UF6V30201

C17

GND

1V2

1UF6V30201

C18

GND

RFLDO_O

1UF6V30201

C19

GND

1UF6V30201

C20

GND

VBGULPC_VSUS

8pF

50V 0201

C12

8pF

50V 0201

C10GND

GND

GND

1UF

6V3 0201C8

GND

RFLD

O_O

TP PAD PCB 1mm

TP20

1UF6V30201

C2

GND

P0_2

P2_0

P2_7

VDDI

O

1UF

6V3 0201C7

GND

RFTR

X

CODE

C_V

GND

4K702011%

R19

AOHP

RAO

HPM

AOHP

L

XOP

TP PAD PCB 1mm

TP2

Audio Output

L

SYS_PWR

MFB

Red

D8

Blue

D7

LED2

LED1

GND

DNP16V 0201C11

100nF16V 0201C9

MICP

MICN

4U7F6V3

0201C6

GND

MICBIAS

TP PAD PCB 1mm

TP12

TP PAD PCB 1mm

TP14

TP PAD PCB 1mm

TP16

TP PAD PCB 1mm

TP18

P2_0

UPDI

HCI_TXD

HCI_RXD

TP PAD PCB 1mm

TP10ADAP_IN_5V

TEST POINTS

0R02011%

R18

MIC

TP PAD PCB 1mm

TP19

TP PAD PCB 1mm

TP21GND

BAT_IN BAT+

BAT-

ADAP_IN

P2_0

UPDI

TX

RX

GND

CX2016 16MHz

Y1

SYS_PWR

GND

1UF6V30201

C25

GND

2.2K02011%

R13

TP PAD PCB 1mm

TP3

TP PAD PCB 1mm

TP5

MICP

MICN

10uF6.3V0402

C26

TP PAD PCB 1mm

TP1R

4U7F6.3V0201

C21

LXES03TAA1-142D1

12 4

5

36 LXES0ND

GND

GND

ADAP_IN_5V

VSS

GND

ADAP_IN

DNP50V0201

C4

3.3nH

0201L2

GND

6p8F50V0201

C1

GND

1.5pF50V0201

C5

TP PAD PCB 1mm

RFTP1

ANT

6p8F

0201L1

DNP50V0201

C3

GND

CODEC_VO

VDDI

O

BK2_LXSYS_PWRBK2_O

BK1_

LX

GND

10uF6.3V0402

C16

0R0201 1%

R21

DNP0201 1%

R22

DNP

R23

CODEC_VBK2_O

BK1_OUT

CODEC_VO

Feed1 2 23.2x1.6mm_ANT

*1

GND

TP PAD PCB 1mm

TP9BK2_O

GNDC4GNDC5GNDC6

VCOMD2MICN1C1MICP1D1MIC_BIASE2VDD_COREE3P1_3B7RST_NE4P1_5B8HCI_RXDB2HCI_TXDC2

GNDD4GNDD5GNDD6

VDDA

A3

AOHPL

B1

AOHPM

A1

AOHPR

A2

VDD_IO

E1P2_7

B4

P2_0

E5P0_2

B5

RF_RTX

A6

VCC

_RF

A7

XO_P

A8

XO_N

A9

ULPC_VSUS B3VBG A4

RFLDO_O B9CLDO_O A5BK2_LX D9

BK2_VDD C9BK2_O E9P0_3 C8P0_0 B6

CODEC_VO F9

LDO31_V

INF8

LDO31_V

OF7

ADAP_IN

F1BAT_IN

F2AMB_D

ETE6

SYS_PW

RF3

BK1_VDD

F4BK1_LX

F5BK1_O

F6LE

D1

E7LE

D2

E8MFB

D8

U1

IS2066B

SYS_PWR

VDDIO

GND

VCOM

XON

TP PAD PCB 1mm

TP11RFLDO_O

TP PAD PCB 1mm

TP13CODEC_VO

TP PAD PCB 1mm

TP15MFB

TP PAD PCB 1mm

TP17VDDIO

TP PAD PCB 1mm

TP8RST_NTP PAD PCB 1mm

TP7BK1_OUT

2

1 3

4

SW1

1K0201 1%

R8

330201 1%

R2

10K0201 1%

R3

AT_PA2

AT_PA1

AT_PC3 RST_N

HCI_RXD

HCI_TXD

MFB

P0_0

330201 1%

R4AT_PB3

P1_5

330201 1%

R5AT_PB2

1K0201 1%

R6AT_PB1

47K0201 1%

R9AT_PA7

1K0201 1%

R11AT_PA5

1K0201 1%

R10AT_PA6

KEY_X

1K0201 1%

R12AT_PA3

KEY_Y

P2_0

ADAP_IN

1K0201 1%

R15AT_PC1 P0_3

TP PAD PCB 1mm

TP6TP PAD PCB 1mm

TP4KEY_X

KEY_Y

100K0201 1%

R16

DNP0201 1%

R17

BAT_IN

GND

PA21PA32GND3VDD4PA45

PA5

6PA

67

PA7

8PB

59

PB4

10

PB3 11PB2 12PB1 13PB0 14PC0 15PC

116

PC2

17PC

318

PA0

19PA

120 ATtiny1616

BAT_IN_MCU

AT_PC0AT_PB0AT_PB1AT_PB2AT_PB3

AT_P

B4AT

_PB5

AT_P

A7AT

_PA6

AT_P

A5

AT_PA4

AT_PA3AT_PA2

AT_P

A1

AT_P

C3AT

_PC2

AT_P

C1UPDI

GND

BAT_IN_MCU BAT_IN

0R0201

R14

10uH

L4

10uH

L3

3K302011%

R20

0R040250mOhm

R7

0R040250mOhm

R1

LXES03TAA1-142D3

LXES03TAA1-142D6

LXES03TAA1-142D10

LXES03TAA1-142D9

LXES03TAA1-142D2

LXES03TAA1-142D4

LXES03TAA1-142D5

GND

GND

GND

GND

GND

GND

GND

AN3082Reference Circuit


Figure 3-2. IS2066B with MCU Audio Bluetooth WST Earbud Reference Circuit (Left)



Figure 3-3. IS2066B with MCU Audio Bluetooth WST Earbud Reference Circuit (Charging Box)



4. Mass Production Test Board DesignThis chapter describes the Mass Production Board Level Test (MPBT) and Mass Production Multi Flash(MPMF) Test fixture hardware design. For more details on Mass Production (MP) tools in MP tool releasepackage, refer to the MP Tool User Guide.

MPBT: Mass Production Board level Test (PCBA level calibration and testing)

MPET: Mass Production EEPROM Tool (EEPROM programming file merging)

MPSE: Mass Production Script Editor (test items and limits configuration)

MPMF: Mass Production Multi Flash (memory gang programming)

4.1 MP Tool Flow for IS2066BThe following figure explains the work-flow of MP tool for IS2066B.

Figure 4-1. MP Tool Flow - IS2066B

AN3082Mass Production Test Board Design


Figure 4-2. MP Test Flow - IS2066B

The following MP tools for IS2066B are used for testing:• MPBT

– Digital testing (GPIO, EEPROM programming, system)– PMU calibration and testing– RF calibration and testing– Audio testing (functional)

• MPMF– L and R pairing record preprogramming– EEPROM programming– BD address programming

• MPSE – Production script and test items configuration• MPET – EEPROM merge tool

4.2 MPBT DUT Test Board DesignThe IS2066B MPBT test includes the following items:

Table 4-1. IS2066B MPBT Test

Design Under Test Test Pin Note

GPIO P1_3, P1_5, P0_0, P0_3,P0_2, P2_0, P2_7,HCI_RXD, HCI_TXD

GPIO Open/Short Test

PMU CLDO_O, LDO31_VO,BK2_O, VCC_RF, BK1_O,BAT_IN, ADAP_IN

Power Measurement and Calibration



...........continuedDesign Under Test Test Pin Note

RF Test RTX (RF test point onmatching path)

Use RF test probe fixed on PCB, contact theRF test point and ground during test

RF Antenna must be bypassed or shieldedduring test

Audio AOHPR, AOHPL, MICP1,MICN1

Analog Speaker Output, MIC Input

LED LED1 and LED2 LED1 (Blue) and LED2 (Red)

Figure 4-3. IS2066B DUT MPBT Test Board Circuit (R Earbud)

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

B B

A A

P2_0

MIC1+

HCI_RXDHCI_TXD

MFB

MIC1- LOUT+

AIRAILROUT+

P2_0

ROUT+

MIC1+

MIC1-

AIL

RST

LOUT+ MFB

HCI_TXD

HCI_RXD

MFB

RST

AIR

AIL MIC1+MIC1-

UPDI

UPDI

2 1

D19SPE0572

C1410u/16V

C30.1u/16V

TP2RF-PB2

21

D5SPE1211

2 1

D15SPE0572

2 1

D11SPE0572

12

C910u/16V

12

JP1JP 1x2

2 1

D18SPE0572

2 1

D28SPE0572

TOP KEEPOUT AREA

TOP&BOT KEEPOUT AREA

TOP KEEPOUT AREA

COMPONENT AREA

G3

G4

G1

G2

PCB1SLT-BOARD

2 1

D24SPE0572

2 1

D29SPE0572

C151u/16V

135

246

J2JP 2x3

C410u/16V

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

CON1JP 2x20

C5NP-0402

12

34

SW1SW-TACT

2 1

D21SPE0572

2 1

D7SPE0572

2 1

D20SPE0572

2 1

D25SPE0572

C10.1u/16V

2 1

D23SPE0572

C710u/16V

2 1

D35SPE0572

1 2

3 4

SW3SW-TACT

2 1

D8SPE0572

C80.1u/16V

C210u/16V

2 1

D14SPE0572

MIC_NTP5MIC_PTP3GNDTP20HCI_RXDTP18HCI_TXDTP16VSSVIAADAP_IN_5VTP10

RST_N TP8AOHPLTP2AOHPRTP1BAT_INTP19UPDITP14GNDTP21

MFB TP15P20TP12

RFTP1 RFTP1

RFLDO_O TP11BK2_O TP9VDDIO TP17

CODEC_VO TP13BK1_OUT TP7

PCB3

FP-IS2066B_R

C610u/16V

135791113

2468101214

J3JP 2x7

C161u/16V

2 1

D4SPE0572

BK2_O

CODEC_VO

ADAP

BAT_IN

BK1_OUTVDD_IO

BK1_OUT

CODEC_VO

VDD_IO

BAT_IN

ADAP

BK1_OUT

BK2_ORFLDO_O

RFLDO_O

CODEC_VOVDD_IO

ADAP

BAT_IN

BAT_IN

RFLDO_O

BK2_O

BAT_IN

ADAP

BAT_IN

VICTORIA INTERFACE(Bottom layer)

SLTBoard

3V3_LDO

VOL3

BK1_OUT

VDD_IO

VOL1

IS2066B_R mapping VICTORIA interface

BK2_O BUCK_LDO

CODEC_VO

MFB P36

IS2066B_R VICTORIA

0805

For MCU update interface(TOP layer)

(1V5)

(1V8)

0603

0603

0603 0805

0603 08050805 0402

0805

RFLDO_O BOOST

ESD diode(Bottom layer)

Button(TOP layer)

IS2066B_R(TOP layer)

RF TP(Bottom layer)

IS2066B_R interface for test(TOP layer)

P2_0

HCI_TXDHCI_RXDMIC1+

MIC1- LOUT+ROUT+

MFB

HCI_RXDHCI_TXD

ROUT+LOUT+P2_0

MFBRSTUPDI



Figure 4-4. IS2066B DUT MPBT Test Board Circuit (L Earbud)

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

B B

A A

P2_0

MIC1+

HCI_RXDHCI_TXD

MFB

MIC1- LOUT+

AIRAILROUT+

P2_0

ROUT+

MIC1+

MIC1-

AIL

RST

LOUT+ MFB

HCI_TXD

HCI_RXD

MFB

RST

AIR

AIL MIC1+MIC1-

UPDI

UPDI

2 1

D19SPE0572

C1410u/16V

C30.1u/16V

TP2RF-PB2

21

D5SPE1211

2 1

D15SPE0572

2 1

D11SPE0572

12

C910u/16V

12

JP1JP 1x2

2 1

D18SPE0572

2 1

D28SPE0572

TOP KEEPOUT AREA

TOP&BOT KEEPOUT AREA

TOP KEEPOUT AREA

COMPONENT AREA

G3

G4

G1

G2

PCB1SLT-BOARD

2 1

D24SPE0572

2 1

D29SPE0572

C151u/16V

135

246

J2JP 2x3

C410u/16V

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

CON1JP 2x20

C5NP-0402

12

34

SW1SW-TACT

2 1

D21SPE0572

2 1

D7SPE0572

2 1

D20SPE0572

2 1

D25SPE0572

C10.1u/16V

2 1

D23SPE0572

C710u/16V

2 1

D35SPE0572

1 2

3 4

SW3SW-TACT

2 1

D8SPE0572

C80.1u/16V

C210u/16V

2 1

D14SPE0572

MIC_NTP5MIC_PTP3GNDTP20HCI_RXDTP18HCI_TXDTP16VSSVIAADAP_IN_5VTP10

RST_N TP8AOHPLTP2AOHPRTP1BAT_INTP19UPDITP14GNDTP21

MFB TP15P20TP12

RFTP1 RFTP1

RFLDO_O TP11BK2_O TP9VDDIO TP17

CODEC_VO TP13BK1_OUT TP7

PCB3

FP-IS2066B_R

C610u/16V

135791113

2468101214

J3JP 2x7

C161u/16V

2 1

D4SPE0572

BK2_O

CODEC_VO

ADAP

BAT_IN

BK1_OUTVDD_IO

BK1_OUT

CODEC_VO

VDD_IO

BAT_IN

ADAP

BK1_OUT

BK2_ORFLDO_O

RFLDO_O

CODEC_VOVDD_IO

ADAP

BAT_IN

BAT_IN

RFLDO_O

BK2_O

BAT_IN

ADAP

BAT_IN

VICTORIA INTERFACE(Bottom layer)

SLTBoard

3V3_LDO

VOL3

BK1_OUT

VDD_IO

VOL1

IS2066B_R mapping VICTORIA interface

BK2_O BUCK_LDO

CODEC_VO

MFB P36

IS2066B_R VICTORIA

0805

For MCU update interface(TOP layer)

(1V5)

(1V8)

0603

0603

0603 0805

0603 08050805 0402

0805

RFLDO_O BOOST

ESD diode(Bottom layer)

Button(TOP layer)

IS2066B_L(TOP layer)

RF TP(Bottom layer)

IS2066B_R interface for test(TOP layer)

P2_0

HCI_TXDHCI_RXDMIC1+

MIC1- LOUT+ROUT+

MFB

HCI_RXDHCI_TXD

ROUT+LOUT+P2_0

MFBRSTUPDI

Figure 4-5. MPBT 1x1 Test Fixture Connection Diagram



The following figure illustrates MPBT Test Fixture that includes DUT test board PCB, Socket, Victoriaboard (AC102013) and RF test equipment.

Note: AC102013 can be ordered from the Microchip website directly.

Figure 4-6. MPBT Test Fixture Example

During testing, the antenna shield copper paper is used to minimize the RF power leakage to antennapath.



Figure 4-7. DUT Socket RF Test Probe and Shielding

4.3 MPMF 1X2 FixtureThe following images are the IS2066B DUT MPMF 1x2 test board circuit and MPMF 1x2 test fixtureconnection diagram.



Figure 4-8. IS2066B DUT MPMF 1x2 Test Board Circuit5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ROM APP1/P2_0OFF

The BAT_IN_1 output 4.1V

5V ADAPTERExternal 3V3

The BAT_IN_2 output 4.1V

5V ADAP LED

When the BAT_IN_2 output > 3.6V, ADAP_IN_2 will output 5V.

When the BAT_IN_1 output > 3.6V, ADAP_IN_1 will output 5V.

BAT_IN Power

ONROM IBDK

Control the P20 to High or Low

0805 0402

08050805 0603

0603

0805

08050603

0603

08050805

08050603

0603

08050805

0603

0402 0402 0402 0402

08050805

0603

0805 0805

0603

0603 0603

ADAP_IN Power

For decice 0 For device 1

For decice 0 For device 1

For device 1For device 0

PCB View

BAT_IN_1

EXT_3V3

ADAP_5V

ADAP_5V

EXT_3V3

ADAP_5V

ADAP_5V

BAT_IN_2

ADAP_IN_2ADAP_IN_1

BAT_IN_1 BAT_IN_2

ADAP_5V ADAP_5V

P20_1 P20_2

Board Name

Size Title Rev

Date: Sheet o f

P/N

Power / mode switch 1.0

IS2066B_L_and_R_JIG

B

1 3Thursday, May 02, 2019

????

5F, No.5, Industry E. Rd. VII, Hsinchu Science Park,Hsinchu City 30078, TaiwanTEL. 886-3-5778385

Board Name

Size Title Rev

Date: Sheet o f

P/N


IS2066B_L_and_R_JIG

B


????


Board Name

Size Title Rev

Date: Sheet o f

P/N


IS2066B_L_and_R_JIG

B


????


TOP KEEPOUT!!

TOP & BOTTOM KEEPOUT AREA

2 module AreaTOP KEEPOUT !!

Only Top Component Area

Component Area

Component

Area

Only Top

Only Top

BottomComponent Area

BottomComponent Area

Component AreaOnly Bottom

Component AreaOnly Bottom

PCB1Fixture Board_1X4

NC

D2LED-Y-1

12

Q1STS2306

312

C110u/16V

R620K/1%

12

C510u/16V

U2RT9179PB

VIN1

EN3

ADJ4

VOUT5

GND2

D1SPE1211

21

C810u/16V

C1710u/16V

R670

1 2

R221K5

1 2

R2110K/1%

12

R520K/1%

12

C1410u/16V

SW1PT-S1

1 2 3

U6RT9167A-50PB

VIN1

EN3

BP4

VOUT5

GND2

C220.01u/16V

U1RT9179PB

VIN1

EN3

ADJ4

VOUT5

GND2

U7RT9167A-50PB

VIN1

EN3

BP4

VOUT5

GND2

R1100/1%

1 2

ONSW1SW-1BIT

1 2

C610u/16V

R139K1/1%

1 2

C710u/16V

C40.1u/16V

R21K/1%

12

C1810u/16V

+ C3100u/25V

12

R660

1 2

R318K/1%

12

R231K5

1 2

R146K8/1%

1 2

R166K8/1%

1 2

C210u/16V

C1310u/16V

C210.01u/16V

R410K/1%

12

Q2STS2306

312

R159K1/1%

1 2

P1DC-JACK

1

2

3

U3RT9179PB

VIN1

EN3

ADJ4

VOUT5

GND2

R98K2/1%

12

R108K2/1%

12



5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Device 0 (IS2066B_R)

Device 1 (IS2066B_L)

VDD_IO_1

ADAP_IN_1

BAT_IN_1

BAT_IN_1ADAP_IN_1

VDD_IO_1

ADAP_IN_2

BAT_IN_2

VDD_IO_2

BAT_IN_2ADAP_IN_2VDD_IO_2

P20_1

HCI_RXD_1HCI_TXD_1

HCI_RXD_1

P20_1

HCI_TXD_1

HCI_RXD_2 HCI_TXD_2

HCI_RXD_2HCI_TXD_2

P20_2

P20_2

Board Name

Size Title Rev

Date: Sheet o f

P/N

Module 1.0

IS2066B_L_and_R_JIG

A


????


Board Name

Size Title Rev

Date: Sheet o f

P/N

Module 1.0

IS2066B_L_and_R_JIG

A


????


Board Name

Size Title Rev

Date: Sheet o f

P/N

Module 1.0

IS2066B_L_and_R_JIG

A


????


D3SPE0572

21

D6SPE0572

21

D7SPE0572

21

D21SPE0572

21

PCB4FP-IS2066B_L

MIC_NTP5

MIC_PTP3

GNDTP20

HCI_RXDTP18

HCI_TXDTP16

VSSVIA

ADAP_IN_5VTP10

RST_NTP8AOHPL

TP2

AOHPRTP1

BAT_INTP19

UPDITP14

GNDTP21

MFBTP15P20

TP12

RFTP1RFTP1

RFLDO_OTP11

BK2_OTP9

VDDIOTP17

CODEC_VOTP13

BK1_OUTTP7

D14SPE0572

21

D13SPE0572

21

D10SPE0572

21

D5SPE1211

21

D8SPE0572

21

D4SPE0572

21

D9SPE1211

21 D22

SPE0572

21

PCB3FP-IS2066B_R

MIC_NTP5

MIC_PTP3

GNDTP20

HCI_RXDTP18

HCI_TXDTP16

VSSVIA

ADAP_IN_5VTP10

RST_NTP8AOHPL

TP2

AOHPRTP1

BAT_INTP19

UPDITP14

GNDTP21

MFBTP15P20

TP12

RFTP1RFTP1

RFLDO_OTP11

BK2_OTP9

VDDIOTP17

CODEC_VOTP13

BK1_OUTTP7



5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Close to FT423212/37/64 pin

Close to FT423220/31/42/56 pin

LDO33(500mA)

When ADAP_5V insert, Q13 pin1&3 short, Q14 pin1&3 open, TXD,RXD active.When ADAP_5V open, Q13 pin1&3 open, Q14 pin1&3 short, TXD, RXD short toground.

0603

0603

0603

0603 0603 0603 0603

08050805

0805

0805

0805

0805

0805

0805

0805

0805

0805

0805

0402 0402 0402

0402 0402 0402 0402

0402

0402

0805

0603

0805

0402

0805 0603

0603

0805

0805 0805

0603 0603

USB to UART COM port

GND test point

HCI_RXD_1HCI_TXD_1

HCI_TXD_2HCI_RXD_2

USB_DP_4232

USB_DM_4232

USB_DM_4232USB_DP_4232

3V3_4232

1V8_4232

1V8_4232

3V3_4232

3V3_4232

3V3_4232

1V8_4232

3V3_4232

USB_5V

USB_5VADAP_5V

USB_5VADAP_5V

USB_5VADAP_5V

USB_5VADAP_5V

HCI_RXD_1HCI_TXD_1

HCI_TXD_2HCI_RXD_2

HCI_TXD_1HCI_RXD_1

HCI_RXD_2 HCI_TXD_2

Board Name

Size Title Rev

Date: Sheet o f

P/N

USB TO UART 1.0

IS2066B_L_and_R_JIG

B


????


Board Name

Size Title Rev

Date: Sheet o f

P/N

USB TO UART 1.0

IS2066B_L_and_R_JIG

B


????


Board Name

Size Title Rev

Date: Sheet o f

P/N

USB TO UART 1.0

IS2066B_L_and_R_JIG

B


????


FB2FB-0603

12

C310.1u/16V

R425K1

12

R445K1

12

C411u/10V

U11FT4232H

ADBUS016

ADBUS117

ADBUS218

ADBUS319

ADBUS421

ADBUS522

ADBUS623

ADBUS724

BDBUS026

BDBUS127

BDBUS228

BDBUS329

BDBUS430

BDBUS532

BDBUS633

BDBUS734

CDBUS038

CDBUS139

CDBUS240

CDBUS341

CDBUS443

CDBUS544

CDBUS645

CDBUS746

DDBUS048

DDBUS152

DDBUS253

DDBUS354

DDBUS455

DDBUS557

DDBUS658

DDBUS759

PWREN#60

SUSPEND#36

VCC

IO20

VCC

IO31

VCC

IO42

VCC

IO56

VCO

RE

12

VCO

RE

37

VCO

RE

64

VPLL

9VP

HY

4

VREGIN50

VREGOUT49

DM7

DP8

REF6

RESET#14

EECS63

EECLK62

EEDATA61

OSCI2

OSCO3

TEST13

AGN

D10

GN

D1

GN

D5

GN

D11

GN

D15

GN

D25

GN

D35

GN

D47

GN

D51

C371u/10V

R395K1

12

C320.1u/16V

R400

1 2

C260.01u/16V

R700

12

C391u/10V

Q16STS2306

31

2

R606K8

12

JP3JP 1x2

12

R4912K/1%

12

R680

12

JP1JP 1x2

12

R690

12

U10

RT9167A-33PB

VIN1

EN3

BP4

VOUT5

GND2

Q15STS2306

31

2

R385K1

12

R455K1

12

Q14STS2306

31

2

C304.7u/10V

D-D+

P2USB-B-R

23

14

56

C361u/10V

Q19STS2306

31

2Q20STS2306

31

2

C331u/10V

C351u/10V

JP13JP 1x2

1 2R596K8

12

C280.1u/16V

C2510u/16V

C344.7u/10V

Q13STS2306

31

2

C4212p/50V

R511K/1%

1 2

C4312p/50V

JP4JP 1x2

12

C294.7u/10V

Q17STS2306

31

2

C2710u/16V

R410

1 2

C381u/10V

JP2JP 1x2

12

Q18STS2306

31

2

R435K1

12R71

0

12

R616K8

12

X1X4P-12MHZ

4132

R475K1

12

R586K8

12

R465K1

12

R371K5

12

C401u/10V

FB1FB-0603

12

Figure 4-9. MPMF 1x2 Test Fixture Connection Diagram

Hardware limitation: The initial default value of MPMF is R-Primary L-Secondary. The user can notmodify this setting.



5. Appendix A - Edgar III Board CircuitThe following is the Edgar III board circuit diagram.

Figure 5-1. Edgar III Board Circuit Diagram5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SW1 --- CONDITION SETUPSW1-1: EAN, ON --- EAN PULL HIGHSW1-2: P20, ON --- P20 PULL LOWSW1-3: P24, ON --- P24 PULL LOWSW1-4: BAT TUNNING, ON --- BAT_IN can tune by VR1,1.51V~4.4V.

, OFF -- BAT_IN Off

R1: 56k ohm for 3.3V system 43k ohm for 2.8V system

Level Shift

SW2:OFF - VCC_HCI is 3.3VON - VCC_HCI is 1.8V

MAIN CIRCUIT 1.0

BOSCH_V2

ISSC Technologies Corp.ADD. 4F, No.8, Dusing Rd., Hsinchu Science Park,

Hsinchu City 30078, TaiwanTEL. 886-3-5778385

C

1 1Tuesday, October 25, 2011

????Board Name

Size Title Rev

Date: Sheet of

P/N

HCI_RXD

P20

HCI_TXDGND

CTS

EAN

P24

TX RX

D+D-

TXRX

CTS

RTS

RTS_LS

CTS_LS

P24

D+D-

P20

5V_USB

BAT_INR

TS

HCI_RTSHCI_CTS

EANP24P20

HCI_RXDHCI_TXD

RTS_LS

TXHCI_TXD

HCI_RTS

HCI_RXD

HCI_CTS

RX

CTS_LS

HCI_RXD

TX

HCI_TXD

RX

RTS_LS

CTS_LS

HCI_RTS

HCI_CTS

EAN

EXT_3V35V_USB

EXT_3V3

EXT_3V3

EXT_3V3

BAT_IN5V_USBVCC_HCI

5V_USB

5V_USB

BAT_IN

5V_USB

VCC_HCI

EXT_3V3

VCC_2V4

VCC_2V4

EXT_3V3

VCC_HCI

VCC_2V4

C330.1u/16V

JP2JP 1x8

12345678

DP3DP-4

21

X1X4P-12MHZ

41

32

C340.1u/16V

C310.1u/16V

JP1JP 1x2

12

R15470

1 2

R164K7

12

U3RT9179

1

3 4

5

2VIN

EN ADJ

VOUT

GND

Q1STS2306

312

U8RT9179

1

3 4

5

2VIN

EN ADJ

VOUT

GND

R1130K/1%

12

R710K

12

U9

SN74AHC1G08DCK

1

3 4

5

2A

GND Y

VCC

B

C110.1u/16V

DP2DP-4

21

U14

SN74AHC1G08DCK

1

3 4

5

2A

GND Y

VCC

B

U12

SN74AHC1G08DCK

1

3 4

5

2A

GND Y

VCC

B

C147u/16V

12

C300.1u/16V

C16

10u/16V

R1010K

12

C220.1u/16V

C510u/16V

U11

SN74AHC1G08DCK

1

3 4

5

2A

GND Y

VCC

B

R43K3

12

R1256K

12

C20

10u/16V

C2810u/16V

R2470

12

C910u/16V

DP4DP-4

21

TP41

C410u/16V

U2RT9179

1

3 4

5

2VIN

EN ADJ

VOUT

GND

DP5 DP-421

TP31

C610u/16V

C710u/16V

C210u/16V

R1830K/1%

12

C23NP-0402

12

U13

SN74AHC1G08DCK

1

3 4

5

2A

GND Y

VCC

B

C210.1u/16V

C1010u/16V

R1730K/1%

12

C24NP-0402

12

U10

SN74AHC1G08DCK

1

3 4

5

2A

GND Y

VCC

B

R818K

12

C1712p/50V

C180.1u/16V

VR13296W-1-103(10Kohm)

123

C25NP-0402

12

C320.1u/16V

R91K2

12

D-D+

P1USB-B-R

23

14

56

C26NP-0402

12

U7MCP2200

123456789

10 11121314151617181920VDD

OSC1OSC2RSTGP7/TxLEDGP6/RxLEDGP5GP4GP3TX RTS

RXCTSGP2

GP1/USBCFGGP0/SSPND

VUSBD-D+

VSS

C2910u/16V

ONSW1

SW-4BIT

1 2 3 4

5 6 7 8

R630K/1%

12

DP6 DP-4

21

TP51

C310u/16V

ONSW2

SW-1BIT

12

R31K/1%

12

U4RT9179

1

3 4

5

2VIN

EN ADJ

VOUT

GND

C350.1u/16V

DP1DP-4

21

D1LED-HR

12

C1912p/50V

R143K/1%

C810u/16V

R510

12

C2710u/16V

U1RT9179

1

3 4

5

2VIN

EN ADJ

VOUT

GND

R1410K

12

R1330K/1%

12

CN1CONN 2x20

12345678910111213141516171819202122232425262728293031323334353637383940

AN3082Appendix A - Edgar III Board Circuit


6. Document Revision HistoryRevision Date Section Description

A 05/2019 Document Initial release

AN3082Document Revision History


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Microchip’s customer notification service helps keep customers current on Microchip products.Subscribers will receive e-mail notification whenever there are changes, updates, revisions or erratarelated to a specified product family or development tool of interest.

To register, access the Microchip web site at http://www.microchip.com/. Under “Support”, click on“Customer Change Notification” and follow the registration instructions.

Customer Support

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative• Local Sales Office• Field Application Engineer (FAE)• Technical Support

Customers should contact their distributor, representative or Field Application Engineer (FAE) for support.Local sales offices are also available to help customers. A listing of sales offices and locations is includedin the back of this document.

Technical support is available through the web site at: http://www.microchip.com/support

Microchip Devices Code Protection Feature

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.• Microchip believes that its family of products is one of the most secure families of its kind on the

market today, when used in the intended manner and under normal conditions.• There are dishonest and possibly illegal methods used to breach the code protection feature. All of

these methods, to our knowledge, require using the Microchip products in a manner outside theoperating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so isengaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

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http://www.microchip.com/http://www.microchip.com/http://www.microchip.com/support

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of theircode. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving thecode protection features of our products. Attempts to break Microchip’s code protection feature may be aviolation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your softwareor other copyrighted work, you may have a right to sue for relief under that Act.

Legal Notice

Information contained in this publication regarding device applications and the like is provided only foryour convenience and may be superseded by updates. It is your responsibility to ensure that yourapplication meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORYOR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITSCONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE.Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in lifesupport and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resultingfrom such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectualproperty rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud,chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST,SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip TechnologyIncorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLightLoad, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of MicrochipTechnology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom,CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM,dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming,ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, OmniscientCode Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE,Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, TotalEndurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA aretrademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary ofMicrochip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

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© 2019, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

ISBN: 978-1-5224-4552-4

Quality Management System Certified by DNV

ISO/TS 16949Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and waferfabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in Californiaand India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC®DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory andanalog products. In addition, Microchip’s quality system for the design and manufacture of developmentsystems is ISO 9001:2000 certified.

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AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPECorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200Fax: 480-792-7277Technical Support:http://www.microchip.com/supportWeb Address:http://www.microchip.comAtlantaDuluth, GATel: 678-957-9614Fax: 678-957-1455Austin, TXTel: 512-257-3370BostonWestborough, MATel: 774-760-0087Fax: 774-760-0088ChicagoItasca, ILTel: 630-285-0071Fax: 630-285-0075DallasAddison, TXTel: 972-818-7423Fax: 972-818-2924DetroitNovi, MITel: 248-848-4000Houston, TXTel: 281-894-5983IndianapolisNoblesville, INTel: 317-773-8323Fax: 317-773-5453Tel: 317-536-2380Los AngelesMission Viejo, CATel: 949-462-9523Fax: 949-462-9608Tel: 951-273-7800Raleigh, NCTel: 919-844-7510New York, NYTel: 631-435-6000San Jose, CATel: 408-735-9110Tel: 408-436-4270Canada - TorontoTel: 905-695-1980Fax: 905-695-2078

Australia - SydneyTel: 61-2-9868-6733China - BeijingTel: 86-10-8569-7000China - ChengduTel: 86-28-8665-5511China - ChongqingTel: 86-23-8980-9588China - DongguanTel: 86-769-8702-9880China - GuangzhouTel: 86-20-8755-8029China - HangzhouTel: 86-571-8792-8115China - Hong Kong SARTel: 852-2943-5100China - NanjingTel: 86-25-8473-2460China - QingdaoTel: 86-532-8502-7355China - ShanghaiTel: 86-21-3326-8000China - ShenyangTel: 86-24-2334-2829China - ShenzhenTel: 86-755-8864-2200China - SuzhouTel: 86-186-6233-1526China - WuhanTel: 86-27-5980-5300China - XianTel: 86-29-8833-7252China - XiamenTel: 86-592-2388138China - ZhuhaiTel: 86-756-3210040

India - BangaloreTel: 91-80-3090-4444India - New DelhiTel: 91-11-4160-8631India - PuneTel: 91-20-4121-0141Japan - OsakaTel: 81-6-6152-7160Japan - TokyoTel: 81-3-6880- 3770Korea - DaeguTel: 82-53-744-4301Korea - SeoulTel: 82-2-554-7200Malaysia - Kuala LumpurTel: 60-3-7651-7906Malaysia - PenangTel: 60-4-227-8870Philippines - ManilaTel: 63-2-634-9065SingaporeTel: 65-6334-8870Taiwan - Hsin ChuTel: 886-3-577-8366Taiwan - KaohsiungTel: 886-7-213-7830Taiwan - TaipeiTel: 886-2-2508-8600Thailand - BangkokTel: 66-2-694-1351Vietnam - Ho Chi MinhTel: 84-28-5448-2100

Austria - WelsTel: 43-7242-2244-39Fax: 43-7242-2244-393Denmark - CopenhagenTel: 45-4450-2828Fax: 45-4485-2829Finland - EspooTel: 358-9-4520-820France - ParisTel: 33-1-69-53-63-20Fax: 33-1-69-30-90-79Germany - GarchingTel: 49-8931-9700Germany - HaanTel: 49-2129-3766400Germany - HeilbronnTel: 49-7131-72400Germany - KarlsruheTel: 49-721-625370Germany - MunichTel: 49-89-627-144-0Fax: 49-89-627-144-44Germany - RosenheimTel: 49-8031-354-560Israel - Ra’ananaTel: 972-9-744-7705Italy - MilanTel: 39-0331-742611Fax: 39-0331-466781Italy - PadovaTel: 39-049-7625286Netherlands - DrunenTel: 31-416-690399Fax: 31-416-690340Norway - TrondheimTel: 47-72884388Poland - WarsawTel: 48-22-3325737Romania - BucharestTel: 40-21-407-87-50Spain - MadridTel: 34-91-708-08-90Fax: 34-91-708-08-91Sweden - GothenbergTel: 46-31-704-60-40Sweden - StockholmTel: 46-8-5090-4654UK - WokinghamTel: 44-118-921-5800Fax: 44-118-921-5820

Worldwide Sales and Service


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IntroductionTable of Contents1. Hardware Guidelines1.1. Placement and Routing Guidelines1.2. Power and Ground1.3. RF Traces and Components1.4. Interference Guidelines1.5. Antenna Guidelines1.6. Reference PCB1.7. Buck Layout Guide1.8. Bypass Capacitor Placement and Routing1.9. Crystal Oscillator Routing and Placement1.10. Audio/Voice Interface Routing1.11. Analog Microphone Inputs1.12. WST Earbud Block Diagram1.12.1. WST Earbud Features

1.13. Charger Box Block Diagram1.13.1. Charger Box Features

1.14. Auto Embedded Mode Description1.15. Manual Embedded Mode Description1.16. Host MCU Mode Description1.17. General Purpose Input Output1.18. IS2066B Power Tree1.19. Conductive RF Measurement Setup1.19.1. Hardware Test Connection1.19.2. ISRT Tool Test Procedure

2. Antenna Note2.1. Antenna Return Loss2.2. Antenna Placement

3. Reference Circuit4. Mass Production Test Board Design4.1. MP Tool Flow for IS2066B4.2. MPBT DUT Test Board Design4.3. MPMF 1X2 Fixture

5. Appendix A - Edgar III Board Circuit6. Document Revision HistoryThe Microchip Web SiteCustomer Change Notification ServiceCustomer SupportMicrochip Devices Code Protection FeatureLegal NoticeTrademarksQuality Management System Certified by DNVWorldwide Sales and Service

an3082 is2066b wireless stereo technology reference design application...

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