technology development for ingaas/inp-channel mosfets rodwell@ece.ucsb.edu 805-893-3244,...

Technology Development for InGaAs/InP-channel MOSFETs

rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax

MRS Spring Symposium, Tutorial: Advanced CMOS—Substrates, Devices, Reliability, and Characterization, April 13, 2009, San Francisco

Mark Rodwell University of California, Santa Barbara

Scope of Presentation

Topic of discussion is channel materials for CMOS...the potential use of III-V materials...and their advantages and limitations

To understand this, we must examine in some detailMOSFET scaling limits

Zeroth-Order MOSFET Operation

Bipolar Transistor ~ MOSFET Below Threshold

cI

beV ceV

voltagecollector with little varies

it through pass base reaching electrons allAlmost

)/exp(

al)(exponenti thermalison distributienergy emitter Because

c

bec

I

kTqVI

Field-Effect Transistor Operation

source draingate

Positive Gate Voltage

→ reduced energy barrier

→ increased drain current

FETs: Computing Their Characteristics

chdC

/ where/ electrongd vLQI

/~ DACgs

/ and / where chdgdgsmdsdsgsmd CGCgVGVgI

dschdgsgs VCVCQ

FET Characteristics

chdC /~ DACgs

dsdsgsmd VGVgI

ID

VDS

increasingVGS

electrongchdgdgsm vLCGCg / / /

FET Subthreshold Characteristics

gs

gs

s

s

ox

schanneloxgate

V

V

q

kT

qn

qn

C

qnVVV

lly withexponentia variescharge channel :drive gateWeak

ithlinearly w variescharge channel :drive gate Strong

)()(

Classical Long-Channel MOSFET Theory

*/ :channel off-pinched of endat city Exit velo3)

)()( usiondrift/diffby modeledTransport )2

.channel in field lateral Moderate1)

:sAssumption

mkTvv

x

xnqDExnqJ

E

thermalexit

nn

Classic Long-Channel MOSFET Theory

gthgsgoxD LVVWcI 2/)(

current limitedmobility2

,

)(

current limitedvelocity

, thgsexitgoxvD VVvWcI

1

Expression dGeneralize

,

2

,

D

D

vD

D

I

I

I

I

Id

VgsVth

mobility-limited

velocity-limited

:saturation nlarger tha voltagesdrainFor

ID

VDS

increasingVGS

Ohm

icconstant-current

Classic Long-Channel FET : Far Above Threshold

/ where

1/)(for )(

gexit

thgsthgsexitgoxD

LvV

VVVVVVvWcI

Id

VgsVth

V

Exponential, Square-Law, Linear FET Characteristics

Relevance of DC Parameters

Digital circuit speed largely controlled by on-state current

Standby power consumption controlled by off-state current

Dynamic power consumption controlled by supply Voltage

→ Examine VLSI Power & Delay Relationships

Zeroth-OrderVLSI Performance

Analysis

CMOS Power Dissipation & Gate Delay

y)probabilit switching(frequency2

: ndissipatiodower Dynamic

dominatesusually ecapacitanc g wirin

2/)(2/

delay Gate

2

ddtotaldynamic

onddPFETNFETwireonddtotalgate

VCP

IVCCCIVCVdd

Cwire

ddoffstatic

thonoff

VIP

nkTqVII

on DissipatiStatic

)/exp(/

current state Off offIVdd

kTqVonddstaticddwiredynamic

theIVPpfVCP /2 ~ ~ :ndissipatio dynamic and static between Tradeoff

NFETC

PFETC

onI

Why Large Current Density is Needed

S D S D S D S

G

G

Wg

gg nWW

n

widthtotal widthof each

fingers, 6 withFET

Vdd

Cwire

NFETC

PFETC

onI

.2/current requires

,delay at drive To

ddwired

wire

VCI

C

. large wireslong FETsLarge

needed. are FETslarge small, is If

wire

gd

C

/WI

Device Requirements

High on-state current per unit gate width

Low off-state current→ subthreshold slope

Low device capacitance; but only to point where wires dominate

Low supply voltage: probably 0.5 to 0.7 V

What Are Our Goals ?

Low off-state current (10 nA/m) for low static dissipation→ good subthreshold slope → minimum Lg / Tox

low gate tunneling, low band-band tunneling

Low delay CFET V/I d in gates where transistor capacitances dominate.

~1 fF/m parasitic capacitances→ low Cgs is desirable, but high Id is imperative

Low delay Cwire V/Id in gates where wiring capacitances dominate.

large FET footprint → long wires between gates→ need high Id / Wg ; target ~5 mA/m @ V= 0.7V

target ~ 3 mA/m @ V= 0.5V

Improving FETs

by Scaling

Simple FET ScalingGoal double transistor bandwidth when used in any circuit → reduce 2:1 all capacitances and all transport delays

→ keep constant all resistances, voltages, currents

All lengths, widths, thicknesses reduced 2:1

S/D contact resistivity reduced 4:1

oxgm TvWg /~/

oxgggs TLWC /~/

~/, gfgs WC

subcgsb TLWC /~/

If Tox cannot scale with gate length,

Cparasitic / Cgs increases,

gm / Wg does not increase

hence Cparasitic /gm does not scale

~/ ggd WC

FET scaling: Output Conductance & DIBL effects) D.O.S.neglects expression ( gsC

gchd WC ~

dschdgsgsd VCVCQQI where/

/~ oxgggs TLWC

transconductance

→ Keep Lg / Tox constant as we scale Lg

output conductance

parameter change

gate length decrease 2:1

gate dielectric capacitance density increase 2:1

gate dielectric equivalent thickness decrease 2:1

channel electron density increase 2:1

source & drain contact resistance decrease 4:1

current density (mA/m) increase 2:1

Changes required to double transistor bandwidth:

FET Scaling Laws

GW widthgate

GL

nm Transistors: it's all about the interfaces

Metal-semiconductor interfaces (Ohmic contacts): very low resistivity

Dielectric-semiconductor interfaces (Gate dielectrics): very high capacitance density

Transistor & IC thermal resistivity.

parameter change

gate length decrease 2:1

gate dielectric capacitance density increase 2:1

gate dielectric equivalent thickness decrease 2:1

channel electron density increase 2:1

source & drain contact resistance decrease 4:1

current density (mA/m) increase 2:1

Changes required to double transistor bandwidth:

What do we do if gate dielectric cannot be further scaled ?

FET Scaling Laws

GW widthgate

GL

Why Consider MOSFETs with III-V Channels ?

If FETs cannot be further scaled, instead increase electron velocity:

III-V materials → lower m*→ higher velocityId / Wg = qnsv Id / Qtransit = v / Lg

Difficulties:High-K dielectricsIII-V growth on Sibuilding MOSFETs

low m* constrains vertical scaling, reduces drive current

( need > 1000 cm2 /V-s mobility)

Candidate materials (?) InxGa1-xAs, InP, InAs ( InSb, GaAs)

III-V CMOS: The Benefit Is Low Mass, Not High Mobility

Id

VgsVth

: thresholdabovefar ate,nondegener theory,diffusion -drift Simple

low effective mass → high currents

/ginjectionLvV

)/(~ where 1/2*mkTvv thermalinjection )( VVVvWcI thgsinjectiongoxD

mobilities above ~ 1000 cm2/V-s of little benefit at 22 nm Lg

mV 700

that Ensure

~

)( thgs VVV

III-V MOSFETs for VLSI

What is it ?MOSFET with an InGaAs channel

What are the problems ?low electron effective mass→ constraints on scaling !must grow high-K on InGaAs, must grow InGaAs on Si

Device characteristics must be considered in more detail

Why do it ?low electron effective mass→ higher electron velocitymore current, less charge at a given insulator thickness & gate lengthvery low access resistance

III-V MOSFET

Characteristics

Low Effective Mass Impairs Vertical Scaling

Shallow electron distribution needed for high gm / Gds ratio, low drain-induced barrier lowering.

./ 2*2wellTmL

Only one vertical state in well. Minimum ~ 5 nm well thickness.→ Hard to scale below 22 nm Lg.

For thin wells, only 1st state can be populated.For very thin wells, 1st state approaches L-valley.

Energy of Lth well state

Semiconductor (Wavefunction Depth) Capacitance

./

energy state Bound2*2

wellwell TmLE

-4

-3

-2

-1

0

1

2

3

0 50 100 150 200 250

En

erg

y(e

V)

Y (Ang.)

Tsemi

semiTc /

ecapacitanctor Semiconduc

torsemiconduc

Density-Of-States Capacitance

Two implications:

- With Ns >1013/cm2, electrons populate satellite valleys - Transconductance dominated by finite state density

and n is the # of band minima

)//( 2* nmnEE swellf

2*2 / where nmqcdos

dosswellf cVV /

Fischetti et al, IEDM2007

Solomon & Laux , IEDM2001

motion) nalbidirectio(

Current Including Density of States, Wavefunction Depth

Id

VgsVth

: thresholdabovefar ate,nondegener theory,diffusion -drift Simple

DOSoxeq /c /c /c/c 111 1 where torsemiconduc

)( VVVvWcI thgsthermalgeqD

...but with III-V materials, we must also consider degenerate carrier concentrations.

Current of Degenerate & Ballistic FET

eV 1m

mA84

/)(

3

2

:densityCurrent

.)3/4( : velocityelectron ean M

,/)(2 : velocity ermi F

),)(2/( :density electron

:degenerateHighly

motion) ional(unidirect 2//:states ofDensity

2/32/1

0

*

2

2/32/1*2/5

2

2/3

2/1*

2*

2*

cf

cfs

f

cff

cfs

fs

EE

m

mn

qEEmnqvqnJ

vv

mEEv

EEmnn

mndEdN

...) Asbeck, , FischettiSolomon,

Laux,Natori, , Lundstrom(

2D vs. 1D Field-Effect Transistors in Ballistic Limit

tor.semiconduc inshift level FermieV 0.3for

m

mA8.2

eV 1m

mA17

eV 1m

mA84

)04.0/( channel InGaAs FET;-2D2/32/32/1

0

*

0*

cfcf EEEE

m

mJ

mm

Lg

Wg

Id

Source

Drain

gate

gateE

Lg

Wg

Id

Sources

Drains

gate

gateE

torsemiconduc inshift level FermieV 0.3for

m

mA9.3

eV 1m

mA13

eV 1nm 6

A 78

S78/2 eV, 37.0*2

pitch nm 6 @ wellsInGaAs nm 5 FETs;-1D ofArray

2,2

22

cfcf

wellmwell

well

EEEEJ

hqgTm

E

2D FET vs. Carbon Nanotube FET

tor.semiconduc inshift level FermieV 0.3for

, m

mA8.2

eV 1m

mA17

)04.0/*( channel InGaAs FET;-2D2/3

0

cf EEJ

mm

Lg

Wg

Id

Source

Drain

gate

gateE

torsemiconduc inshift level FermieV 0.3for

m

mA7.4

eV 1m

mA5.15

eV 1nm 5

A 78

S78/2

pitch nm 5 nanotubes, carbon ofArray 2

,

cfcf

tubem

EEEEJ

hqg

Lg

Wg

Sources

gate

Drains

Ballistic/Degenerate Drive Current vs. Gate Voltage

More careful analyses by Taur & Asbeck Groups, UCSD; Fischetti Group: U-Mass: IEDM2007

Drive Current in the Ballistic & Degenerate Limits

2/3*

,

2/1*2/3

)/()/(1 where,

V 1m

mA84

ooxodos

othgs

mmncc

mmnK

VVKJ

0

0.05

0.1

0.15

0.2

0.25

0.01 0.1 1

K

m*/mo

1.0 nm, n=1

0.8 nm, n=1

0.7 nm, n=6 0.4 nm, n=6

EOT includes wavefunction depth (0.5 nm for 3.5 nm InGaAs well)

n = # band minimacdos,o = density of states capacitance for m*=mo & n=1

Error bars on Si data points correct for (Ef-Ec)>> kT approximation

High Drive Current Requires Low Access Resistance

m 2015

V 5.0)( @ mmA/ 3~/Target

V 3.0)( @ mmA/ 5.1~/Target

1.0)/(

current, drive onimpact 10% For

gs

thDDgD

thDDgD

thDDSD

WR

VVWI

VVWI

VVRI

substrate

barrier

sidewall

metal gate

quantum well / channel

gate dielectric

N+ source N+ drain

source contact drain contact

Materials Selection;

What channel material should we use ?

Common III-V Semiconductors

InAs

360

GaSb

770

AlSb

1550

GaAs

1420InGaAs

760

InAlAs

1460InP

1350

200

1350 200

500

450

250

450

550

200

170

InGaP

1900

200

InSb

220

150

AlAs

2170

6.48 A lattice constant

6.48 A lattice constant 5.65 A lattice constant;grown on GaAs

5.87 A lattice constant;grown on InP

B. Brar

Semiconductor & Metal Band AlignmentsM. Wistey

Materials of Interest

material Si Ge GaAs InP In0.53Ga0.47As InAs

n 6 6 1 1 1 1

m*/m0 0.98 ml 1.6 ml 0.063 0.08 0.04 0.0230.19 mt 0.08 mt

-(L/X) separation, eV -- -- 0.29 ~0.5 0.5 0.73

bandgap, eV 1.12 0.66 1.42 1.34 0.74 0.35

mobility, cm2/V-s 1000 2000 5000 3000 10,000 25,000

high-field velocity 1E7 1E7 1-2E7 3.5E7 3.5E7 ???

Source: Ioffe Institutehttp://www.ioffe.rssi.ru/SVA/NSM/Semicondrough #s only

Drive Current in the Ballistic & Degenerate Limits

2/3*

,

2/1*2/3

)/()/(1 where,

V 1m

mA84

ooxodos

othgs

mmncc

mmnK

VVKJ

0

0.05

0.1

0.15

0.2

0.25

0.01 0.1 1

K

m*/mo

1.0 nm, n=1

0.8 nm, n=1

0.7 nm, n=6 0.4 nm, n=6

EOT includes wavefunction depth (0.5 nm for 3.5 nm InGaAs well)

n = # band minimacdos,o = density of states capacitance for m*=mo & n=1

Error bars on Si data points correct for (Ef-Ec)>> kT approximation

Si

InPInGaAs

Ge

Intervalley Separation Source: Ioffe Institutehttp://www.ioffe.rssi.ru/SVA/NSM/Semicond

Intervalley separation sets:

-high-field velocity throughintervalley scattering

-maximum electron density in channel without increased carrier effective mass

Choosing Channel Material: Other Considerations

Ge: low bandgap

GaAs: low intervalley separation

InP: good intervalley separationGood contacts only via InGaAs→ band offsetsmoderate mass→ better vertical scaling

InGaAs good intervalley separationbandgap too low ? → quantizationlow mass→ high well energy→ poor vertical scaling

InAs: good intervalley separationbandgap too lowvery low mass→ high well energy→ poor vertical scaling

Non-Parabolic Bands

c.pessimistigenerally are

sexpression FETband-Parabolic

tors.semiconducmost inSimilar

velocity.group Asyptotic

.hyperbolicnearly become

bands energies, highAt

zero.near for only

parabolic~ are Bands

k

Non-Parabolic Bands

T. Ishibashi, IEEE Transactions on Electron Devices, 48,11 , Nov. 2001,

MOSFET DesignAssuming

In0.5Ga0.5As Channel

Device Design / Fabrication Goals

substrate

barrier

sidewall

metal gate

quantum well / channel

gate dielectric

N+ source N+ drain

source contact drain contact

Device gate overdrive 700 500 300 mV drive current 5 3 1.4 mA/m Ns 6*1012 4*1012 2.5*1012 1/cm2

Dielectric: EOT 0.6 nm target, ~1.5 nm short term

Channel : 5 nm thick > 1000 cm2/V-s @ 5 nm, 6*1012 /cm2

S/D access resistance: 20 -m resistivity→ 0.5 -m2 contacts , ~2*1013 /cm2 , ~4*1019 /cm3 , 5 nm depth

substrate

barrier

sidewall

metal gate

quantum well / channel

gate dielectric

N+ source N+ drain

source contact drain contact

Target Device Parameters

m 10contact widenm 25 )m 250 2 )/(.(

thicknm 5 ,cm/105~ :well 212sn

213319 cm1052 thicknm 5 , cm105 /./ sn

Device Structure&

Process Flow

Device Fabrication: Goals & Challenges

III-V HEMTs are built like this→ Source Drain

Gate

....and most III-V MOSFETs are built like this→

K Shinohara

Device Fabrication: Goals & Challenges

r

InGaAs well

barrier

InP well

r

TiWN+ drainregrowth

N+ sourceregrowth

Yet, we are developing,at great effort,a structure like this →

Why ?

Source DrainGate

K Shinohara

Why not just build HEMTs ? Gate Barrier is Low !

Tunneling through barrier→ sets minimum thickness

Source DrainGate

Ec

Ewell-

EF

Ec

Ewell-

EF

Gate barrier is low: ~0.6 eV

Emission over barrier→ limits 2D carrier density

K Shinohara

eV 6.0~)( ,cm/10At 213cfs EEN

Ec

Ewell-

EF

N+ caplayer

Why not just build HEMTs ?

low leakage: need high barrier under gate

Source DrainGate

Ec

Ewell-

EF

Gate barrier also lies under source / drain contacts

low resistance: need low barrier under contacts

widegap barrier layer

N+ layer

K Shinohara

substrate

barrier

sidewall

metal gate

quantum well / channel

gate dielectric

N+ source N+ drain

source contact drain contact

The Structure We Need

no gate barrier under S/D contacts

high-K gatebarrier

Overlap between gateand N+ source/drain

-- is Much Like a Si MOSFET

How do we make this device ?

S/D Regrowth Process Flow

Regrown S/D FETs: Versions

planar regrowthregrowth under sidewalls

need thin sidewalls(now ~20-30 nm)

..or doping under sidewalls

Wistey et al 2008 MBE conference

60

S/D Regrowth by Migration-Enhanced Epitaxy

MBE growth is line-of-sight → gaps in regrowth near gate edges

MEE provides surface migration during regrowth→ eliminates gaps

Original Interface

InGaAs Regrowth

SiO2 dummy gate

SEM: Greg Burek

No gapsSmooth surfaces.

SEM: Uttam Singisetti

InGaAs Regrowth

SEM Cross Section

SiO2 dummy gate

SEM Side View (Oblique)Top of gate

High Si activation (4x1019 cm-3). Quasi-selective: no growth on sidewalls

Wistey et al 2008 MBE conference

Side of gate

Self-Aligned Planar III-V MOSFETs by Regrowth

Wistey Singisetti Burek Lee

N+ InGaAs regrowth, Mo contact metal

gate

Mo contact metal

Self-Aligned Planar III-V MOSFETs by Regrowth

Wistey Singisetti Burek Lee

Regrown S/D FETs: Images

Regrown S/D FETs: Images

III-V MOS

0

0.05

0.1

0.15

0.2

0.25

0.01 0.1 1

K

m*/mo

1.0 nm, n=1

0.8 nm, n=1

0.7 nm, n=6 0.4 nm, n=6

EOT includes wavefunction depth (0.5 nm for 3.5 nm InGaAs well)

InGaAs / InP MOSFETs: Why and Why Not

low m*/m0 → high vcarrier → more currentlow m*/m0 → low density of states → less current

2/3

*,

2/1*

2/3

1

where

, V 1m

mA84

oox

odos

o

thgs

mm

nc

c

mmnK

VVKJ

Low m* impairs vertical (hence Lg ) scaling ;InGaAs no good below 22-nm.

n = # band minimacdos,o = density of states capacitance for m*=mo & n=1

Error bars on Si data points correct for (Ef-Ec)>> kT approximation

Si wins if high-K scales below 0.6 nm EOT; otherwise, III-V has a chance

ballistic / degenerate calculation

InGaAs allows very low access resistance

InGaAs/InP Channel MOSFETs for VLSI

Low-m* materials are beneficial only if EOT cannot scale below ~1/2 nm

Devices cannot scale much below 22 nm Lg→ limits IC density

Little CV/I benefit in gate lengths below 22 nm Lg

Gate dielectrics, III-V growth on Si: also under intensive development

Need device structure with very low access resistance radical re-work of device structure & process flow