scaling of high frequency iii-v transistors rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax...

Scaling of High Frequency III-V Transistors

rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax

Short Course, 2009 Conference on InP and Related Materials, Newport Beach, CA, May 10-14

Mark Rodwell University of California, Santa Barbara

THz Transistors

Transistor bandwidths are increasing rapidly.

Si MOSFETs will soon reach 500+ GHz cutoff frequencies.

It is now clear III-V bipolar transistors can reach ~2-3 THz cutoff frequencies.

III-V FETs have comparable potential, but the prospects and analysis are less clear.

The limits to transistor bandwidth are:contact resistivities

gate dielectric capacitance densities.device and IC power density & thermal resistance.

challenges in reliably fabricating small devices.

WhyTHz Transistors ?

Why Build THz Transistors ?

THz amplifiers→ THz radios→ imaging, sensing, communications

precision analog design at microwave frequencies→ high-performance receivers

500 GHz digital logic→ fiber optics

Higher-Resolution Microwave ADCs, DACs, DDSs

PerformanceFigures of Merit

Transistor figures of Merit / Cutoff Frequencies

H21=short-circuit current gain

gain

s, d

B

MAG = maximum available power gain:impedance-matched

U= unilateral power gain:feedback nulled, impedance-matched

fmax

power-gaincutoff frequency

fcurrent-gaincutoff frequency

What Determines Gate Delay ?

cexLOGIC

LOGIC

Ccb

becbi

becbC

LOGIC

IRq

kTV

V

IR

CCR

CCI

V

4

leastat bemust swing logic The

resistance base the through

charge stored

collector base Supplying

resistance base the through

charging ecapacitanc on Depleti

swing logic the through

charging ecapacitanc on Depleti

:by ermined Delay DetGate

bb

depletion,bb

depletion,

JVR

v

T

A

A

V

V

I

VC

T)V(VvεJ

CI

CCIV

f

ex

electron

C

CE

LOGIC

C

LOGICcb

cceceelectronKirk

cbC

becbCLOGIC

cb

highat low for low very bemust

22

/2

objective. design key HBTa is / High

total.of 80%-55% is

withcorrelated not well Delay

delay; totalof 25%-10y typicall)(

logic

emitter

collector

min,

2depletion full,operating ,max,

depl,

HBT Design For Digital & Mixed-Signal Performance

from charge-control analysis:

)./5.05.0(

)/5.05.05.0(

)/5.05.0)(/(

)66)(/(

LCfcbijebb

LCfcbicbxex

LCfcbicbxjeC

fcbicbxjeCLgate

VICCR

VICCR

VICCCqIkT

CCCIVT

analog ICs have similar bandwidth constraints...

High-FrequencyElectron Device

Design

Simple Device Physics: Resistance

Good approximation for contactwidths less than 2 transfer lengths.

A

TR bulk

bulk resistance

AR contact

contact resistance-perpendicular

L

W

AR sheet

contact

3

'

contact resistance- parallel

Simple Device Physics: Depletion Layers

capacitance

T

AC

transit time

v

T

2

space-chargelimited current

2

22

max depletionapplied VVT

v

A

I

2 where

max

depletionapplied VVI

C

T

VCI

Simple Device Physics: Thermal Resistance

Exact

L

W

WK

W

L

LKR

th

thth

1

1

sinh1

sinh1

Carslaw & Jaeger 1959

LKW

L

LKR

ththth

1ln

1

junctionnear

flowheat lcylindrica

Long, Narrow StripeHBT Emitter, FET Gate

junction fromfar

flowheat spherical

LKLKR

ththth

1

4

1

surfacenear

flowheat planar

Square ( L by L ) IC on heat sink

surface fromfar

flowheat spherical

Simple Device Physics: Fringing Capacitance

5.1T

W

L

C

wiring capacitance

plate-parallel fringing

)3 to(1

/ and / of

function varying-slowly

21 GWGWL

C

FET parasitic capacitances

LC / ~/ LCparasitic

VLSI power-delay limits FET scaling constraints

Electron Plasma Resonance: Not a Dominant Limit

*2kinetic

1

nmqA

TL

T

AC

ntdisplaceme

m

dielecic L

Rf

2

1

2

1

frequency scattering

kinetic

bulk

mnmqA

TR

*2bulk

1

2

1

2/1

frequency relaxation dielectric

bulkntdisplaceme

RC

fdielecicntdisplacemekinetic

2/1

frequencyplasma

CLf plasma

THz 800 THz 7 THz 74319 cm/105.3

InGaAs-

n

319 cm/107

InGaAs-

pTHz 80 THz 12 THz 13

Electron Plasma Resonance: Not a Dominant Limit

*2kinetic

1

nmqA

TL

T

AC

ntdisplaceme

m

dielecic L

Rf

2

1

2

1

frequency scattering

kinetic

bulk

mnmqA

TR

*2bulk

1

2

1

2/1

frequency relaxation dielectric

bulkntdisplaceme

RC

fdielecicntdisplacemekinetic

2/1

frequencyplasma

CLf plasma

THz 800 THz 7 THz 74319 cm/105.3

InGaAs-

n

319 cm/107

InGaAs-

pTHz 80 THz 12 THz 13

Electron Plasma Resonance: Not a Dominant Limit

*2kinetic

1

nmqA

TL

T

AC

ntdisplaceme

m

dielecic L

Rf

2

1

2

1

frequency scattering

kinetic

bulk

mnmqA

TR

*2bulk

1

2

1

2/1

frequency relaxation dielectric

bulkntdisplaceme

RC

fdielecicntdisplacemekinetic

2/1

frequencyplasma

CLf plasma

THz 800 THz 7 THz 74319 cm/105.3

InGaAs-

n

319 cm/107

InGaAs-

pTHz 80 THz 12 THz 13

Electron Plasma Resonance: Not a Dominant Limit

*2kinetic

1

nmqA

TL

T

AC

ntdisplaceme

m

dielecic L

Rf

2

1

2

1

frequency scattering

kinetic

bulk

mnmqA

TR

*2bulk

1

2

1

2/1

frequency relaxation dielectric

bulkntdisplaceme

RC

fdielecicntdisplacemekinetic

2/1

frequencyplasma

CLf plasma

THz 800 THz 7 THz 74319 cm/105.3

InGaAs-

n

319 cm/107

InGaAs-

pTHz 80 THz 12 THz 13

Frequency Limitsand Scaling Laws of (most) Electron Devices

width

lengthlog

length

power

thicknessarea /

length

width

4area

area/

thickness/area

thickness

2limit-charge-space max,

T

I

R

R

C

sheetcontactbottom

contacttop

To double bandwidth, reduce thicknesses 2:1 Improve contacts 4:1reduce width 4:1, keep constant lengthincrease current density 4:1

topR

bottomR

PIN photodiode

parameter change

collector depletion layer thickness decrease 2:1

base thickness decrease 1.414:1

emitter junction width decrease 4:1

collector junction width decrease 4:1

emitter contact resistance decrease 4:1

current density increase 4:1

base contact resistivity decrease 4:1

Changes required to double transistor bandwidth:

Linewidths scale as the inverse square of bandwidth because thermal constraints dominate.

eW

bcWcTbT

ELlength emitter

Bipolar Transistor Scaling Laws

parameter change

gate length decrease 2:1

gate dielectric capacitance density increase 2:1

gate dielectric equivalent thickness decrease 2:1

channel electron density increase 2:1

source & drain contact resistance decrease 4:1

current density (mA/m) increase 2:1

Changes required to double transistor bandwidth:

Linewidths scale as the inverse of bandwidth because fringing capacitance does not scale.

FET Scaling Laws

GW widthgate

GL

THz & nm Transistors: it's all about the interfaces

Metal-semiconductor interfaces (Ohmic contacts): very low resistivity

Dielectric-semiconductor interfaces (Gate dielectrics): very high capacitance density

Transistor & IC thermal resistivity.

BipolarTransistors

Indium Phosphide Heterojunction Bipolar Transistors

Z. GriffithE. Lind

Bipolar Transistor Operation

cI

beV ceV

voltagecollector with little varies

it through pass base reaching electrons allAlmost

)/exp(

al)(exponenti thermalison distributienergy emitter Because

c

bec

I

kTqVI

Transistor Hybrid-Pi equivalent circuit model

nkTqIg Em /

)( cbmjebe gCC

mbe gR /

Cutoff frequencies in HBTs

collex

Ebc

Ejecollectorbase RR

qI

kTC

qI

kTC

f

2

1

nbbase DT 22 effccollector vT 2

cbibbCR

ff

8max

Epitaxial Layer Structure

emitter

emittercap

gradedbase

collector

subcollector

Epitaxy: InP Emitter, InGaAs Base, InP Collector, Both Junctions GradedKey Features:

N++ InGaAs emitter contact layer

InP emitter

InGaAs/InAlAs superlattice e/b grade

InGaAs graded basebandgap or doping grade

BC setback layer

InGaAs/InAlAs superlattice b/c grade

InP collector

InGaAs etch-stop layerthin for heat conduction

InP subcollector

Layer Material Doping Thickness (nm)

Emitter cap In0.53Ga0.47As 8 1019 cm-3: Si 25

N+ emitter InP 8 1019 cm-3: Si 50

N- emitter InP 1 1018 cm-3: Si 20

Emitter-base grade In0.53Ga0.47As / In0.52Al0.48As,

1.6 nm period N: 1 1017 cm-3: Si

24

Emitter-base grade In0.53Ga0.47As / In0.52Al0.48As,

1.5 nm period P: 8 1017 cm-3: C 1

Base In0.53Ga0.47As P: 7-4 1019 cm-3: C 24.5

Setback In0.53Ga0.47As N: 9 1016 cm-3: Si 4.5

Base-collector grade

In0.53Ga0.47As / In0.52Al0.48As, 1.6 nm period

N: 9 1016 cm-3: Si 15

Pulse doping InP 6 1018 cm-3: Si 3

Collector InP N: 2 1016 cm-3: Si 82

etch-stop In0.53Ga0.47As N: 8 1019 cm-3: Si 5

Subcollector InP N: 8 1019 cm-3: Si ~200

M. DahlstromZ. Griffith UCSB

M. UrteagaTSC

emitter

emittercap

gradedbase

collector

subcollector

Epitaxy with Abrupt BE Junction

Similar design

Abrupt E/B junction (no e/b grade)

Advantages:ease of stopping emitter etch on base→ good base contacts

Disadvantages:Increased Vbe .Cannot make e/b ledge.

Layer Material Doping Thickness (nm)

Emitter cap In0.53Ga0.47As 8 1019 cm-3: Si 25

N+ emitter InP 8 1019 cm-3: Si 50

N- emitter InP 1 1018 cm-3: Si 20

N- emitter InP N: 1 1017 cm-3: Si 24

Emitter-base grade In0.53Ga0.47As / In0.52Al0.48As,

1.5 nm period P: 8 1017 cm-3: C 1

Base In0.53Ga0.47As P: 7-4 1019 cm-3: C 24.5

Setback In0.53Ga0.47As N: 9 1016 cm-3: Si 4.5

Base-collector grade

In0.53Ga0.47As / In0.52Al0.48As, 1.6 nm period

N: 9 1016 cm-3: Si 15

Pulse doping InP 6 1018 cm-3: Si 3

Collector InP N: 2 1016 cm-3: Si 82

etch-stop In0.53Ga0.47As N: 8 1019 cm-3: Si 5

Subcollector InP N: 8 1019 cm-3: Si ~200

M. DahlstromZ. GriffithE. Lind

Alternative Grades for Thinner Epitaxy

Common Grade in LiteratureInGaAs/InAlAs 18 nm thick, 1.5 nm period

Sub-monolayer Grade0.15 nm InAlAs, (0.15 to 0.165 nm InGaAs)10.8 nm thick

Strained InxGa1-xAs Grade

InGaAs/GaAs 6 nm

E . LindZ. Griffith

Other Methods of Grading the Junctions

IEDM 2001

InGaAs/InGaAsP/InP grade InP/GaAsSb/InP DHBT

-suitable for MOCVD growth

- excellent results

- does not need B/C grading

- E/B band alignment through GaAsSb alloy ratio (strain)

or InAlAs emitter

Transport Analysis

Approximate Carrier Transit Times eW

bcWcTbT

exitbnbb vTDT 22

satcc vT 2

ELlength emitter

TimeTransit Base

TimeTransit Collector

Base Transit Time with Graded Base

gbg

g

LWsatgngngbb

EkTWL

L

evLDLDLW gb

/

:length grading theis where

1/// /2

fs 35/

ifcorrect modeldiffusion -Drift* kTmDτ nmb

cm/s 103

secV/cm 40

:Assumes

7

2

exit

N

v

D

Dino Mensa

Base Transit Time: Grading Approaches Dino MensaMiguel UrteagaMattias Dahlström

Compositional grading: strained graded InGaAs base

Doping grading unstrained In0.53Ga0.47As base

(strained) AsGaIn AsGaIn

:drop potential meV 52

0.470.530.5450.455

/cm105~ to/cm108~

:from varieddoping Carbon319319

V=0

TcTc/2

-

-+ +

V=0

Tc/4

+ +

-

-

+ +

-

-

-

-

+

+

Collector Transit TimeT. Ishibashi

base.near velocity tosensitive more is

2)(

)/1(

sketch) (refer to ticselectrosta elementary From

c

0

c

CT

eff

cc

v

Tdx

xv

Tx

.scattering L- todue decreasesthen

high, is velocity initial as ,Fortuitous

layers nm 200-70~for cm/s103.5 :InP

:voltagecollector .density vscurrent Kirk fromor ata,d RF fit tobest From7

Space-Charge Limited Current Density → Ccb charging time

Collector Field Collapse (Kirk Effect)

Collector Depletion Layer Collapse

)2/)(/( 2 cdsatcb TqNvJV

)2/)(( 2min, cTqNV dcb

eff

C

CECE

LOGICCLOGICcCLOGICcb v

T

A

A

VV

VIVTAIVC

2/

emitter

collector

min,

collector

2

min,max /)2(2 ccbcbeff TVVvJ

cecbbe VVV )( hence , that Note

Collector capacitance charging time scales linearly with collector thickness if J = Jmax

Space-Charge-Limited Current (Kirk effect) in DHBTs

ceV

Jff

increased with

increases esholdeffect thr-Kirk

highat and in Decrease max

CEEeffective

effectivesat

c

c

ce

satce

TWLA

Av

TR

dI

dV

JV

2

is areaflux current

collector effective thewhere

2

increased with in Increase2

chargespace

,

2min,

2min,max

/)(2

/)2(2

ccecesat

ccbcbsat

TVVv

TVVvJ

100

200

300

400

500

0 2 4 6 8 10 12

f (

GH

z)

Je (mA/um2)

f, -0.3 V

cb

0.0 Vcb

-0.2 Vcb

0.2 Vcb

0.6 Vcb

0

2

4

6

8

10

12

14

16

0 0.5 1 1.5 2 2.50

5

10

15

20

25

30

35

40

J e (m

A/

m2 )

Vce

(V)

Ajbe

= 0.6 x 4.3 m2

Ib step

= 180 uA

Vcb

= 0 V

Ic (mA

)

Peak ft, f

max

Current-induced Collector Velocity Overshoot

0

0.5

1

1.5

2

2.5

0 0.5 1 1.5 2 2.5 3 3.5

tau e

c, ps

inverse current density, 1/J,m2/mA

J=0

J= 8 mA/um2

300 Å InGaAs base

2000 Å InP collector

280 GHz peak f

bias. with of variation todue and),/ asnot vary does often (1/current bias hfactor witideality emitter in modulation toduepart in also is variationnonlinear observed :CAUTION ec jeEexm CqInkTRg

not

is metransit ticollector of definitioncorrect

toalproportionexactly not is )(

)/1(

metransit ticollector reduced

collector ofpart early in )( increases

,scattering L- reducescurrent Increased

cc

0

c

base

c

base

c

T

ccbase

I

Q

I

Q

Idxxv

TxIQ

xv

C

Nakajima, H. "A generalized expression for collector transit time of HBTstaking account of electron velocity modulation," Japanese Journal ofApplied Physics, vo. 36, Feb. 1997, pp. 667-668

T. Ishibashi

Transit time Modulation Causes Ccb Modulation

),(//1)(constant0 cbccbc

T

celectronsbase

holesbase VIfTAVdxTxAxqnQQ c

cb

f

c

cb

c

holesbasef

cb

holesbasecb VI

C

I

Q

V

QC

Camnitz and Moll, Betser & Ritter, D. Root holesbaseb ΔQI ,

E

drift collectorbase

-

+

+

+

+

-

-

-

--

-

-

-2

-1

0

1

2

0 100 200 300 400

eV

nm

L

-2

-1

0

1

2

0 100 200 300 400

eV

nm

0 0 ccbcbf ICV

:Modulation Velocity Collector

0 0 ccbcbf ICV

: Effect Kirk

2

3

4

5

6

7

8

0 2.5 5 7.5 10 12.5

Ccb

/Ae (

fF/

m2 )

Je (mA/m2)

-0.2 V

0.0 V

0.2 V

Vcb

= 0.6 V

cbb

cb

Vτ

C

by of modulation and-

collector into pushout base-

both to due is in Increase

100

200

300

400

500

0 2 4 6 8 10 12

f (

GH

z)

Je (mA/um2)

f, -0.3 V

cb

0.0 Vcb

-0.2 Vcb

0.2 Vcb

0.6 Vcb

DHBTs InP in effect weak-

SHBTs InGaAs in effect strong-

reduced with in Increase cbcbc CVτ

Emitter-Base Junction Effects

Electron degeneracy contributes 1 - μm2

equivalent series resistance

10-3

10-2

10-1

100

101

102

-0.3 -0.2 -0.1 0 0.1 0.2

J(m

A/u

m^2

)

Vbe

-

Fermi-Dirac

Equivalent series resistance approximation

Boltzmann

)(

)(

xnq

J

x

xE

n

fn

Space-charge storage

need thin layer to avoid substantial charge storage delays

Voltage drops in depletion region

need thin layer &high electron density ).08.0/(emitter InPfor

eV 1.0m

mA130

2

)(*

limit degenerateHighly

0*

2

2

32

2

mm

EE

EEqmJ

cf

cf

RodwellLundstrom.

RC parasitics

Simple Device Physics: Resistance

Good approximation for contactwidths less than 2 transfer lengths.

A

TR bulk

bulk resistance

AR contact

contact resistance-perpendicular

L

W

AR sheet

contact

3

'

contact resistance- parallel

HBT RC Parasitics

base contact width < 2 transfer lengths

→ simple analysis

Limiting case of Pulfrey / Vaidyanathanfmax model.

HBT RC Parasitics

emitteremittercontactex AR /,

Eesspread LWR 12/ ELlength emitter

Egapsgap LWR 4/

Ebcscontactspread LWR 6/,

contactsbasebcbasecontactcontact AWR _, /

cemitterecb TAC /,

cgapgapcb TAC /,

ccontactsbasecontactcb TAC /_,

Base-Collector Time Constant & Fmax.

where8max

cbibbCR

ff

)(

)2/(

,,

,,

,

spreadgapcontactspreadcontactecb

gapcontactspreadcontactgapcb

contactcontactcbcbibbcb

RRRRC

RRRC

RCCR

Relationship to Equivalent Circuit Model

contactspreadcontactgapspreadbb RRRRR ,

contactcbgapcbecbcbicbx CCCCC ,,,

)(

)2/(

,,

,,,

spreadgapcontactspreadcontactecb

gapcontactspreadcontactgapcbcontactcontactcbcbibb

RRRRC

RRRCRCCR

Device Design

Device Scaling

Simple Device Physics: Thermal Resistance

Exact

L

W

WK

W

L

LKR

th

thth

1

1

sinh1

sinh1

Carslaw & Jaeger 1959

LKW

L

LKR

ththth

1ln

1

junctionnear

flowheat lcylindrica

Long, Narrow StripeHBT Emitter, FET Gate

junction fromfar

flowheat spherical

LKLKR

ththth

1

4

1

surfacenear

flowheat planar

Square ( L by L ) IC on heat sink

surface fromfar

flowheat spherical

Bipolar Transistor Design eW

bcWcTbT

nbb DT 22

satcc vT 2

ELlength emitter

eex AR /contact

2through-punchce,operatingce,max cesatc TVVAvI /)(,

contacts

contactsheet 612 AL

W

L

WR

e

bc

e

ebb

e

e

E W

L

L

PT ln1

cccb /TAC

Bipolar Transistor Design: Scaling eW

bcWcTbT

nbb DT 22

satcc vT 2

ELlength emitter cccb /TAC

eex AR /contact

2through-punchce,operatingce,max cesatc TVVAvI /)(,

contacts

contactsheet 612 AL

W

L

WR

e

bc

e

ebb

e

e

E W

L

L

PT ln1

parameter change

collector depletion layer thickness decrease 2:1

base thickness decrease 1.414:1

emitter junction width decrease 4:1

collector junction width decrease 4:1

emitter contact resistance decrease 4:1

current density increase 4:1

base contact resistivity decrease 4:1

Changes required to double transistor bandwidth:

Linewidths scale as the inverse square of bandwidth because thermal constraints dominate.

eW

bcWcTbT

ELlength emitter

Bipolar Transistor Scaling Laws

0

20

40

60

80

100

120

140

100 200 300 400 500 600 700

jun

ctio

n t

em

pe

ratu

re r

ise

, K

elv

in

master-slave D-Flip-Flop clock frequency, GHz

substrate: cylindrical+spherical regions

substrate: planar region

package

total

Thermal Resistance Scaling : Transistor, Substrate, Package

2substrate

2/11ln

D

DT

K

P

DLK

P

W

L

LK

PT sub

InPEInPe

e

EInP

junctionnear

flowheat lcylindrica

eLr for

flow spherical

2/for

flowplanar

HBTDr

callylogarithmi

increases

variation

antinsignificconstant is if

lly quadratica increases

subT

.)(bandwidth

as scales

density,Power

h.1/bandwidt

as scale

lenghts Wiring

2

chipCu

chippackage WK

PT

1

4

1

)/GHz 150( m 40 clocksub fT

IC CML HBT-2000

0

20

40

60

80

100

120

140

100 200 300 400 500 600 700

jun

ctio

n t

em

pe

ratu

re r

ise

, K

elv

in

master-slave D-Flip-Flop clock frequency, GHz

substrate: cylindrical+spherical regions

substrate: planar region

package

total

Thermal Resistance Scaling : Transistor, Substrate, Package

2substrate

2/11ln

D

DT

K

P

DLK

P

W

L

LK

PT sub

InPEInPe

e

EInP

junctionnear

flowheat lcylindrica

eLr for

flow spherical

2/for

flowplanar

HBTDr

callylogarithmi

increases

variation

antinsignificconstant is if

lly quadratica increases

subT

.)(bandwidth

as scales

density,Power

h.1/bandwidt

as scale

lenghts Wiring

2

chipCu

chippackage WK

PT

1

4

1

)/GHz 150( m 40 clocksub fT

IC CML HBT-2000Probable best solution: Thermal Vias ~500 nm below InP subcollector...over full active IC area.

InP Bipolar Transistor Scaling Roadmap

emitter 512 256 128 64 32 nm width16 8 4 2 1 m2 access

base 300 175 120 60 30 nm contact width, 20 10 5 2.5 1.25 m2 contact

collector 150 106 75 53 37.5 nm thick, 4.5 9 18 36 72 mA/m2 current density4.9 4 3.3 2.75 2-2.5 V, breakdown

f 370 520 730 1000 1400 GHzfmax 490 850 1300 2000 2800 GHz

power amplifiers 245 430 660 1000 1400 GHz digital 2:1 divider 150 240 330 480 660 GHz

industry university→industry

university2007-8

appearsfeasible

maybe

eW

bcWcTbT

Can we make a 1 THz SiGe Bipolar Transistor ?

InP SiGeemitter 64 18 nm width

2 1.2 m2 access

base 64 56 nm contact width, 2.5 1.4 m2 contact

collector 53 15 nm thick 36 125 mA/m2 2.75 ??? V, breakdown

f 1000 1000 GHzfmax 2000 2000 GHz

PAs 1000 1000 GHz digital 480 480 GHz(2:1 static divider metric)Assumes collector junction 3:1 wider than emitter.Assumes SiGe contacts 2:1 wider than junctions

Simple physics clearly drives scaling transit times, Ccb/Ic → thinner layers, higher current density high power density → narrow junctions small junctions→ low resistance contacts

Key challenge: Breakdown 15 nm collector → very low breakdown

(also need better Ohmic contacts)

HBT Design For Digital & Mixed-Signal Performance

from charge-control analysis:

)./5.05.0(

)/5.05.05.0(

)/5.05.0)(/(

)66)(/(

LCfcbijebb

LCfcbicbxex

LCfcbicbxjeC

fcbicbxjeCLgate

VICCR

VICCR

VICCCqIkT

CCCIVT

InP HBT: Status

0

200

400

600

800

1000

0 200 400 600 800 1000

Teledyne DBHT

UIUC DHBT

NTT DBHT

ETHZ DHBT

UIUC SHBT

UCSB DHBT

NGST DHBT

HRL DHBT

IBM SiGe

Vitesse DHBT

f ma

x (G

Hz)

ft (GHz)

600 GHz

500GHz maxff

Updated Sept. 2008

800 GHz

900 GHz

700 GHz

400GHz

InP DHBTs: September 2008

)(

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),/(

),/(

hence ,

:digital

gain, associated ,F

:amplifiers noise low

mW/

gain, associated PAE,

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2/) (

alone or

min

1max

max

max

max

cb

cbb

cex

ccb

clock

ττ

VIR

VIR

IVC

f

m

ff

ff

ff

ff

:metrics better much

:metrics popular

250 nm

600nm

350 nm

250 nm

125 nm

512 nm InP DHBT

Production

DDS IC: 4500 HBTs 20-40 GHz op-amps

500 nm mesa HBT 150 GHz M/S latches 175 GHz amplifiers

LaboratoryTechnology

Teledyne / BAE Teledyne / UCSB

UCSB UCSB / Teledyne / GCS

500 nm sidewall HBT

f = 405 GHz

fmax = 392 GHz

Vbr, ceo = 4 V

Teledyne

20 GHz clock53-56 dBm OIP3 @ 2 GHzwith 1 W dissipation

( Teledyne )

Z. GriffithM. UrteagaP. RowellD. PiersonB. BrarV. Paidi

256 nm GenerationInP DHBT

0

10

20

30

109 1010 1011 1012

109

101

0

101

1

1012

dB

Hz

f = 560 GHz

fmax

= 560 GHz

U

H21

0

10

20

30

40

109 1010 1011 1012

dB

Hz

UH21

f = 424 GHz

fmax

= 780 GHz

0

5

10

15

20

0 1 2 3 4V

ce

mA

/m

20

10

20

30

40

109 1010 1011 1012

dB

Hz

U

H21

ft = 660 GHz

fmax

= 218 GHz

0

10

20

30

0 1 2 3

mA

/m

2

Vce

150 nm thick collector

70 nm thick collector

60 nm thick collector

200 GHz master-slavelatch design

Z. Griffith, E. Lind

J. Hacker, M. Jones

324 GHzAmplifier

324 GHz Medium Power Amplifiers in 256 nm HBT

ICs designed by Jon Hacker / Teledyne

Teledyne 256 nm process flow-

Hacker et al, 2008 IEEE MTT-S

~2 mW saturated output power

0

10

20

30

40

Cu

rre

nt,

mA

-20

-10

0

10

20

Gai

n (

dB

), P

ow

er

(dB

m),

PA

E (

%)

-20 -15 -10 -5 0 5

Input Power (dBm)

O utput Pow er (dBm )

G ain (dB)

D ra in C urrent (m A )

P AE (% )

128 / 64 / 32 nm HBT Technologies

Conventional ex-situ contacts are a mess

textbook contact with surface oxide

Interface barrier → resistance

Further intermixing during high-current operation → degradation

with metal penetration

THz transistor bandwidths: very low-resistivity contacts are required

Improvements in Ohmic Contacts

128 nm generation requires ~ 4 - μm2 emitter & base resistivities

64 nm generation requires ~ 2 - μm2

Contacts to N-InGaAs*:Mo MBE in-situ 2.2 (+/- 0.5) - μm2

TiW ex-situ / NH4 pre-clean ~2.2 - μm2

variable between process runs

Contacts to P-InGaAs:Mo MBE in-situ below 2.5 - μm2

Pd/Ti... ex-situ ~4 - μm2

...far better contacts coming...

*measured emitter resistance remains higher than that of contacts.

A.. CrookV. JainA. BaraksharM. WisteyU. Singisetti

S. Bank

Mo Emitter Contacts: Robust Integration into Process Flow

Proposed Process Integration:M. WisteyA. BaraksharU. SingisetttiV. Jain

Process Must Change Greatly for 128 / 64 / 32 nm Nodes

Undercutting of emitter ends

control undercut→ thinner emitter thinner emitter

→ thinner base metalthinner base metal→ excess base metal resistance

{101}A planes: fast

{111}A planes: slow

128 nm Emitter Process: Dry Etched Metal & Semiconductor

SiO2

TiW

InGaAs n++

InGaAs p++ Base

InP n

CrSF6/Ar ICP Cl2/N2 ICPSiNx sidewall

Wet Etch

HCl:H3PO4BHF

Ti

a b c d e

InGaAs p++ Base InGaAs p++ Base InGaAs p++ Base InGaAs p++ Base

InP n

InGaAs n++ InGaAs n++

Litho patternmetal

sidewall dry etch wet etch

0

10

20

30

109 1010 1011 1012

10

9

10

10

101

1

10

12

dB

Hz

f = 560 GHz

fmax

= 560 GHz

U

H21

0

5

10

15

20

0 1 2 3 4V

cem

A/

m2

results @ c.a. 200 nm emitter metal width

E. Lind

Planarization E/B Processes for 64 & 32 nm

Planarization boundary

E; LobisserV. JainG. Burek

III-V FET Scaling

Simple FET ScalingGoal double transistor bandwidth when used in any circuit → reduce 2:1 all capacitances and all transport delays

→ keep constant all resistances, voltages, currents

All lengths, widths, thicknesses reduced 2:1

S/D contact resistivity reduced 4:1

oxgm TvWg /~/

oxgggs TLWC /~/

~/, gfgs WC

subcgsb TLWC /~/

If Tox cannot scale with gate length,

Cparasitic / Cgs increases,

gm / Wg does not increase

hence Cparasitic /gm does not scale

~/ ggd WC

FET scaling: Output Conductance & DIBL effects) D.O.S.neglects expression ( gsC

gchd WC ~

dschdgsgsd VCVCQQI where/

/~ oxgggs TLWC

transconductance

→ Keep Lg / Tox constant as we scale Lg

output conductance

parameter change

gate length decrease 2:1

gate dielectric capacitance density increase 2:1

gate dielectric equivalent thickness decrease 2:1

channel electron density increase 2:1

source & drain contact resistance decrease 4:1

current density (mA/m) increase 2:1

Changes required to double transistor bandwidth:

FET Scaling Laws

GW widthgate

GL

III-V MOSFETs for VLSI

What is it ?MOSFET with an InGaAs channel

What are the problems ?low electron effective mass→ constraints on scaling !must grow high-K on InGaAs, must grow InGaAs on Si

Our focus today is III-V FET scaling generally

Why do it ?low electron effective mass→ higher electron velocitymore current, less charge at a given insulator thickness & gate lengthvery low access resistance

Low Effective Mass Impairs Vertical Scaling

Shallow electron distribution needed for high gm / Gds ratio.

./ 2*2wellTmL

Only one vertical state in well. Minimum ~ 5 nm well thickness.→ constrains gate length scaling.

For thin wells, only 1st state can be populated.For very thin wells, 1st state approaches L-valley.

Energy of Lth well state

Density-Of-States Capacitance

Two implications:

- With Ns >1013/cm2, electrons populate satellite valleys - Transconductance limited by finite state density

and n is the # of band minima

)//( 2* nmnEE swellf

2*2 / where nmqcdos

dosswellf cVV /

Fischetti et al, IEDM2007

Solomon & Laux , IEDM2001

motion) nalbidirectio(

Drive Current in the Ballistic & Degenerate Limits

2/3*

,

2/1*2/3

)/()/(1 where,

V 1m

mA84

ooxodos

othgs

mmncc

mmnK

VVKJ

0

0.05

0.1

0.15

0.2

0.25

0.01 0.1 1

K

m*/mo

1.0 nm, n=1

0.8 nm, n=1

0.7 nm, n=6 0.4 nm, n=6

EOT includes wavefunction depth (0.5 nm for 3.5 nm InGaAs well)

n = # band minimacdos,o = density of states capacitance for m*=mo & n=1

Error bars on Si data points correct for (Ef-Ec)>> kT approximation

HEMT Scaling Challenge: Low Gate Barrier

Tunneling through barrier→ sets minimum thickness

Source DrainGate

Ec

Ewell-

EF

Ec

Ewell-

EF

Gate barrier is low: ~0.6 eV

Emission over barrier→ limits 2D carrier density

K Shinohara

eV 6.0~)( ,cm/10At 213cfs EEN

Ec

Ewell-

EF

N+ caplayer

HEMT Scaling Challenge: High Access Resistance

low leakage: need high barrier under gate

Source DrainGate

Ec

Ewell-

EF

Gate barrier also lies under source / drain contacts

low resistance: need low barrier under contacts

widegap barrier layer

N+ layer

K Shinohara

THz III-V FET Scaling: What Must Be Done

As gate length is reduced...

channel thickness should be reduced...

barrier thickness should be reduced...

target gm/Wg and Id/Wg

should be increased...

source and drain access resistivity should be reduced...

We face serious difficulties in doing these.

parameter change

gate length decrease 2:1

gate dielectric capacitance density increase 2:1

gate dielectric equivalent thickness decrease 2:1

channel electron density increase 2:1

source & drain contact resistance decrease 4:1

current density (mA/m) increase 2:1

Changes required to double transistor bandwidth:

FET Scaling Laws

GW widthgate

GL

substrate

barrier

sidewall

metal gate

quantum well / channel

gate dielectric

N+ source N+ drain

source contact drain contact

A MOSFET Might Scale Better than a HEMT

no gate barrier under S/D contacts

high-K gatebarrier

Overlap between gateand N+ source/drain

Interconnects

kz

Parasitic slot mode

-V 0V +V

0V

Coplanar WaveguideNo ground viasNo need (???) to thin substrate

Parasitic microstrip mode

+V +V +V

0V

Hard to ground IC to package

substrate mode coupling or substrate losses

ground plane breaks → loss of ground integrity

Repairing ground plane with ground straps is effective only in simple ICsIn more complex CPW ICs, ground plane rapidly vanishes → common-lead inductance → strong circuit-circuit coupling

40 Gb/s differential TWA modulator drivernote CPW lines, fragmented ground plane

35 GHz master-slave latch in CPWnote fragmented ground plane

175 GHz tuned amplifier in CPWnote fragmented ground plane

poor ground integrity

loss of impedance control

ground bounce

coupling, EMI, oscillation

III-V:semi-insulating substrate→ substrate mode coupling

Siliconconducting substrate→ substrate conductivity losses

kz

Classic Substrate Microstrip

Strong coupling when substrate approaches ~d / 4 thickness

H

W Thick Substrate → low skin loss

Hrskin 2/1

1

Zero ground inductance in package

a

Brass carrier andassembly ground

interconnectsubstrate

IC with backsideground plane & vias

near-zeroground-groundinductance

IC viaseliminateon-wafergroundloops

High via inductance

12 pH for 100 m substrate -- 7.5 @ 100 GHz

TM substrate mode coupling

Line spacings must be ~3*(substrate thickness)

lines must be widely spaced

ground vias must be widely spaced

all factors require very thin substrates for >100 GHz ICs→ lapping to ~50 m substrate thickness typical for 100+ GHz

No ground planebreaks in IC

fewer breaks in ground plane than CPW

III-V MIMIC Interconnects -- Thin-Film Microstrip

narrow line spacing → IC density

... but ground breaks at device placements

still have problem with package grounding

thin dielectrics → narrow lines → high line losses → low current capability → no high-Zo lines

H

W

HW

HZ

r

oo 2/1

~

...need to flip-chip bond

no substrate radiation, no substrate losses

InP mm-wave PA (Rockwell)

No breaks in ground plane

III-V MIMIC Interconnects -- Inverted Thin-Film Microstrip

narrow line spacing → IC density

... no ground breaks at device placements

still have problem with package grounding

thin dielectrics → narrow lines → high line losses → low current capability → no high-Zo lines

...need to flip-chip bond

Some substrate radiation / substrate losses

InP 150 GHz master-slave latch

InP 8 GHz clock rate delta-sigma ADC

No clean ground return ? → interconnects can't be modeled !

35 GHz static divider interconnects have no clear local ground return interconnect inductance is non-local interconnect inductance has no compact model

InP 8 GHz clock rate delta-sigma ADC

8 GHz clock-rate delta-sigma ADC thin-film microstrip wiring every interconnect can be modeled as microstrip some interconnects are terminated in their Zo some interconnects are not terminated ...but ALL are precisely modeled

VLSI Interconnects with Ground Integrity & Controlled Zo

negligible breaks in ground plane

narrow line spacing → IC density

negligible ground breaks @ device placements

still have problem with package grounding

thin dielectrics → narrow lines → high line losses → low current capability → no high-Zo lines

...need to flip-chip bond

no substrate radiation, no substrate losses

Conclusions

Few-THz Transistors

Scaling limits: contact resistivities, device and IC thermal resistances.

Few-THz InP Bipolar Transistors: can it be done ?

62 nm (1 THz f, 1.5 THz fmax ) scaling generation is feasible.700 GHz amplifiers, 450 GHz digital logic

Is the 32 nm (1 THz amplifiers) generation feasible ?

Few-THz InP Field-Effect Transistors: can it be done?

challenges are gate barrier, vertical scaling,source/drain access resistance, increased gm and drive current.

2DEG carrier concentrations must increase.

S/D regrowth offers a path to lower access resistance.

Solutions needed for gate barrier: maybe even MOSFET ?

What Would We Do With Them ?

THz amplifiers→ THz radios→ imaging, sensing, communications

precision analog design at microwave frequencies→ high-performance receivers

500 GHz digital logic→ fiber optics

Higher-Resolution Microwave ADCs, DACs, DDSs