frequency limits of inp-based integrated circuits [email protected] 805-893-3244, 805-893-5705...
TRANSCRIPT
![Page 1: Frequency Limits of InP-based Integrated Circuits rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax Collaborators (III-V MOS) A. Gossard, S. Stemmer,](https://reader033.vdocuments.us/reader033/viewer/2022052510/56649f495503460f94c6b453/html5/thumbnails/1.jpg)
Frequency Limits of InP-based Integrated Circuits
[email protected] 805-893-3244, 805-893-5705 fax
Collaborators (III-V MOS)
A. Gossard, S. Stemmer, C. Van de Walle University of California Santa Barbara
P. Asbeck, A. Kummel, Y. Taur, University of California San Diego
J. Harris, P. McIntyre,Stanford University
C. Palmstrøm,University of Minnesota
M. Fischetti University of Massachusetts Amherst
Plenary, Indium Phosphide and Related Materials Conference, May 15-18, Matsue, Japan
Sponsors
J. Zolper, S. Pappert, M. RoskerDARPA (TFAST, SWIFT, FLARE)
D. Purdy, I. MackOffice of Naval Research
Kwok Ng, Jim HutchbySemiconductor Research Corporation
Mark Rodwell , E. Lind, Z. Griffith, S. R. Bank, A. M. CrookU. Singisetti, M. Wistey, G. Burek, A.C. GossardUniversity of California, Santa Barbara
Collaborators (HBT)
M. Urteaga, R. Pierson , P. Rowell, M-J Choe, B. BrarTeledyne Scientific Company
X. M. Fang, D. Lubyshev, Y. Wu, J. M. Fastenau, W.K. Liu International Quantum Epitaxy, Inc.
S. MohneyPenn State University
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Specific Acknowledgements
(Prof.) Erik Lind
125 nm HBTsprocess technologytheory / epi design
Dr. Zach Griffith
500 & 250 nm HBTs150 GHz Logic100 GHz op-amps
Dr. Mark Wistey
InGaAs MOSFETprocess technologytheory / epi design
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THz Transistors are coming soon; both InP & Silicon
InP Bipolars: 250 nm generation: → 780 GHz fmax , 424 GHz f, 4-5 V BVCEO
125 nm & 62 nm nodes→ ~THz devices
IBM IEDM '06: 65 nm SOI CMOS → 450 GHz fmax , ~1 V operation Intel Jan '07: 45 nm / high-K / metal gate
continued rapid progress → continued pressure on III-V technologies
If you can't beat them, join them ! unclear if Si MOSFETs will work well at sub-22-nm gate length
InGaAs/InAs/InP channels under serious investigation for CMOS VLSI.Datta, DelAlamo, Sadana, ...
0
10
20
30
40
109 1010 1011 1012
dB
Hz
U
H21
f = 424 GHz
fmax
= 780 GHz
Z. Griffith
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THz InP vs. near-THz CMOS: different opportunities
65 / 45 / 33 / 22 ... nm CMOSvast #s of very fast transistors ... having low breakdown, sloppy DC parameters what NEW mm-wave applications will this enable ?
massive monolithic mm-wave arrays→ 1 Gb/s over ~1 km mm-wave MIMO
DC parameters limit analog precision...
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THz InP vs. near-THz CMOS: different opportunities
InP HBT: THz bandwidths, good breakdown, analog precision
10-12
10-10
10-8
10-6
10-4
10-2
0 0.25 0.5 0.75 1
I c , I
b (
A)
Vbe
(V)
Ic
Ib
340 GHz, 70 mW amplifiers (design)In future: 700 or 1000 GHz amplifiers ?
0
10
20
30
40
109 1010 1011 1012
dB
Hz
U
H21
f = 424 GHz
fmax
= 780 GHz &
200 GHz digital logic (design)In future: 450 GHz clock rate ?
30-50 GHz gain-bandwidth op-amps→ low IM3 @ 2 GHz In future: 200 GHz op-amps for low-IM3 10 GHz amplifiers?
Z. Griffith
M. Urteaga (Teledyne)
Z. Griffith
M. Jones
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Transistor Benchmarks
fmax matters
0
10
20
30
40
109 1010 1011 1012
dB
Hz
U
H21
ft = 660 GHz
fmax
= 218 GHz
no gain above 218 GHz
Tuned amplifiers: fmax sets bandwidth
Mixed-signal: CcbV/ Ic , CjeV/ Ic , RexIcV , RbbIcV , f
0
2
4
6
8
10
0 1 2 3 4 5 6 7 8
J e (m
A/
m2 )
Vce
(V)
6.8 V BVCEO
BVCEO is not the only voltage limit
0
2
4
6
8
10
0 1 2 3 4 5 6 7 8
J e (m
A/
m2 )
Vce
(V)
!
Need Safe Operating Area...at least BVceo/2 at Jmax/2
thermal resistance, high-current breakdownhigh-temperature operation (~75 C) ?
Goal is >1 THz fand fmax
<50 fs CV / I charging delays → emphasize InP-collector DHBTs
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HBT Scaling Laws
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0
100
200
300
400
500
600
700
800
0 100 200 300 400 500 600 700 800
RSC
UIUC DHBT
NTT
Fujitsu HEMT
SFU
UIUC SHBT
UCSB
NGST
Pohang SHBT
HRL
IBM SiGe
Vitesse
f max
(G
Hz)
ft (GHz)
500 GHz400 GHz300 GHz200 GHz maxff
Updated March 2007
600 GHz
Teledyne
InP DHBTs: May 2007
)(
),/(
),/(
),/(
hence ,
:digital
gain, associated ,F
:amplifiers noise low
mW/
gain, associated PAE,
:amplifierspower
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alone or
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1max
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max
max
cb
cbb
cex
ccb
clock
ττ
VIR
VIR
IVC
f
m
ff
ff
ff
ff
:metrics better much
:metrics popular
250-300nm
600nm
300-400nm
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HBT Scaling Roadmaps
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emitter 500 nm width 16 m2 contact
base 300 width, 20 m2 contact
collector 150 nm thick, 5 mA/m2 current density5 V, breakdown
f 400 GHzfmax 500 GHz
power amplifiers 250 GHz digital clock rate 160 GHz(static dividers)
2005: InP DHBTs @ 500 nm Scaling Generation
✓✓
✓
✓
✓
✓
✓✓
✓
✓✓
(178 GHz)
(150 GHz)
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emitter 500 250 nm width 16 9 m2 access
base 300 150 width, 20 10 m2 contact
collector 150 100 nm thick, 5 10 mA/m2 current density5 3.5 V, breakdown
f 400 500 GHzfmax 500 700 GHz
power amplifiers 250 350 GHz digital clock rate 160 230 GHz(static dividers)
2006: 250 nm Scaling Generation, 1.414:1 faster
✓✓
✓
✓
✓
✓
✓✓
✓(425 GHz)
(780 GHz)
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emitter 500 250 125 nm width 16 9 4 m2 access
base 300 150 75 width, 20 10 5 m2 contact
collector 150 100 75 nm thick, 5 10 20 mA/m2 current density5 3.5 3 V, breakdown
f 400 500 700 GHzfmax 500 700 1000 GHz
power amplifiers 250 350 500 GHz digital clock rate 160 230 330 GHz(static dividers)
2007: 125 nm Scaling Generation → almost-THz HBT
✓✓
✓✓
✓
✓✓
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emitter 500 250 125 63 nm width 16 9 4 2.5 m2 access
base 300 150 75 70 nm width, 20 10 5 5 m2 contact
collector 150 100 75 53 nm thick, 5 10 20 35 mA/m2 current density5 3.5 3 2.5 V, breakdown
f 400 500 700 1000 GHzfmax 500 700 1000 1500 GHz
power amplifiers 250 350 500 750 GHz digital clock rate 160 230 330 450 GHz(static dividers)
2008-9: 65 nm Scaling Generation→beyond 1-THz HBT
✓
✓
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HBT Scaling Challenges
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Scaling challenges: What looks easy, what looks hard ?
key device parameter required change
collector depletion layer thickness decrease 2:1
base thickness decrease 1.414:1
emitter junction width decrease 4:1
collector junction width decrease 4:1
emitter resistance per unit emitter area decrease 4:1
current density increase 4:1
base contact resistivity (if contacts lie above collector junction)
decrease 4:1
base contact resistivity (if contacts do not lie above collector junction)
unchanged
Hard:Thermal resistance (ICs)Emitter contact + access resistanceYield in deep submicron processesContact electromigration (?), dark-line defects (?)
Probably not as hard :Maintaining adequate breakdown for 3 V operation...
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Temperature Rise: Transistor, Substrate, Package
2substrate
2/11ln
D
DT
K
P
DLK
P
W
L
LK
PT sub
InPEInPe
e
EInP
junctionnear
flowheat lcylindrica
eLr for
flow spherical
2/for
flowplanar
HBTDr
callylogarithmi
increases
variation
antinsignificconstant is if
lly quadratica increases
subT
ICs digital
GHz 150
eddemonstrat
from scaled etc.
densities,power
rates,clock
lenghts, Wiring
chipCu
chippackage WK
PT
2
11
0
50
100
150
100 200 300 400 500 600 700
jun
ctio
n t
em
pe
ratu
re r
ise
, K
elv
in
master-slave D-Flip-Flop clock frequency, GHz
substrate: planar region
package
total
substrate: cylindrical + spherical regions
)/GHz 150( m 40 clocksub fT
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HBTs:
500 nm Generation
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500 nm Generation in Manufacturing: Teledyne Self-aligned Dielectric Sidewall Process
Emitter Contact
Base Contact
Dielectric Sidewall
10 11 120
10
20
30
40
Frequency (GHz)
|H21
|(re
d), U
(blu
e) (
dB)
f = 405GHz
fmax = 392 GHz
RF Gains
JE = 6.5 mA/um2
VCE = 1.5 V
No short-circuits from liftoff defects.
Emitter can be much thinner→ small etch undercut.
M. Urteaga et al, 2004 IEEE Device Research Conference, June 21-23, 2004
Electroplate emitter contactEtch emitter semiconductor
Dielectric sidewall depositionBase contact patterning
Selectively deposit base metal
emitterEB grade
base
emittermetal
basemetal
dielectricsidewallspacer base contact
window
c.f. also Minh Le et al IEDM 2006 (Vitesse)
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Example ICs in 500 nm HBT
142 GHz, 800 mWmaster/slave latch
Fe
N+
S.I.
N+N+ N+Fe
mesa HBT UCSB
sidewall /pedestal HBTTeledyne
128 GHz, 206 mW master/slave latch
175 GHz, 7.5 mW medium-power amp.
mesa HBT UCSB
Other Results:160 Gb/s multiplexer (T. Swahn et al, Chalmers / Vitesse)~5000-HBT direct-digital frequency synthesis ICs (Vitesse, Teledyne)
V. PaidiZ. Griffith
M. UrteagaP. Rowell
D. PiersonB. Brar
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HBTs:
250 nm Generation
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250 nm scaling generation InP DHBTs
Emitter contact resistance 5 m2 Base contact resistance is < 5 m2
Z. GriffithE. Lind
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DHBTs: 250 nm Scaling Generation
0
10
20
30
40
109 1010 1011 1012
dB
Hz
U
H21
ft = 660 GHz
fmax
= 218 GHz
0
10
20
30
0 1 2 3
mA
/m
2
Vce
150 nm thick collector 60 nm thick collector
0
10
20
30
40
109 1010 1011 1012
dB
Hz
U
H21
f = 424 GHz
fmax
= 780 GHz
Emitter access: 5.1 m2
Base contact: 6.3 m2
Z. GriffithE. Lind
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Example IC Designs in 250 nm HBT
200 GHz master-slave latches
...fabrication on hold...
340 GHz, 70 mW, medium-power amplifiers
...fabrication planned summer/fall 2007
M. JonesZ. Griffith
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125 nm InP HBTdevelopment
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Emitter Access Resistance
125 nm generation requires 5 - μm2 emitter resistivities
65 nm generation requires 1-2 - μm2
Recent Results:ErAs/Mb MBE in-situ 1.5 - μm2 Mb MBE in-situ 0.6 - μm2
TiPdAu ex-situ 0.5 - μm2
TiW ex-situ 0.7 - μm2
Degeneracy contributes 1 - μm2
10-3
10-2
10-1
100
101
102
-0.3 -0.2 -0.1 0 0.1 0.2
J(m
A/u
m^2
)
Vbe
-
Fermi-Dirac
Equivalent series resistance approximation
Boltzmann
20 nm emitter-base depletion layer contributes 1 - μm2 resistance
)(
)(
xqn
J
x
xE fn
Te=0 nm
Te=100 nm
Erik LindAdam Crook
Seth BankUttam Singisetti
10 nm steps
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1 2 3 4 510
-6
10-4
10-2
100
102
104
106
Vcb (V)
Cur
rent
(A/c
m2)
Epitaxial Layer Development for 125 nm Generation
InGaAs base: low sheet resistivity, low transit time, but collector must be graded
Vcb
= 0.0 V-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
0 10 20 30 40 50 60 70 80
eV
nm
collectorbase
0
10
20
30
0 1 2 3
mA
/m
2
Vce
low-current breakdown dominated by tunneling in setback layer
Erik Lind
1) less superlattice periods...
2) thinner (sub-monolayer) superlattice periods→ random alloy grade
3) thin GaAs/InGaAs strained-layer grade
DC data shows expected increase in breakdown.Transport (RF) data is pending.
: Zach Griffith
B-C grade redesign: thin the setback, thin the grade
calculation-2.5-2
-1.5-1
-0.50
0.51
1.5
0 20 40 60 80 100
eV
nm
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125 nm Emitter Process
Blanket sputter deposition TiW emitter contact metalOptical lithography → ICP reactive-ion etchingICP RIE etch of InGaAs/InP semiconductor,Selective wet etch to base
Erik Lind
125 nm emitter 500 nm undercut at emitter ends
61 nm junction:40 nm lateral undercut
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UCSB 125 nm DHBT Development
125 nm emitter process
EmitterMetal
InGaAs/InP
emitter contact resistivity ~ 0.7 - μm2
base contact resistivity ~ 3-5 -μm2
Target performance ~ 700-900 GHz simultaneous ft & fmax , 3-4 V breakdown
Erik LindAdam Crook
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How might we build the 62.5 nm HBT ?
Mesa process: control of etch undercut with dry+wet process
Alternatives:- dielectric sidewall process- sidewall process with extrinsic base regrowth: allows thinner base
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InP-based FETs;
MOSFETs & HEMTs
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InP-based HEMTs & MOSFETs : Why ?
20 40 60 80 100 120 140 160 1800 200
1
2
3
4
5
6
7
0
8
Frequency, GHz
Min
imum
Nois
e F
igur
e, d
B
GHz 500f
GHz 200f
A ~2.5:1 f / fsignal ratio
provides 3 dB noise figure.
Low-noise 100-300 GHz preamplification is a key application for 1-THz-f HEMTs
InGaAs/InP HEMTs: mm-wave low-noise amplifiers
f
fRRRgF igsmi )(1min
InGaAs/InP MOSFETs: post-22-nm VLSI (?)
Higher mobility and peak electron velocity than in Silicon
→ higher ( Id / Wg ) and lower ( CV / I ) at sub-22-nm scaling (?)
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Some Encouraging Initial Data . . .-- non-parabolic bands (variable m*) significantly increase feasible sheet charge
Asbeck / Fischetti / Taur simulate drive currents much larger than for constant-m* model
-- mobilities seem to be acceptable even in thin wells
M. Wisteypreliminary data
. . . and our current device designs . . .
P + substrate
barrier
metal gate
undopedsubstrate
InGaAs channel
dielectricN+ regrowth N+ regrowth
source contact drain contact
undopedsubstrate
InP sub-channel
device design and fabrication:Asbeck group: UCSDTaur group: UCSDFischetti group: U. MassRodwell group: UCSBPalmstrøm group: U. Minn
well: 2.5 nm InGaAs, 2.5 nm InP
N+ InGaAs/InAs extrinsic source & drain by regrowth
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Frequency Limits of InP-based Integrated Circuits
Scaling limits: contact resistivities, device and IC thermal resistances.
InP Bipolar Transistors
62 nm (1 THz f, 1.5 THz fmax ) scaling generation is feasible.700 GHz amplifiers, 450 GHz digital logic
Is the 32 nm (1 THz amplifiers) generation feasible ?
InP Field-Effect Transistors
Low electron effective mass → difficulties with further scaling
Guarded optimism regarding 22 nm generation for VLSI
Serious difficulties beyond.
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(end)
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non-animated versions of the three
key scaling slides
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HBT scaling laws
eW
bcWcTbT
Goal: double transistor bandwidth when used in any circuit → keep constant all resistances, voltages, currents → reduce 2:1 all capacitances and all transport delays
vTDT bnbb /22 vTcc 2
ELlength emitter
cccb /TAC
ecex AR /2
, / ceKirkc TAI
contacts
c
e
bcs
e
esbb AL
W
L
WR
612
→ thin base ~1.414:1
→ thin collector 2:1
→ reduce junction areas 4:1
→ reduce emitter contact resistivity 4:1
(current remains constant, as desired )
→ reduce base contact resistivity 4:1
reduce widths 2:1 & reduce length 2:1 → constant Rbb reducing widths 4:1, keep constant length → reduced Rbb
EInPe
e
EInP LK
P
W
L
LK
PT
ln
need to reduce junction areas 4:1reduce widths 2:1 & reduce length 2:1 → doubles Treducing widths 4:1, keep constant length→ small T increase ✓
✓✓✓
Linewidths scale as the inverse square of bandwidth because thermal constraints dominate.
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Back-of-Envelope FET Scaling
wellwoxoxeq TTc 2//~/1
)(~ VVVWvcI thgsgexiteqd
/~ gexitLvV
2/1*)/(~ mkTvexit (non-degenerate)
ceq doubledthin layers 2:1
Goal double transistor bandwidth when used in any circuit → reduce 2:1 all capacitances and all transport delays
→ keep constant all resistances, voltages, currents
gexiteqm Wvcg ~ ✓gm , Id held constant reduce Wg 2:1
✓Cgs reduced 2:1 gggeqgs WWLcC 1~ dielectric fringing
✓(Cgd , Cs-b , Cd-b ) all reduced 2:1 gbdbsgd WCCC toalproportion all , ,
reduce Lg 2:1
✓(Rs , Rd ) held constant
g
DSs
DSg
cs W
L
LWR /
/
reduce Ls/d 2:1 ,reduce c 4:1
2:1 vertical scaling → 2:1 increased ( gm / Wg ) → 2:1 reduced Wg → 2:1 reduced fringing capacitances
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FETs no longer scale well
tunneling through oxide → high-K dielectrics (if feasible)
Low density of states limits drive current
density-of-states term dominates , limits ( gm / Wg )and ( Id / Wg )→ fringing & substrate capacitances no longer scale, can dominate over Cgs
wellwoxoxeeqgeqm TTmqcWvcg 2///)2(~/1 where~ *22
Solomon & Laux, 2001 IEDM
Thin layers & low effective mass limit channel sheet charge density
*/mqnEE swellf
*2 /1 mTEE wellcwell
high sheet-charge in thin well→ populate higher-mass band minima
infinite well approximation
Thin quantum wells have low mobility
62/ wellTWE
Li SST 2005; Gold et al, SSC 1987; Sakaki et al, APL 1987
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0
10
20
30
40
109 1010 1011 1012
dB
Hz
U
ft = 450 GHz,
fmax
= 490 GHz
h21
InP DHBT: 500 nm Scaling Generation
600 nm wide emitter, 120 nm thick collector, 30 nm thick base
Z. Griffith