multi-level gate networks nand and nor gates digital technology: enel211

Multi-Level Gate NetworksNAND and NOR Gates

Digital Technology: ENEL211

Outline

• Gate levels in circuit networks– Reducing levels

• Functionally complete sets

• Alternative AND/NAND and OR/NOR gates

• Designing NAND-only or NOR-only circuit networks

Levels of Gates in a Network

• The number of gates cascaded in series between a network input the output is referred to as the number of levels of gates

• Sum-of-products or product-of-sums expression yields a two level network

Note: Usually networks are driven from flip-flop devices so that variables and their compliments are available – therefore Inverters can be excluded from the level count of the network

Categories of Network

• AND-OR: 2 level with a level of AND gates followed by an OR gate at the output

• OR-AND: 2 level with level of OR gates followed by an AND gate at the output

• OR-AND-OR: 3 level with a level of OR gates followed by a level of AND gates then an OR gate at the output

• Network of AND and OR gates: multiple levels of AND and OR gate

Changing Levels in Networks

• Levels in AND-OR networks are (usually) increased by factoring the sum-of-products expression.

• Levels in OR-AND networks are (usually) increased by multiplying out terms in the product-of-sums expression

• Increasing the levels can bring about a reduction in the number of gates – which is good isn’t it?

Problems with Multiple Levels of Cascading

• Designers are concerned with the number of levels in networks

• Increasing the number levels of a Network will increase the time between change in input and output

• And slow down the operation of a digital system• Thus: the number of levels limited by propagation

delays of gates

A Four-Level Network

G

B

F

A

E

C

HX

D

Level 1Level 2Level 3Level 4

Analysis

• Network for X has 4 levels, 6 gates and 13 inputs• Partially multiplying out the expression gives rise

to a network with 3 levels, 6 gates and 19 inputs

HCFGABFGEDCEDABX

HFGEDCABX

)()(

]))[((

Equivalent 3 Level Network

BA

GFC

GFBA

B

D

E

X

Level 1Level 2Level 3

• No increase in the number of gates

• But would normally expect a trade-off between levels and gates

• Increase in the number inputs – but does this matter?

Realising Networks with a Single Gate Type

• Companies learned that AND-OR-NOT gates circuits could be implemented using only NAND or NOR gates

• Circuits implemented using a single gate type are generally faster and require less components

• Economies of scale: reduced costs due to bulk buying– Though this is not applicable nowadays due to low

price of integrated circuits

Functionally Complete Sets of Logic Gates

• A set of logic operations is said to functionally complete if any Boolean function can be expressed in terms of the operations in the set

Example: AND, OR and NOT

• Take the set of Boolean Operations:– AND, OR and NOT

• Since any Boolean function can be expressed in sum-of-products form

• And sum-of-products expressions only comprise of AND, OR and NOT operations

• The logical set of operations AND, OR and NOT is therefore functionally complete

The NAND operation isfunctionally Complete

AA

A

B

A+B

A

B

A.B

ABAB

BABA

AAA

Show that the NOR operation is also Functionally Complete

Design of minimum Two-Level NAND-NAND Network

• Find the minimum sum-of-products expression

• Draw the corresponding two-level AND-OR network

• Replace all gates with NAND gates (leave gate interconnection unchanged)– Complement any literal inputs to the level 1

gate

AND-OR and Equivalent NAND-NAND

XA

C

B

D

X

A

C

B

D

EE

Design of minimum Two-Level NOR-NOR Network

• Find the minimum product-of-sums expression

• Draw the corresponding two-level AND-OR network

• Replace all gates with NOR gates (leave gate interconnection unchanged)– Complement any literal inputs to the level 1

gate

Example XOR Gate

)()(

)).((

...

..

BABA

BABABA

BABA

BABABA

AX

B

A B X

0 0 0

0 1 1

1 0 1

1 1 0

Exercise

1 1

1 1

1

Given the truth opposite:• Design a two-level

NAND-NAND network

• And a two-level NOR-NOR network

• With minimum gates.– Assume complements

are available

A

B

D

C

AB

CD

Digital Simulation

• If you’ve got Digital Works or Logisim, build the AND-OR network and corresponding NAND-NAND network and satisfy yourself that they are equivalent

• And do the same for the OR-AND and NOR-NOR network

– Logisim http://ozark.hendrix.edu/~burch/logisim/

Design of Multi-Level NAND-Gate Networks

• Specify the operation of the switching network• Design network with AND and OR gates.• Output must be an OR gate (at level 1)• AND gate output cannot be used as AND gate

inputs• Or gate output cannot be used as OR gate inputs• Replace all gates with NAND gates• Invert any literals at levels, 1,3,5,… (levels 2,4,6,

…leave unchanged

Design of Multi-Level NOR-Gate Networks

• Specify the operation of the switching network• Design network with AND and OR gates.• Output must be an AND gate (at level 1)• AND gate output cannot be used as AND gate

inputs• Or gate output cannot be used as OR gate inputs• Replace all gates with NOR gates• Invert any literals at levels, 1,3,5,… (levels 2,4,6,

…leave unchanged

Exercise

KJIHGFEDCBAX ])([• Draw the switching network for X. Assume

complements are available• Redraw it using NAND gates only

Multi-Level AND-OR Network

BE

F

G

C

DA

K

IH

J

X

Level 1Level 2Level 3Level 4Level 5

€

X = A[B + C(D + E) + FG] + HIJ + K

Equivalent NAND Network

BE

A

G

C

DA

K

IH

J

X

Level 1Level 2Level 3Level 4Level 5

Alternative NOT Gate

• Usually the inversion “bubble” is placed at the output of gate

• However the bubble can be placed at the input

A

A

A

A

Alternative AND and OR Gates

A

BAB

A

BA+B

(By simple application of DeMorgan’s Law)

Alternative NAND and NOR Gates

• These symbols can be used to facilitate analysis and design of NAND and NOR networks.

A

BAB

A

BA+B

Example of Alternative Method

• Consider the NAND gate network below• Assume compliments are available

A

BC

E

F X

D

Example

• Replace the NAND gates at the 1st and 3rd level with their alternative symbols

A

BC

E

F X

D

Example

A

BC

E

F X

D

• Double inversions cancel• Remove inversion bubbles for literals and replace

with their complements

Exercise

• Convert the AND-OR network below to a NOR gate only network using the reverse process

• Assume compliments are available

A

BC

D

E

F

XG

Exercise: Solution

A

BC

D

E

F

XG

• Change OR gates to “conventional” NOR gate symbol• Change AND gates to the alternative NOR gate symbol

– Invert input literals at these (AND) gates

• Swap alternative NOR gate symbols for conventional NOR gates symbol (but not necessary)

Converting to NAND (or NOR) for non-alternating ANDs and ORs

• Consider the network below• AND and OR gates do not alternate between

levels

XC

DE

A

B

First Step for NAND conversion

XC

DE

A

B

• Replace ANDs with NANDs by adding inversion bubble to the output

• Replace Ors with NANDs by adding inversion bubbles to inputs

• But this is not an equivalent circuit…

Second Step for NAND conversion

• When an inverted input drives an inverted output no action is necessary

• But when non-inverted input drives an inverted output (or the other way round) insert an inverter

• Complement literals at inverted inputs

XC

DE

A

B

Exercise

• For the function F3=(0,2,3,7)8

• Use a Karnaugh Map to derive a least minterm expression

• And a least maxterm expression

• Draw and NOR realisation of both the minterm and maxterm expression

• Verify your results