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MOS INTEGRATED CIRCUIT
µPD42S4400, 4244004 M-BIT DYNAMIC RAM
1 M-WORD BY 4-BIT, FAST PAGE MODE
DescriptionThe µPD42S4400, 424400 are 1,048,576 words by 4 bits CMOS dynamic RAMs. The fast page mode capability
realize high speed access and low power consumption.
Besides, the µPD42S4400 can execute CAS before RAS self refresh.
These are packaged in 26-pin plastic TSOP(II ) and 26-pin plastic SOJ.
Features• 1,048,576 words by 4 bits organization • Single +5.0 V ± 10 % power supply
• Fast page mode
• Fast access and cycle time
Document No. M11160EJ7V0DS00 (7th edition)Date Published February 1996 PPrinted in Japan
The information in this document is subject to change without notice.
PowerAccess time R/W cycle time
Fast page mode
Part number consumption(MAX.) (MIN.)
cycle time
Active (MAX.) (MIN.)
µPD42S4400-60, 424400-60 495 mW 60 ns 120 ns 40 ns
µPD42S4400-70, 424400-70 440 mW 70 ns 140 ns 45 ns
µPD424400-80 440 mW 80 ns 160 ns 50 ns
µPD424400-10 440 mW 100 ns 190 ns 60 ns
• Multiplexed address inputs ······ Row address: A0 - A9, Column address: A0 - A9
• The µPD42S4400 can execute CAS before RAS self refresh
Part number Refresh cycle RefreshPower consumption
at standby (MAX.)
µPD42S4400 1,024 cycles/128 ms CAS before RAS self refresh, 0.825 mWCAS before RAS refresh, (CMOS level input)
RAS only refresh, Hidden refresh
µPD424400 1,024 cycles/16 ms CAS before RAS refresh, 5.5 mWRAS only refresh, (CMOS level input)
Hidden refresh
© 1990, 1993, 1994, 1995
DATA SHEET
µPD42S4400, 424400
2
Ordering Information
Part numberAccess time
Package Refresh(MAX.)
µPD42S4400GS-60-9JD 60 ns 26-pin plastic TSOP (II ) CAS before RAS self refresh
µPD42S4400GS-70-9JD 70 ns (300 mil) CAS before RAS refresh
µPD42S4400LA-60 60 ns 26-pin plastic SOJRAS only refresh
µPD42S4400LA-70 70 ns (300 mil)Hidden refresh
µPD424400GS-60-9JD 60 ns 26-pin plastic TSOP (II ) CAS before RAS refresh
µPD424400GS-70-9JD 70 ns (300 mil) RAS only refresh
µPD424400GS-80-9JD 80 nsHidden refresh
µPD424400GS-10-9JD 100 ns
µPD424400LA-60 60 ns 26-pin plastic SOJ
µPD424400LA-70 70 ns (300 mil)
µPD424400LA-80 80 ns
µPD424400LA-10 100 ns
µPD42S4400, 424400
3
Pin Configurations (Marking Side)
26-pin Plastic TSOP ( II ) (300 mil) 26-pin Plastic SOJ (300 mil)
GND
I/O4
I/O3
CAS
OE
26
25
24
23
22
A8
A7
A6
A5
A4
18
17
16
15
14
I/O1
I/O2
WE
RAS
A9
1
2
3
4
5
9
10
11
12
13
A0
A1
A2
A3
VCC
PD
42S4400G
S-9JD
P
D424400G
S-9JD
µ µ
GND
I/O4
I/O3
CAS
OE
26
25
24
23
22
A8
A7
A6
A5
A4
18
17
16
15
14
I/O1
I/O2
WE
RAS
A9
1
2
3
4
5
9
10
11
12
13
A0
A1
A2
A3
VCC
PD
42S4400L
A
PD
424400LA
µ µ
A0 to A9 : Address Inputs
I/O1 to I/O4 : Data Inputs/Outputs
RAS : Row Address Strobe
CAS : Column Address Strobe
WE : Write Enable
OE : Output Enable
VCC : Power Supply
GND : Ground
µPD42S4400, 424400
4
Block Diagram
Clock Generator
CAS before RAS Counter
RAS
CAS
WE
VCC
GND
A0 to A9
X0 - X9
Y0 - Y9
Row
Dec
oder
Row Address Buffer
Column Address Buffer
1,02
4
Memory Cell
Array
1,024 × 1,024 × 4
1,024 × 4
1,024
Sense Amplifier
Column Decoder
Data Output Buffer
Data Input Buffer
× 4
OE
I/O1 to
I/O4
µPD42S4400, 424400
5
Input/Output Pin FunctionsThe µPD42S4400, 424400 have input pins RAS, CAS, WE, OE, A0 to A9 and input/output pins I/O1 to I/O4.
Pin name
RAS
(Row address strobe)
CAS
(Column address strobe)
A0 to A9
(Address inputs)
WE
(Write enable)
OE
(Output enable)
I/O1 to I/O4
(Data inputs/outputs)
Input/Output Function
Input RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS refresh
Input CAS activates data input/output circuit by latching column address and
selecting a digit line connected with the sense amplifier.
Input Address bus.
Input total 20-bit of address signal, upper 10-bit and lower 10-bit in sequence
(address multiplex method).
Therefore, one word is selected from 1,048,576-word by 4-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, tASC) and hold time (tRAH, tCAH)
are specified for the activation of RAS and CAS.
Input Write control signal.
Write operation is executed by activating RAS, CAS and WE.
Input Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
If WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.
Input/Output 4-bit data bus.
I/O1 to I/O4 are used to input/output data.
µPD42S4400, 424400
6
Electrical Specifications
• All voltages are referenced to GND.
• After power up (VCC ≥ VCC (MIN.)), wait more than 100 µs (RAS, CAS inactive) and then, execute eight CAS
before RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Voltage on any pin relative to GND VT –1.0 to +7.0 V
Supply voltage VCC –1.0 to +7.0 V
Output current IO 50 mA
Power dissipation PD 1 W
Operating ambient temperature TA 0 to +70 ˚C
Storage temperature Tstg –55 to +125 ˚C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply voltage VCC 4.5 5.0 5.5 V
High level input voltage VIH 2.4 VCC + 1.0 V
Low level input voltage VIL –1.0 +0.8 V
Operating ambient temperature TA 0 70 ˚C
Capacitance (T A = 25 ˚C, f = 1 MHZ)
Parameter Symbol Test condition MIN. TYP. MAX. Unit
Input capacitance CI1 Address 5 pF
CI2 RAS, CAS, WE, OE 7
Data input/output capacitance CI/O I/O 7 pF
µPD42S4400, 424400
7
DC Characteristics (Recommended operating conditions unless otherwise noted)
Parameter Symbol Test condition MIN. MAX. Unit Notes
Operating current ICC1 RAS, CAS cycling tRAC = 60 ns 90 mA 1, 2, 3
tRC = tRC (MIN.) tRAC = 70 ns 80IO = 0 mA
tRAC = 80 ns 80
tRAC = 100 ns 80
Standby µPD42S4400 ICC2 RAS, CAS ≥ VIH (MIN.), IO = 0 mA 2.0 mA
current RAS, CAS ≥ VCC – 0.2 V, IO = 0 mA 0.15
µPD424400 RAS, CAS ≥ VIH (MIN.), IO = 0 mA 2.0
RAS, CAS ≥ VCC – 0.2 V, IO = 0 mA 1.0
RAS only refresh current ICC3 RAS cycling, CAS ≥ VIH (MIN.) tRAC = 60 ns 90 mA 1, 2, 3 ,4
tRC = tRC (MIN.), IO = 0 mA tRAC = 70 ns 80
tRAC = 80 ns 80
tRAC = 100 ns 80
Operating current ICC4 RAS ≤ VIL (MAX.), CAS cycling tRAC = 60 ns 70 mA 1, 2, 5
(Fast page mode) tPC = tPC (MIN.), IO = 0 mA tRAC = 70 ns 60
tRAC = 80 ns 60
tRAC = 100 ns 60
CAS before RAS ICC5 RAS cycling tRAC = 60 ns 90 mA 1, 2
refresh current tRC = tRC (MIN.) tRAC = 70 ns 80IO = 0 mA
tRAC = 80 ns 80
tRAC = 100 ns 80
CAS before RAS ICC6 CAS before RAS refresh : tRAS ≤ 200 ns 200 µA 1, 2
long refresh current tRC = 125.0 µs
(1,024 cycles / 128 ms, RAS, CAS :
only for the µPD42S4400) VCC – 0.2 V ≤ VIH ≤ VIH (MAX.)
0 V ≤ VIL ≤ 0.2 V
Standby : tRAS ≤ 1 µs 300 µA 1, 2
RAS, CAS ≥ VCC – 0.2 V
Address : VIH or VIL
WE, OE: VIH
IO = 0 mA
CAS before RAS ICC7 RAS, CAS : 150 µA 2self refresh current tRASS = 5 ms
(only for the µPD42S4400) VCC – 0.2 V ≤ VIH ≤ VIH(MAX.)
0 V ≤ VIL ≤ 0.2 V
IO = 0 mA
Input leakage current II (L) VI = 0 to 5.5 V –10 +10 µA
All other pins not under test = 0 V
Output leakage current IO (L) VO = 0 to 5.5 V –10 +10 µA
Output is disabled (Hi-Z)
High level output voltage VOH IO = –5.0 mA 2.4 V
Low level output voltage VOL IO = +4.2 mA 0.4 V
Notes 1. ICC1, ICC3, ICC4, ICC5 and ICC6 depend on cycle rates (tRC and tPC).
2. Specified values are obtained with outputs unloaded.
µPD42S4400, 424400
8
3. ICC1 and ICC3 are measured assuming that address can be changed once or less during RAS ≤ VIL (MAX.)
and CAS ≥ VIH (MIN.).
4. ICC3 is measured assuming that all column address inputs are held at either high or low.
5. ICC4 is measured assuming that all column address inputs are switched only once during each fast page
cycle.
µPD42S4400, 424400
9
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
(1) Input timing specification (2) Output timing specification
V IH (MIN.) = 2.4 V
V IL (MAX.) = 0.8 V
V OH (MIN.) = 2.4 V
V OL (MAX.) = 0.4 V
t T = 5 ns t T = 5 ns
(3) Output load condition
100 pF
CL
I/O
820 Ω
290 Ω
VCC
Common to Read, Write, Read Modify Write Cycle
Parameter SymboltRAC = 60 ns tRAC = 70 ns tRAC = 80 ns tRAC = 100 ns
Unit NotesMIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Read / Write cycle time tRC 110 – 130 – 160 – 190 – ns
RAS precharge time tRP 40 – 50 – 70 – 80 – ns
CAS precharge time tCPN 10 – 10 – 10 – 10 – ns
RAS pulse width tRAS 60 10,000 70 10,000 80 10,000 100 10,000 ns 1
CAS pulse width tCAS 15 10,000 20 10,000 20 10,000 25 10,000 ns
RAS hold time tRSH 15 – 20 – 20 – 25 – ns
CAS hold time tCSH 60 – 70 – 80 – 100 – ns
RAS to CAS delay time tRCD 20 45 20 50 25 60 25 75 ns 2
RAS to column address delay time tRAD 15 30 15 35 17 40 17 50 ns 2
CAS to RAS precharge time tCRP 10 – 10 – 10 – 10 – ns 3
Row address setup time tASR 0 – 0 – 0 – 0 – ns
Row address hold time tRAH 10 – 10 – 12 – 12 – ns
Column address setup time tASC 0 – 0 – 0 – 0 – ns
Column address hold time tCAH 15 – 15 – 15 – 20 – ns
OE lead time referenced to RAS tOES 0 – 0 – 0 – 0 – ns
CAS to data setup time tCLZ 0 – 0 – 0 – 0 – ns
OE to data setup time tOLZ 0 – 0 – 0 – 0 – ns
OE to data delay time tOED 15 – 15 – 20 – 25 – ns
Transition time (rise and fall) tT 3 50 3 50 3 50 3 50 ns
Refresh time µPD42S4400 tREF – 128 – 128 – – – – ms 4
µPD424400 – 16 – 16 – 16 – 16 ms
µPD42S4400, 424400
10
Notes 1. In CAS before RAS refresh cycles, tRAS (MAX.) is 100 µs. If 10 µs < tRAS < 100 µs, RAS precharge time for
CAS before RAS self refresh (tRPS) is applied.
2. For read cycles, access time is defined as follows:
Input conditions Access time Access time from RAS
tRAD ≤ tRAD (MAX.) and tRCD ≤ tRCD (MAX.) tRAC (MAX.) tRAC (MAX.)
tRAD > tRAD (MAX.) and tRCD ≤ tRCD (MAX.) tAA (MAX.) tRAD + tAA (MAX.)
tRCD > tRCD (MAX.) tCAC (MAX.) tRCD + tCAC (MAX.)
tRAD (MAX.) and tRCD (MAX.) are specified as reference points only ; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ≥ tRAD (MAX.) and tRCD ≥ tRCD (MAX.) will not cause
any operation problems.
3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.
4. This specification is applied only to the µPD42S4400-60, 42S4400-70.
Read Cycle
Parameter SymboltRAC = 60 ns tRAC = 70 ns tRAC = 80 ns tRAC = 100 ns
Unit NotesMIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Access time from RAS tRAC – 60 – 70 – 80 – 100 ns 1
Access time from CAS tCAC – 15 – 20 – 20 – 25 ns 1
Access time from column address tAA – 30 – 35 – 40 – 50 ns 1
Access time from OE tOEA – 15 – 20 – 20 – 25 ns
Column address lead time tRAL 30 – 35 – 40 – 50 – ns
referenced to RAS
Read command setup time tRCS 0 – 0 – 0 – 0 – ns
Read command hold time tRRH 0 – 0 – 10 – 10 – ns 2
referenced to RAS
Read command hold time tRCH 0 – 0 – 0 – 0 – ns 2
referenced to CAS
Output buffer turn-off delay tOEZ 0 15 0 15 0 20 0 25 ns 3
time from OE
Output buffer turn-off delay tOFF 0 15 0 15 0 20 0 25 ns 3
time from CAS
Notes 1. For read cycles, access time is defined as follows:
Input conditions Access time Access time from RAS
tRAD ≤ tRAD (MAX.) and tRCD ≤ tRCD (MAX.) tRAC (MAX.) tRAC (MAX.)
tRAD > tRAD (MAX.) and tRCD ≤ tRCD (MAX.) tAA (MAX.) tRAD + tAA (MAX.)
tRCD > tRCD (MAX.) tCAC (MAX.) tRCD + tCAC (MAX.)
tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD ≥ tRAD (MAX.) and tRCD ≥ tRCD (MAX.) will not cause
any operation problems.
2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOFF (MAX.) and tOEZ(MAX.) define the time when the output achieves the condition of Hi-Z and is not referenced
to VOH or VOL.
µPD42S4400, 424400
11
Write Cycle
Parameter SymboltRAC = 60 ns tRAC = 70 ns tRAC = 80 ns tRAC = 100 ns
Unit NotesMIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
WE hold time referenced to CAS tWCH 15 – 15 – 15 – 20 – ns 1
WE pulse width tWP 10 – 10 – 15 – 20 – ns 1
WE lead time referenced to RAS tRWL 15 – 20 – 20 – 25 – ns
WE lead time referenced to CAS tCWL 15 – 15 – 15 – 20 – ns
WE setup time tWCS 0 – 0 – 0 – 0 – ns 2
OE hold time tOEH 0 – 0 – 0 – 0 – ns
Data-in setup time tDS 0 – 0 – 0 – 0 – ns 3
Data-in hold time tDH 15 – 15 – 15 – 20 – ns 3
Notes 1. tWP (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be met.
2. If tWCS ≥ tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.
Read Modify Write Cycle
Parameter SymboltRAC = 60 ns tRAC = 70 ns tRAC = 80 ns tRAC = 100 ns
Unit NoteMIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Read modify write cycle time tRWC 150 – 175 – 210 – 250 – ns
RAS to WE delay time tRWD 80 – 90 – 105 – 130 – ns 1
CAS to WE delay time tCWD 35 – 40 – 45 – 55 – ns 1
Column address to WE delay time tAWD 50 – 55 – 65 – 80 – ns 1
Note 1. If tWCS ≥ tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD ≥ tRWD (MIN.), tCWD ≥ tCWD (MIN.), tAWD ≥ tAWD (MIN.) and tCPWD ≥ tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.
µPD42S4400, 424400
12
Fast Page Mode
Parameter SymboltRAC = 60 ns tRAC = 70 ns tRAC = 80 ns tRAC = 100 ns
Unit NoteMIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Fast page mode cycle time tPC 40 – 45 – 50 – 60 – ns
Access time from CAS precharge tACP – 35 – 40 – 45 – 55 ns
RAS pulse width tRASP 60 125,000 70 125,000 80 125,000 100 125,000 ns
CAS precharge time tCP 10 – 10 – 10 – 10 – ns
RAS hold time from CAS precharge tRHCP 35 – 40 – 45 – 55 – ns
Read modify write cycle time tPRWC 80 – 85 – 95 – 115 – ns
CAS precharge to WE delay time tCPWD 55 – 60 – 70 – 85 – ns 1
Note 1. If tWCS ≥ tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD ≥ tRWD (MIN.), tCWD ≥ tCWD (MIN.), tAWD ≥ tAWD (MIN.) and tCPWD ≥ tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.
Refresh Cycle
Parameter SymboltRAC = 60 ns tRAC = 70 ns tRAC = 80 ns tRAC = 100 ns
Unit NoteMIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
CAS setup time tCSR 10 – 10 – 10 – 10 – ns
CAS hold time (CAS before RAS refresh) tCHR 10 – 10 – 15 – 20 – ns
RAS precharge CAS hold time tRPC 10 – 10 – 10 – 10 – ns
RAS pulse width tRASS 100 – 100 – – – – – µs 1(CAS before RAS self refresh)
RAS precharge time tRPS 110 – 130 – – – – – ns 1
(CAS before RAS self refresh)
CAS hold time tCHS –50 – –50 – – – – – ns 1
(CAS before RAS self refresh)
WE setup time tWSR 0 – 0 – 10 – 10 – ns
WE hold time tWHR 10 – 10 – 15 – 20 – ns
Note 1. This specification is applied only to the µPD42S4400-60, 42S4400-70.
µPD42S4400, 424400
13
Read Cycle
I/O
RAS V IH–
V IL–
WE V IH–
V IL–
t RAS t RP
t RC
CAS V IH–
V IL–
t CSH
t RCD t CRP t RSH
t CAS
t CPN
Address V IH–
V IL–
t ASR t RAH t ASC t CAH
t RAD t RAL
Row Col.
t RCS t RRH
t RCH
OE V IH–
V IL–
V OH–
V OL–
t OES
t OEA
t RAC
t AA
t CAC
t OLZ
t CLZ
t OFF
t OEZ
Data out Hi-Z Hi-Z
µPD42S4400, 424400
14
Early Write Cycle
Remark OE: Don’t care
RAS
tRAS
tRC
tRP
tCSH
tRSH tRCD
tCAS
tCPN tCRP
tRAD
tASR tRAH tASC tCAH
Row Col.
tWCS
VIH–
VIL–
CAS VIH–
VIL–
Address VIH–
VIL–
WE VIH–
VIL–
Data in I/O VIH–
VIL–
tDS
tWCH
tDH
µPD42S4400, 424400
15
Late Write Cycle
I/O
RAS V IH–
V IL–
WE V IH–
V IL–
t RAS t RP
t RC
CAS V IH–
V IL–
t CSH
t RCD t CRP t RSH
t CAS
t CPN
V IH–
V IL–
t ASR t RAH t ASC t CAH
t RAD
Row Col.
t RCS
OE V IH–
V IL–
V IH–
V IL–
t CWL
t OED
Data in Hi-Z
t RWL
t WP
t OEH
t DS t DH
µPD42S4400, 424400
16
Read Modify Write Cycle
I/O
RAS V IH–
V IL–
WE V IH–
V IL–
t RAS t RP
t RWC
CAS V IH–
V IL–
t CSH
t RCD t CRP t RSH
t CAS
t CPN
Address V IH–
V IL–
t ASR t RAH t ASC t CAH
t RAD
Row Col.
t RCS
OE V IH–
V IL–
V IH–
V IL–
t RWD
t CAC
Data in
t AWD
t CWD
t DS t DH
t WP
t RWL
t CWL
t AA
t RAC
t OED
t OEA t OEH
I/O V OH–
V OL– Data out
Hi-Z Hi-Z
t OEZ t CLZ
t OLZ
µPD42S4400, 424400
17
Fast Page Mode Read Cycle
Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.
RAS V IH–
V IL–
CAS V IH–
V IL–
t RASP
t RHCP
t RSH t PC t CSH
t CPN t CAS t CP t CAS t CP t CAS t RCD t CRP
t RP
Address V IH–
V IL–
t ASR t RAH
Row
t ASC
t RAD
Col.
t CAH t ASC
Col.
t CAH t ASC
Col.
t CAH
t RAL
WE V IH–
V IL–
t RCS t RCH t RCH t RCS t RCS t RRH
t RCH
OE V IH–
V IL–
t OES
I/O V OH–
V OL–
t RAC
t AA
t CAC
t CLZ
t OEA
t OLZ
Data out Data out
t OEA
t OLZ
t ACP
t OEZ
t OFF t CAC
t CLZ
t AA
t OEA
t OLZ
t ACP
t OEZ
t OFF t CAC
t CLZ
t AA
Data out
t OEZ t OFF
Hi-Z Hi-Z Hi-Z Hi-Z
µPD42S4400, 424400
18
Fast Page Mode Early Write Cycle
Remarks 1. OE: Don’t care
2. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
RAS
tRASP
VIH–
VIL–
CAS VIH–
VIL–
Address VIH–
VIL–
WE VIH–
VIL–
I/O VIH–
VIL–
tRP
tRHCP
tRSH tPC
tCPN
tCSH
tCAS tCP tCAS tCAS tCP
tRAL
tCAH tCAH tASC tCAH
Col. Col. Row
tASR tRAH
tWCS tWCS
tRCD
tRAD
tASC
Col.
tWCH tWCH tWCH
Data in Data in Data in
tDH tDS tDH tDS tDH tDS
tWCS
tASC
tCRP
µPD42S4400, 424400
19
Fast Page Mode Late Write Cycle
Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.
CAS V IH–
V IL–
t CPN t CP t CP
t CSH
t CAS t RCD
RAS V IH–
V IL–
t RASP t RP
t CRP
t PC t RSH
t RHCP
t CAS t CAS
Row Col.
t ASR t RAH
t RAD
t ASC t CAH t ASC
Col.
t CAH t ASC
Col.
t CAH
t RAL
V IH–
V IL–
WE V IH–
V IL–
t RCS
t CWL
t WP t RCS
t CWL
t WP t RCS
t CWL
t WP
t RWL
OE V IH–
V IL–
t OEH t OEH t OEH
I/O V IH–
V IL–
t OED t DS t DH
Hi-Z Data in
t OED t DS t DH
Data in Hi-Z
t OED t DS t DH
Data in Hi-Z
Address
µPD42S4400, 424400
20
Fast Page Mode Read Modify Write Cycle
Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.
t RCS
CAS V IH–
V IL–
t CPN t CP t CAS t CAS t CP
t PRWC
t CAS t RCD
RAS V IH–
V IL–
t RASP t RP
t CRP
Address V IH–
V IL–
t ASR t RAH
t RAD
t ASC t CAH t ASC t CAH t CAH t ASC
Row Col. Col. Col.
t RAL
WE V IH–
V IL–
t RWD
t OLZ
I/O V IH–
V IL–
t DH t DS
t AWD
t CWD t WP t RCS
t CWL
t ACP t CPWD
t AWD
tCWD t WP
t CWL
t ACP t CPWD
t AWD
t CWD t RCS
t CWL
t RWL
t WP
OE V IH–
V IL–
I/O V OH–
V OL– out
tOEZ
t CLZ t OED
t OEA
t CAC
t AA
t RAC
in
t OEA
t OEH t CAC
t AA
t OLZ
t DH t DS
out
tOEZ
t CLZ t OED
in
t OLZ
t DH t DS
out
t OEZ
t CLZ t OED
in
t OEH
t AA
t CAC
t OEA
t OEH
Hi-Z Hi-Z Hi-Z Hi-Z
µPD42S4400, 424400
21
CAS Before RAS Self Refresh Cycle (Only for the µPD42S4400)
Remark Address, OE: Don’t care I/O: Hi-Z
RAS
CAS
WE
VIH_
VIL_
VIH_
VIL_
VIH_
VIL_
tCSR
tWSR tWHR
tRASS tRPS
tCRP
tRPC
tCHS tCPN
Cautions on Use of CAS Before RAS Self Refresh
CAS before RAS self refresh can be used independently when used in combination with distributed CAS
before RAS long refresh; However, when used in combination with burst CAS before RAS long refresh or with
long RAS only refresh (both distributed and burst), the following cautions must be observed.
(1) Normal Combined Use of CAS Before RAS Self Refresh and Burst CAS Before RAS Long Refresh
When CAS before RAS self refresh and burst CAS before RAS long refresh are used in combination, please
perform CAS before RAS refresh 1,024 times within a 16 ms interval just before and after setting CAS before
RAS self refresh.
(2) Normal Combined Use of CAS Before RAS Self Refresh and Long RAS Only Refresh
When CAS before RAS self refresh and RAS only refresh are used in combination, please perform RAS only
refresh 1,024 times within a 16 ms interval just before and after setting CAS before RAS self refresh.
(3) If tRASS (MIN.) is not satisfied at the beginning of CAS before RAS self refresh cycles (tRAS < 100 µs), CAS before
RAS refresh cycles will be executed one time.
If 10 µs < tRAS < 100 µs, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
And refresh cycles (1,024/128 ms) should be met.
For details, please refer to How to use DRAM User’s Manual.
µPD42S4400, 424400
22
CAS Before RAS Refresh Cycle
Remark Address, OE: Don’t care I/O: Hi-Z
RAS Only Refresh Cycle
Remark WE, OE: Don’t care I/O: Hi-Z
RAS
tRC
VIH–
VIL–
CAS VIH–
VIL–
VIH–
VIL–
tWHR
tCSR tCHR tRPC tCSR tCHR tRPC tCPN
tCRP
tRAS tRP tRP tRAS
tWSR
WE
tRC
tWSR tWHR
RAS
tRC
VIH–
VIL–
CAS VIH–
VIL–
tASR
tCRP tRPC
tCPN
tCRP
tRAS tRP tRP tRAS
tASR
tRC
Row Address VIH–
VIL–
tRAH tRAH
Row
µPD42S4400, 424400
23
Hidden Refresh Cycle (Read)
I/O
RAS V IH–
V IL–
WE V IH–
V IL–
t RAS t RP
t RC
CAS V IH–
V IL–
t RCD t CRP t RSH t CPN
V IH–
V IL–
t ASR t RAH t ASC t CAH
t RAD
Row Col.
t RCS t WHR
OE V IH–
V IL–
V OH–
V OL–
t OES
t RAC
t AA
t CAC
t OLZ
t CLZ
t OFF
t OEZ
Data out Hi-Z Hi-Z
t RAS
t RC
t RP
t OEA
t RAL
t CHR
Address
µPD42S4400, 424400
24
Hidden Refresh Cycle (Write)
Remark OE: Don’t care
RAS
tRAS
tRC
tRAS
tCHR tRCD tCPN tCRP
tRAD
tASC tCAH
Row Col.
VIH–
VIL–
CAS VIH–
VIL–
Address VIH–
VIL–
WE VIH–
VIL–
I/O
tRP
tRC
tRP
tRSH
tASR tRAH
tDS tDH
tWCS tWCH
Data in VIH–
VIL–
tWSR tWHR
µPD42S4400, 424400
25
Test Mode Set Cycle (WE, CAS Before RAS Refresh Cycle)
RAS VIH–
VIL–
CAS VIH–
VIL–
WE VIH–
VIL–
tCSR tCHR
tWSR tWHR
tRPC tCRP
tRC
tRAS tRP
Remark Address, OE: Don’t care I/O: Hi-Z
Test Mode
By using the test mode, the test time can be reduced. The reason for this is that, the memory emulates the
× 8-bit organization during test mode. Don’t care about the input level of the CAS input A0.
(1) Setting the mode
Executing the test mode cycle (WE, CAS before RAS refresh cycle) sets the test mode.
(2) Write/read operation
When either a “0” or a “1” is written to the input pin in test mode, this data is written to 8 bits of memory cell.
Next, when the data is read from the output pin at the same address, the cell can be checked.
Output = “1”: Normal write (all memory cells)
Output = “0”: Abnormal write
(3) Refresh
Refresh in the test mode must be performed with the RAS / CAS cycle or with the WE, CAS before RAS refresh
cycle. The WE, CAS before RAS refresh cycle use the same counter as the CAS before RAS refresh’s internal
counter.
(4) Mode Cancellation
The test mode is cancelled by executing one cycle of RAS only refresh cycle or CAS before RAS refresh cycle.
µPD42S4400, 424400
26
Package Drawings
A
NOTE
Each lead centerline is located within 0.21 mm (0.009 inch) of its true position (T.P.) at maximum material condition.
M D M
C
26
1
14
13
N B
K
L
H
I J
P
E
F
detail of lead end
26 PIN PLASTIC TSOP (II) (300 mil)
ITEM MILLIMETERS INCHES
A
B
C
E
F
G
H
I
17.36 MAX.
1.27 (T.P.)
0.1±0.05
1.2 MAX.
1.0
1.06 MAX.
7.62±0.1
9.22±0.2
0.684 MAX.
0.042 MAX.
0.004±0.002
0.048 MAX.
0.039
0.363±0.008
0.300±0.004
0.050 (T.P.)
D 0.42 0.017±0.003
J 0.8±0.2 0.031 +0.009 –0.008
K 0.145 0.006±0.001
L 0.5±0.1 0.020 +0.004 –0.005
M
N 0.10
0.21 0.009
0.004
P 3°
S26G3-50-9JD
+7° –3° 3° +7°
–3°
+0.08 –0.07
+0.025 –0.015
G
µPD42S4400, 424400
27
26 PIN PLASTIC SOJ (300 mil)
ITEM MILLIMETERS INCHES
B
C
D
E
F
G
H
I
J
K
17.4
8.47±0.2
3.5±0.2
2.4±0.2
0.8 MIN.
7.57
M
N
6.73±0.20
0.12
1.27(T.P.)
2.6
0.40±0.10
P
1.08±0.15
0.6
0.685
0.298
0.043
0.024
0.138±0.008
0.094
0.031 MIN.
0.102
0.050(T.P.)
0.016
0.005
0.265±0.008
0.333
P26LA-50A-2
U 0.20 0.008
+0.2 –0.35
+0.008 –0.013
+0.009 –0.008
+0.006 –0.007
+0.009 –0.008
+0.004 –0.005
0.15Q 0.006
T R 0.85 R0.033
+0.004 –0.002
+0.10 –0.05
NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
26
B
131
C D
14G
H
JI
F
K Q
M N M
E
PT
U
µPD42S4400, 424400
28
Recommended Soldering Conditions
The following conditions (see tables below and next page) must be met for soldering conditions of the
µPD42S4400, 424400.
For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL”
(IEI-1207).
Please consult with our sales offices in case other soldering process is used, or in case the soldering is done
under different conditions.
Types of Surface Mount Device
µPD42S4400GS-9JD, 424400GS-9JD: 26-pin plastic TSOP ( II ) (300 mil)
Soldering process Soldering conditions
Infrared ray reflow Peak temperature of package surface: 235 ˚C or lower,
Reflow time: 30 seconds or less (210 ˚C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote
(10 hours pre-baking is required at 125 ˚C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used in the second process).
VPS Peak temperature of package: 215 ˚C or lower,
Reflow time: 40 seconds or less (200 ˚C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote
(10 hours pre-baking is required at 125 ˚C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used in the second process).
Partial heating method Terminal temperature: 300 ˚C or lower,
Time: 3 seconds or lower (Per side of the package).
Note Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25 ˚C and relative humidity at 65 % or less.
Caution Do not apply more than one soldering method at any one time, except for “Partial heating
method”.
Symbol
IR35-107-2
VP15-107-2
————
µPD42S4400, 424400
29
Symbol
IR35-207-2
VP15-207-2
————
µPD42S4400LA, 424400LA: 26-pin plastic SOJ (300 mil)
Soldering process Soldering conditions
Infrared ray reflow Peak temperature of package surface: 235 ˚C or lower,
Reflow time: 30 seconds or less (210 ˚C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote
(20 hours pre-baking is required at 125 ˚C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used in the second process).
VPS Peak temperature of package: 215 ˚C or lower,
Reflow time: 40 seconds or less (200 ˚C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote
(20 hours pre-baking is required at 125 ˚C afterwards)
Cautions
1. After the first reflow process, cool the package down to room
temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove
residual flux (water can be used in the second process).
Partial heating method Terminal temperature: 300 ˚C or lower,
Time: 3 seconds or less (Per side of the package).
Note Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25 ˚C and relative humidity at 65 % or less.
Caution Do not apply more than one soldering method at any one time, except for “Partial heating
method”.
µPD42S4400, 424400
30
[MEMO]
µPD42S4400, 424400
31
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to V DD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
32
µPD42S4400, 424400
No part of this document may be copied or reproduced in any form or by any means without the prior writtenconsent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in thisdocument.NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectualproperty rights of third parties by or arising from use of a device described herein or any other liability arisingfrom use of such device. No license, either express, implied or otherwise, is granted under any patents,copyrights or other intellectual property rights of NEC Corporation or others.While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons orproperty arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safetymeasures in its design, such as redundancy, fire-containment, and anti-failure features.NEC devices are classified into the following three quality grades:“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based ona customer designated “quality assurance program“ for a specific application. The recommended applicationsof a device depend on its quality grade, as indicated below. Customers must check the quality grade of eachdevice before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,audio and visual equipment, home electronic appliances, machine tools, personal electronicequipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disastersystems, anti-crime systems, safety equipment and medical equipment (not specifically designedfor life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, lifesupport systems or medical equipment for life support, etc.
The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.If customers intend to use NEC devices for applications other than those specified for Standard quality grade,they should contact NEC Sales Representative in advance.Anti-radioactive design is not implemented in this product.
M4 94.11
[MEMO]
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