data brief - eval-l9963-nds - l9963 single node in a
Post on 23-Dec-2021
5 Views
Preview:
TRANSCRIPT
Features• Single node L9963 board for distributed multi-cell BMS• To be used with EVAL-L9963-MCU or EVAL-L9963 as second stage or stacked
with additional EVAL-L9963-NDS• Measures from 4 to 14 cells in series, with 0 us desynchronization delay
between samples. Supports also busbar connection without altering cell results• Coulomb counter supporting pack overcurrent detection in both ignition on and
off states• Fully synchronized current and voltage samples• 16-bit voltage measurement• Communication between nodes through a 2.66 Mbps isolated serial
communication with regenerative buffer, supporting dual access ring• Transformer based isolation• Up to 4 analog inputs for NTC sensing, plus PCB temperature sensing• Hot-plug protection circuit
DescriptionThe EVAL-L9963-NDS is a hardware tool for L9963 for Li-ION battery managementapplication. The board is intended to be used as a single node in a distributed BMS.EVAL-L9963-NDS is needed when the total number of battery cells to be managedexceeds 14. The number of nodes to be stacked depends on total battery voltage,additional nodes can be added via additional EVAL-L9963-NDS. A maximum of 14total nodes beyond the base node EVAL-L9963-MCU or an EVAL-L9963 can bestacked. It has to be used in conjunction with EVAL-L9963-MCU or an EVAL-9963 assecond stage or stacked with additional EVAL-L9963-NDS.
EVAL-L9963-NDS allows the user to manage up to 14 channels for cell voltagesensing, one channel for current sensing, and up to 4 analog input for temperaturesensing (plus an additional on-board NTC to sense PCB temperature). The boardprovides additional protection for hot plug.
EVAL-L9963-NDS is not intended to be used as a standalone evaluation board butwith EVAL-L9963-MCU or EVAL-L9963.
Product summary
Order code EVAL-L9963-NDS
Reference EVAL-L9963-NDSEvaluation board
L9963 single Node in a Distributed BMS System
EVAL-L9963-NDS
Data brief
DB4192 - Rev 1 - April 2020For further information contact your local STMicroelectronics sales office.
www.st.com
1 Block Diagram
EVAL-L9963-NDS provides a single L9963 device with the external connectors for battery and isolatedcommunication.
Figure 1. EVAL-L9963-NDS block diagram
EVAL-L9963-NDSBlock Diagram
DB4192 - Rev 1 page 2/12
2 Featured components
The EVAL-L9963-NDS can be considered as an additional node in a distributed BMS system, the first stageshould be implemented with an EVAL-L9963-MCU or an EVAL-L9963-NDS. In the following table there is a shortdescription of all ST featured components.
Table 1. Featured components
Name Description
L9963 Automotive chip for battery management applications
EVAL-L9963-NDSFeatured components
DB4192 - Rev 1 page 3/12
3 Minimum system requirements
• EVAL-L9963-MCU or EVAL-L9963 as first stage of a distributed BMS system• Power supply:• at least 3 output 0 – 30 V (if possible 60V):
– 1 output to power L9963 (0:60 V)– 1 output to simulate Cells common mode voltage (0:60V)– 1 output to simulate Cell voltage (0:5V)
EVAL-L9963-NDSMinimum system requirements
DB4192 - Rev 1 page 4/12
4 Connectors
Table 2. EVAL-L9963-NDS connectors
Name Description Configuration
ISOL
Isolated serial communication port:1. Fault Line supply2. ISOLm3. ISOLp4. FaultL
USB Type A connector
ISOH
Isolated serial communication port:1. Fault Line supply2. ISOHm3. ISOHp4. FaultH
USB Type A connector
P2
Battery connector:1. Cell 142. Cell 123. Cell 104. Cell 85. Cell 66. Cell 47. Cell 28. Cell 09. Ground10. Current sensor resistor negative pin11. NTC 1-12. NTC 2-13. NTC3 -14. NTC4 –15. VBAT16. Cell 1317. Cell 1118. Cell 919. Cell 720. Cell 521. Cell 322. Cell 123. Ground24. Current sensor resistor positive pin25. NTC 1+26. NTC 2+27. NTC3 +28. NTC4 +
Multi pin connector
EVAL-L9963-NDSConnectors
DB4192 - Rev 1 page 5/12
5 Hot plug protection
Figure 2. Hot plug protection circuit
The structure in Figure 2. Hot plug protection circuit on the GND path will help with standing the hot plug bylimiting the in rush current incoming from any L9963 pin connected to the centralized clamp.Working principle is the following:• When L9963 is OFF and no cell is connected, the VREG regulator is shut down and MHOT is safely kept off
by the RPD pull down resistor.• Upon the first hot plug event, inrush current incoming from the centralized clamp is forced to flow into RHOT
resistor, which offers proper limiting.• Any VDS voltage spike on MOSFET during hot plug could be coupled to the gate via the parasitic Miller
capacitance. Unwanted turn-on is safely filtered by CGS, that helps keeping VGS below the thresholdvoltage. Hence the MOSFET will stay OFF during hot plug.
• If the hot plug voltage is enough to guarantee L9963 powerup the MOSFET will be turned on by VREGregulator with a proper delay, obtained through RG gate resistor.
• Finally, during L9963 normal operation the MOSFET will be ON, thus guaranteeing a very low impedancepath (few mΩ) on the AGND line.– Such a small shift between L9963 GND and battery pack GND will not alter cell measurement at all,
since cell ADCs are fully differential. Hence, both cell and sum of cells measurements will be accurate.– Moreover, since L9963 only drains few mA from the battery pack, error introduced on the VBAT stack
measurement via internal voltage divider will be negligible.– Also the CSA used for Coulomb Counting features a fully differential architecture, thus being immune
to such a small common mode shift.
EVAL-L9963-NDSHot plug protection
DB4192 - Rev 1 page 6/12
6 Distributed BMS topology
EVAL-L9963-NDS is intended to be used in combination with either EVAL-L9963-MCU or EVAL-L9963 as anadditional node of a distributed BMS system. EVAL-L9963-MCU or EVAL-L9963 are needed as first stage and upto 14 EVAL-L9963-NDS can be connected as additional nodes. In Figure 3. Distributed BMS architecture apossible layout for a distributed BMS using multiple EVAL-L9963-NDS together with either EVAL-L9963-MCU orEVA-L9963. Distributed BMS architecture.
Figure 3. Distributed BMS architecture
EVAL-L9963-NDSDistributed BMS topology
DB4192 - Rev 1 page 7/12
7 EVAL-L9963 Evaluation board schematic
Figure 4. Board schematic: page 1
R26
100
R29
100
R33
100
R36
100
R41
100
R45
100
R51
100
R56
100
R61
100
R66
100
R72
100
R75
100
R84
100
R89
100
R92
100
C29
10nF
C37
10nF
R27
39 R31 39 R34
39
R38
39
R42
39
R48
39
R52
39
R59
39
R63
39
R69
39
R73
39
R82
39
R87
39
R90
39
C41
10nF
C46
10nF
C49
10nF
C52
10nF
C58
10nF
C60
10nF
C63
10nF
C65
10nF
C68
10nF
C70
10nF
C72
10nF
C87
10nF
C28
47nF
C36
47nF
C40
47nF
C45
47nF
C48
47nF
C51
47nF
C56
47nF
C59
47nF
C62
47nF
C64
47nF
C67
47nF
C69
47nF
C71
47nF
C86
47nF
C88
47nF
GN
D_B
GN
D_B
GN
D_B
GN
D_B
GN
D_B
GN
D_B
GN
D_B
GN
D_B
GN
D_B
GN
D_B
GN
D_B
GN
D_B
GN
D_B
GN
D_B
GN
D_B
R25
0 R28
0 R32
0 R35
0 R40
0 R44
0 R50
0 R55
0 R60
0 R65
0 R71
0 R74
0 R83
0 R88
0 R91
0
1
23
Q1
MJD
31C
T4
C26
10uF
GN
D_B
C25
100n
FG
ND
_B
C31
220n
F
C32
2.2u
FN
ot A
ssem
bled
C34
100n
FC
332.
2uF
Not
Ass
embl
edC
3510
0nF
GN
D_B
Not
Ass
embl
ed
C30
100n
F
VC
OM
VTR
EF
C39
1uF
C21
2.2u
FC
2710
0nF
GN
D_BD
6
SMA
6T68
AY
L5
BLM
31K
N10
2
R37
60.4
R39
60.4
C42
10nF G
ND
_B
I/O1
1G
ND
2I/O
23
I/O2
4V
bus
5I/O
16
U14
USB
LC6-
2SC
6Y
C44 1u
F
GN
D_B
VC
OM
D7
SZM
M3Z
4V7T
1GR
6218
kC
612.
2nF
GN
D_B
GN
D_BR68
10k
VB
AT
62
C14
61
S14
60B
14_1
359
S13
58
C13
57
C12
56
S12
55B
12_1
154
S11
53
C11
52
C10
51
S10
50B
10_9
49
S948
C0
26
C1
27
S128
B2_
129
S230
C2
31
C3
32
S333
B4_
334
S435
C4
36
C5
37
S538
B6_
539
S640
C6
41
C7
42
S743
B8_
744
S845
C8
46
C9
47
ISO
Hp
7
ISO
Hm
8
ISO
Lp_S
DI
3
ISO
Lm_N
CS4
GPI
O8_
SCK
1G
PIO
9_SD
O2
DGND 9
VC
OM
5
CGND 6
GPI
O1_
FAU
LT_H
10
GPI
O2_
FAU
LT_L
11
GPI
O3
12G
PIO
413
GPI
O5
14G
PIO
615
GPI
O7_
WA
KEU
P16
NPNDRV17
VR
EG18
VTR
EF19
SPIE
N20
VA
NA
21
AGND 22
ISEN
SEp
23IS
ENSE
m24
GNDREF 25
CA
P263
CA
P164
GND 65
U13
L996
3
C81
6.8n
FC
826.
8nF
C83
6.8n
FC
856.
8nF
R80
3K9
R81
3K9
R85
3K9
R86
3K9
R76
10K
R77
10K
R78
10K
R79
10K
GN
D_B
Ass
embl
ed fo
r L99
63 in
SPI
R43
10k
VTR
EF
Not
Ass
embl
ed
R22
0
GN
D_B
R67
3K9
C66
6.8n
F
R64
10K R70
NTC
G16
3JH
103H
TDS
GN
D_B
GN
D_B
VTR
EF
NTC
_IN
TER
NA
L_IN
PUT
C73
4.7n
F
C0
C1
C2
C4
C5
C6
C7
C8
NTC
1+
C9
C10
C11
C12
C13
C14
C3
VB
AT_
CEL
L
C74
4.7n
F
C75 4.7n
FC
76 4.7n
F
GN
D_B
NTC
2+N
TC3+
NTC
4+
NTC
1-N
TC2-
NTC
3-N
TC4-
C77
4.7n
F
C78
4.7n
F
C79 4.7n
FC
80 4.7n
F
GN
D_B
GN
D_B
VB
AT_
CEL
LC
13C
11C
9C
7C
5C
3C
1G
ND
_B
C12
C10
C8
C6
C4
C2
C0
GN
D_B
C14
NTC
1+N
TC2+
NTC
3+N
TC4+
NTC
1-N
TC2-
NTC
3-N
TC4-
C43
22pF
C47
22pF
VC
OM
MIS
O_L
9963
MO
SI_L
9963
SCK
_L99
63
CS_L
9963
C93
47nF
C92
47nF
C91
68nF
C90
33pF
C89
10uF
R93
100
R94
100
GN
D_B
ISEN
SEM
ISEN
SEP
ISEN
SEP
ISEN
SEM
NTC
_IN
TER
NA
L_IN
PUT
R58
6K2
ISO
Hp_
L996
3_ou
tput
ISO
Hm
_L99
63_o
utpu
t
Not
Ass
embl
edC
3847
nF
Not
Ass
embl
edC
5047
nF
L6
ESM
IT41
80
R49
60.4
R53
60.4
C53
10nF
I/O1
1G
ND
2I/O
23
I/O2
4V
bus
5I/O
16
U15
USB
LC6-
2SC
6Y
C55 1u
FC
5422
pF
C57
22pF
GN
D_B
Ass
embl
ed fo
r L99
63 in
SPI
R46
33R
Ass
embl
ed fo
r L99
63 in
SPI
R57
33R
Ass
embl
ed fo
r L99
63T
R47
0
Ass
embl
ed fo
r L99
63T
R54
0
GN
D_B
ISO
Lm_L
9963
ISO
Lp_L
9963
VC
OM
R21
10k
VB
AT_
UP
FAU
LTL_
L996
3
VB
AT_
UP
1 2 3 4
ISO
POR
T1
FAU
LTH
_L99
63
ISO
Hm
_L99
63_o
utpu
tIS
OH
p_L9
963_
outp
ut
1 2
4 3
U22 TL
X92
91
FAU
LTL_
L996
3R13
1
470R
GN
D_B
GN
D
R13
010
k
VD
D5
FAU
LT_1
Ass
embl
ed fo
r L99
63T
R12
9
10k
GN
D_B
CS_L
9963
MO
SI_L
9963
MIS
O_L
9963
SCK
_L99
63
FAU
LTL_
L996
3
TP6 G
ND
BTP
7 GN
DB
GN
D_B
GN
D_B
1 2 3 4 5 6 7 8 9 10 11 12 13 14
15 16 17 18 19 20 21 22 23 24 25 26 27 28
P2V
BA
T_C
ELL
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
ISEN
SEP
ISEN
SEM
NTC
1+N
TC2+
NTC
3+N
TC4+
NTC
1-N
TC2-
NTC
3-N
TC4-
FAU
LTH
_L99
63FA
ULT
H_L
9963
C15
547
nF
GN
D_B
TP1 C1
4
TP10 C1
3
TP11 C1
2
TP12 C1
1
TP13 C1
0
TP14 C9
TP15 C8
TP16 C7
TP17 C6
TP18 C5
TP19 C4
TP20 C3
TP21 C2
TP22 C1
TP23 C0
1kR15
6
D13
LED
GN
D_B
R16
8
0
R16
2
0R
164
0R
166
0R
167
0
R16
50
R16
10
NC
R15
90
R16
30
NC
R16
00
NTC
1-N
TC2- N
CR
170
0N
CR
169
0N
TC4-
NTC
3-
VB
AT_
FAU
LT
Add
ition
alce
llin
put
conn
ecto
rfor
singl
eboa
rdBM
Sde
mon
strat
ion
like
48v
BMS
L996
3/L9
963T
trans
ceiv
eras
sem
bly
note
:
EVAL-L9963-NDSEVAL-L9963 Evaluation board schematic
DB4192 - Rev 1 page 8/12
8 Board layout
Figure 5. Assembly TOP
Figure 6. Inner 1
EVAL-L9963-NDSBoard layout
DB4192 - Rev 1 page 9/12
Figure 7. Inner 2
Figure 8. Assembly BOTTOM
EVAL-L9963-NDSBoard layout
DB4192 - Rev 1 page 10/12
Revision history
Table 3. Document revision history
Date Version Changes
06-Apr-2020 1 Initial release.
EVAL-L9963-NDS
DB4192 - Rev 1 page 11/12
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to STproducts and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. STproducts are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design ofPurchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or servicenames are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
EVAL-L9963-NDS
DB4192 - Rev 1 page 12/12
top related