computer architecture: intro beginnings j. schmalzel s. mandayam

Computer Architecture: IntroBeginnings

J. Schmalzel

S. Mandayam

CourseIntroductionOverviewContent launch: Module 1

Structure & Conduct of the Course

Discussion v. LecturingInteraction: Question/Comment TicketTeam-learningIn-class labsOut-of-class labs, readings, problems

Introduction

Instructors: J. Schmalzel, S. MandayamCourse

Digital Foundations Introduction to Embedded Processors The Embedded Development Environment Interfacing to the Physical World Hardware and Software Trade-Offs

Course Goal

Goal: Impart knowledge of computer architecture to support informed decisions about the hardware, software, and the hardware/software trade-offs that underlie the computing paradigm.

Objectives, 1

Describe major functional elements of CISC, RISC architectures

Perform detailed analysis and synthesis of combinatorial and sequential subsystems using schematic and/or behavioral design capture w/ sim

Describe principles and applications of the three basic computing elements: CPU, MEM, I/O

Use an embedded system that includes diverse architectural features

Objectives, 2

Apply analytic and simulation techniques to predict and verify performance metrics

Design an example architecture using SOTA tools Identify opportunities for hardware and software

trade-offs (Insert your objectives here…) ( …and here)

Digital Foundations

The basic model of a computer system:

CPU MEM

I/O

Central Processing Unit (CPU)

ControlsExecutesComputes (Fixed- and/or Floating-

Point)

Memory

Program storeData storageHigh-speedLow-speedVolatile, Non-volatile

RAM, ROM, FLASH (EEPROM)

FastSlow

Input/Output (I/O)

Communication between CPU and outside world

FastSlowStandardized (e.g., IEEE 802.11b)Parallel (IEEE 1184)Serial (USB

2.0)

Hierarchical View of EP and Digital Systems

CPU MEM

I/O

GatesBoolean Algebra

Design Techniques

MSI Functions

State Machines

Interface Method

Computer Architecture

Operating System

HLLs

Number Systems

Binary Hexadecimal Octal

For an n-bit binary number:Base notation. For a k-bit binary number with n-bits to the left of

the radix point and m-bits to the right of the radix point.

For example, 1101001.101 = ______________10

= (64 + 32 + 8 + 1) . (0.5 + 0.125)

= 105.625

Similarly, for hex:

mm

nn

nn bbbbbbbbb

2...222.222...22 33

22

11

00

11

22

22

11

...16.16...16 11

00

11

hhh nn

Conversions

11111111 ____________(10)(Fast way: 100000000 -1 = 255)

10101010.01 _____________ (10)(AA.416 = 10*16 + 10 + .25 = 170.25)

AB6C.D _________________________ (2) ___________(10)(1010101101101100.1101; 10*4096 + 11*256 + 6*16 + 12 + 13/16 = 43,884.8125)

Coding

Binary system must be used to accomplish many functions such as arithmetic and data transmission. A code defines the mapping between binary digits and the intended application.

Example Codes

Gray code: Only one bit change between adjacent codes (000010110100 101111011001000…)

Binary-Coded Decimal (BCD): Direct (but inefficient) coding of decimal numbers using 4 bits

2’s ComplementNeed: A method to represent negative numbers. Can use a sign bit + magnitude; e.g., +5: 0 101, -5: 1 101, but there are better codes. The 2’s Complement is one.

1’s Complement: Complement each bit.1’s Complement of 11011 is 00100

2’s complement: 1’s complement + 1Example: Find 2’s complement of 1001100. _______________ (0110100.)

To check, sum of the positive and negative codes should sum to zero (ignore overflow out of msb). (“By inspection” trick: Working from right to left, write down all zeros until the first 1. Write it down, too, then complement every bit after that.)

Boolean Algebra

True/False High/Low On/Off +5 Vdc / 0 Vdc (+3.3 Vdc / 0 Vdc)

Notation Variable by itself is assumed “true” Variable with a symbol denotes

complementation: ¯ ~ * /

Boolean Identities X0=0 X1=X XX=X XX*=0 X+0=X X+1=1 X+X=X X+X*=1 X**=X

Commutative Laws:

X+Y=Y+X

XY=YX Associative Laws:

X+(Y+Z)=(X+Y)+Z

X(YZ)=(XY)Z Distributive Laws:

X(Y+Z)=XY+XZ DeMorgan’s Theorems:

(XY)*=X*+Y* (X+Y)*=X* Y*

Gates (p. 63 M&K)

AND ( ^ • & C: & )

OR ( + C: | )

NOT {Inverter} ( ¯ ~ * / C: ~ )

XOR ( C: )

NAND

NOR

XNOR

Combinatorial Design Process

Problem statementTruth table and describing Boolean AlgebraSimplificationImplementationVerification

Design Examples

Full Adder (Step 1: Design a device that performs binary addition, including carry input.)

FA

A

B

Ci

S

Co

Full Adder Truth Table (Step 2)

0 0 0 0 0

Ci A B S Co

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Sum-of-Product Boolean expressions for S and Co:

S = Ci*A*B + Ci*AB* + CiA*B* + CiAB

Co = Ci*AB + CiA*B + CiAB* + CiAB

Graphical Simplification (Step 3)

0 1

0

1

00

01

11

10

Co

0

00

1

1 1

Ci

AB

BCi

AB

ACi

Co = AB + ACi + BCi

A Karnaugh-Map organizes truth table entries as a gray code--only one variable changes between adjacent cells. This lets you use the identities X+X*=1 and X*1=X to simplify by inspection. For example, the AB subcube: ABCi* + ABCi = AB(Ci*+Ci) = AB(1) = AB

Other Simplification Methods

Quine-McCluskey algorithm

“Espresso”http://www-cad.eecs.berkeley.edu:80/Software/software.html

http://cse.bellarmine.edu/espresso (C. Staley; Find it on download.com)

Espresso Demo

Simplify So and Co for FA

Implementation (Step 3)Translate the simplified BA to a network of gates:

&

&

&

+

CiA

CiB

AB

Co

Verification (Step 4)Verify the proper behavior of the design. Use simulation techniques to present test vectors and compare responses to predictions.

Exhaustive v. Statistical (Monte Carlo)

Combinatorial Function Blocks

DecodersMultiplexers

Digital Foundations, cont.

The basic model of a computer system:

CPU MEM

I/O

Real Gates

Logic levels are voltage levelsFinite current driveTiming diagrams Finite switching speedPropagation delaysNoise

Logic Levels are Voltage LevelsVdd

Vss

High

Low

VOHmin

VOLmax

VILmax

VIHmin

VOHtyp

VOLtyp

Finite Current Levels

VOH’/VOL’

+

RS

VOH/VOL

The electrical circuit model for a digital output (or input) includes a series impedance. This helps explain why a gate can’t source/sink unlimited amounts of current (mA v. A).

Finite Switching SpeedsExample: Switching speed of an inverter. A timing diagram shows behavior as it develops with time.

Input (Ideal)

Output

tr tf

Finite Propagation DelaysExample: Switching speed of an inverter.

Input (Ideal)

Output

tPDLH tPDHL

Noise

How well logic is able to reject noise is described by its Noise Immunity. The Noise Margin (NM) is the predicted ability of a device to handle noise on its inputs and still reliably determine the correct logic levels.

NML = VOLmax - VILmax

NMH = VOHmin - VIHmin

Logic Levels/Voltage Levels for 74HC138 w/ VCC=5 Vdc

Vdd

Vss

High

Low

VOHmin

VOLmax

VILmax

VIHmin

VOHtyp

VOLtyp

3.5 V (0.7*5.0)

1.5 V (0.3*5.0)

4.9 V (5.0-0.1)

4.999

@IOH = -20A

0.1 V (0.0+0.1)

0.001 @IOL = +20A

Variation in VOH and VOL

VOH or VOL

IOH

IOL This is reference direction--that’s why IOH is negative.

Ideal VOH or VOL

+

Rs

What is a typical Rs?

Calculation of Rs at IOL of 4 mA

VOH or VOL

IOH

IOL This is reference direction--that’s why IOH is negative.

Ideal VOH or VOL

+

Rs

Use 6 Vdc values: 0.26V/.004A = 65

Propagation delay (6 Vdc)

From A, B, or C to any Y output: Max 38 ns

From Enable to any Y output: Max 33 ns

Questions, Comments, Discussion