altera stratix iii ep3sl150 development & education...
TRANSCRIPT
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Cover Page 1.1
DE3 Base Board
B
1 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Cover Page 1.1
DE3 Base Board
B
1 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Cover Page 1.1
DE3 Base Board
B
1 32Thursday, September 04, 2008
10 ~ 15
01 TOP 01 ~ 03
0706
PAGE
22
04
SCHEMATIC
ALTERA Stratix III EP3SL150 Development & Education Board
08 ~ 09
CONTENTCover Page, Placement,TOP
05 HSTC Connector DHSTC Connector C
10 Power
HSTC Connector B
08 USB DEVICE 16
02 HSTC Connector A
HSTC Connector D
07 IN/OUTDDR2 SO-DIMM06 DDR2 SO-DIMM
04 HSTC Connector C
ISP 1761 USB Hi-Speed OTG
03 HSTC Connector B
09 EP3SL150
05
17 ~ 21
HSTC Connector A
CLOCK, LED, 7-Segment, Button, GPIO Connector
EP3SL150 BANK1...BANK8, POWER, CONFIGPOWER 1.1V, 3.3V, 5V, 12V
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Placement 1.1
DE3 Base Board
B
2 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Placement 1.1
DE3 Base Board
B
2 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Placement 1.1
DE3 Base Board
B
2 32Thursday, September 04, 2008
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
OTG_DC_DACKOTG_HC_DACK
OTG_OE_n
OTG_D[0..31]
OTG_DC_DREQ
OTG_RESET_n
12MHZ
OTG_HC_DREQ
OTG_HC_IRQ
OTG_A[1..17]
OTG_DC_IRQ
OTG_CS_nOTG_WE_n
JTAG_TCKJTAG_TMSJTAG_TDOFPGA_TDO
nCONFIGCPU_RST_n
Button[0..3]
HSTCB_RX_n[0..29]
HSTCB_TX_p[0..29]HSTCB_TX_n[0..29]
HSTCB_RX_p[0..29]
HSTCB_SCLHSTCB_SDA
LEDR[0..7]LEDG[0..7]LEDB[0..7]
HEX0_DPHEX1_DP
HEX0_D[0..6]HEX1_D[0..6]
SW[0..3]
DIP_SW[0..7]
HSTCA_TX_p[0..15]
HSTCA_RX_p[0..15]
HSTCA_TX_n[0..15]
SD_CLKSD_CMDSD_WPnSD_DAT0SD_DAT1SD_DAT2SD_DAT3
OSC_BAOSC_BBOSC_BCOSC_BDOSC1_50
EXT_CLKCLK_OUT
JTAG_TCKJTAG_TMS
JTAG_TDOHSTCD_TDO
HSTCD_CLKIN_n[0..1]HSTCD_CLKIN_p[0..1]
HSTCD_TX_p[0..29]
HSTCD_RX_n[0..29]
HSTCD_TX_n[0..29]
HSTCD_SDAHSTCD_SCL
HSTCD_RX_p[0..29]
HSTCD_CLKOUT_p[0..1]HSTCD_CLKOUT_n[0..1]
POWER_ON
JTAG_TMSJTAG_TCK
HSTCD_TDOHSTCC_TDO
HSTCD_EN
HSTCC_CLKOUT_p[0..1]HSTCC_CLKOUT_n[0..1]
JTAG_TMSJTAG_TCK
HSTCC_TDOHSTCB_TDO
HSTCC_TX_p[0..29]
HSTCC_RX_n[0..29]
HSTCC_TX_n[0..29]
HSTCC_SDAHSTCC_SCL
HSTCC_RX_p[0..29]
POWER_ON
HSTCC_CLKIN_n[0..1]HSTCC_CLKIN_p[0..1]
HSTCC_EN
HSTCB_RX_n[0..29]
HSTCB_SCL
HSTCB_TX_p[0..29]
HSTCB_SDA
HSTCB_TX_n[0..29]
HSTCB_RX_p[0..29]
HSTCB_CLKIN_n[0..1]HSTCB_CLKIN_p[0..1]
POWER_ON
JTAG_TMSJTAG_TCK
HSTCB_TDOHSTCA_TDO
HSTCB_CLKOUT_p[0..1]HSTCB_CLKOUT_n[0..1]
HSTCB_EN
HSTCA_RX_n[0..29]
HSTCA_TX_p[0..29]HSTCA_TX_n[0..29]
HSTCA_RX_p[0..29]
HSTCA_SCLHSTCA_SDA
POWER_ON
HSTCA_CLKOUT_n[0..1]HSTCA_CLKOUT_p[0..1]
JTAG_TMSJTAG_TCK
HSTCA_TDO
HSTCA_EN
HSTCA_CLKIN_n[0..1]HSTCA_CLKIN_p[0..1]
OSC2_50
OSC_BAOSC_BBOSC_BCOSC_BD
EXT_CLKOSC2_50
CLK_OUT
OSC1_50
nCONFIGCPU_RST_n
HEX0_DPHEX1_DP
LEDR[0..7]LEDG[0..7]LEDB[0..7]
HEX0_D[0..6]HEX1_D[0..6]
Button[0..3]SW[0..3]
DIP_SW[0..7]
SD_DAT2SD_DAT3
SD_CLKSD_CMDSD_WPnSD_DAT0SD_DAT1
12MHZ
HSTCA_CLKIN_2
HSTCA_CLKOUT_2
HSTCB_CLKIN_2
HSTCB_CLKOUT_2
HSTCC_CLKIN_2
HSTCC_CLKOUT_2
HSTCD_CLKIN_2
HSTCD_CLKOUT_2
HSTCA_CLKOUT_n[0..1]HSTCA_CLKOUT_p[0..1]
HSTCA_CLKIN_n[0..1]HSTCA_CLKIN_p[0..1]
JVC[0..3]
JVC[0..3]
BC_S0BC_S1
POWER_ON
BA_S0
BD_S0
BA_S1
BD_S1
BB_S0BB_S1
HSTCA_ENHSTCB_ENHSTCC_ENHSTCD_EN
HSTCA_RX_n[0..15]
FPGA_TDOFPGA_SM_TDO
FPGA_SM_TDO
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
DE3 Base Board - Top 1.1
DE3 Base Board
B
3 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
DE3 Base Board - Top 1.1
DE3 Base Board
B
3 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
DE3 Base Board - Top 1.1
DE3 Base Board
B
3 32Thursday, September 04, 2008
Onboard USB-Blaster
USB-Blaster
JTAG_TCK
JTAG_TDIJTAG_TDO
JTAG_TMS
12MHZ
HSTCD_ENHSTCC_EN
JVC[0..3]
HSTCB_EN
BD_S0
HSTCA_EN
BD_S1
POWER_ON
BC_S0BC_S1
BB_S0
BA_S0
BB_S1
BA_S1
FPGA_SM_TDOFPGA_TDO
Page 9~12
07 IN/OUT Port
LEDG[0..7]
Button[0..3]
HEX1_D[0..6]
HEX1_DPHEX0_DP
nCONFIGCPU_RST_n
HEX0_D[0..6]
LEDR[0..7]
LEDB[0..7]
OSC_BD
SD_CLK
SD_DAT0
CLK_OUT
SD_DAT1SD_DAT2SD_DAT3
SD_CMD
SW[0..3]
SD_WPn
DIP_SW[0..7]
OSC_BAOSC_BB
EXT_CLK
OSC_BC
OSC2_50OSC1_50
HSTCA_CLKIN_n[0..1]
HSTCA_CLKOUT_n[0..1]HSTCA_CLKOUT_p[0..1]
HSTCA_CLKIN_p[0..1]
HSTCA_RX_n[0..15]
HSTCA_TX_p[0..15]HSTCA_TX_n[0..15]
HSTCA_RX_p[0..15]
Page 19
10 Power
BD_S0
POWER_ON
BD_S1
BC_S0BC_S1
BA_S0BA_S1BB_S0BB_S1
Page 14~18
09 EP3SL150
HSTCC_CLKOUT_n[0..1]
HSTCC_CLKIN_n[0..1] HSTCA_CLKIN_n[0..1]HSTCC_CLKIN_p[0..1]
HSTCC_CLKOUT_p[0..1]
HSTCA_CLKIN_p[0..1]
LEDG[0..7]
HSTCA_SCL
HSTCD_CLKOUT_n[0..1]
Button[0..3]
HSTCB_SCL
OTG_DC_DACK
HSTCD_CLKOUT_p[0..1]
HEX1_D[0..6]
HSTCC_SCL
HSTCD_SCL
OTG_HC_DACK
OTG_OE_n
OTG_D[0..31]
HSTCD_CLKIN_n[0..1] HSTCB_CLKIN_n[0..1]
OTG_DC_DREQ
OTG_RESET_n
HSTCA_SDA
HEX0_D[0..6]
HSTCB_SDA
HSTCA_CLKOUT_n[0..1]
FPGA_TDI
HSTCD_CLKIN_p[0..1]
HSTCC_SDA
HSTCB_CLKIN_p[0..1]
HSTCA_CLKOUT_p[0..1]
nCONFIGFPGA_TMS
LEDR[0..7]
OTG_HC_DREQ
CPU_RST_n
HSTCB_CLKOUT_n[0..1]
OTG_A[1..17]
HSTCB_CLKOUT_p[0..1]
FPGA_TDO
LEDB[0..7]
OTG_WE_nOTG_CS_n
HSTCD_SDA
OTG_HC_IRQ
FPGA_TCK
OTG_DC_IRQ
HEX0_DPHEX1_DP
OSC_BD
HSTCD_TX_n[0..29]
HSTCC_RX_n[0..29]
HSTCB_TX_n[0..29]
HSTCC_TX_p[0..29]
HSTCD_TX_p[0..29]
SW[0..3]
HSTCA_TX_n[0..29]HSTCA_TX_p[0..29]
HSTCC_TX_n[0..29]
SD_CLK
SD_WPn
HSTCB_RX_p[0..29]HSTCD_RX_n[0..29]HSTCD_RX_p[0..29]
CLK_OUT
DIP_SW[0..7]
HSTCA_RX_n[0..29]
OSC2_50
HSTCA_RX_p[0..29]
SD_DAT0
HSTCB_RX_n[0..29]
OSC1_50
HSTCC_RX_p[0..29]
SD_DAT1
HSTCB_TX_p[0..29]
SD_DAT2
OSC_BA
EXT_CLK
SD_DAT3
OSC_BBOSC_BC
SD_CMD
HSTCA_CLKIN_2
HSTCA_CLKOUT_2
HSTCB_CLKIN_2
HSTCB_CLKOUT_2
HSTCC_CLKOUT_2
HSTCC_CLKIN_2
HSTCD_CLKOUT_2
HSTCD_CLKIN_2
JVC[0..3]
Page 4
02 HSTC Connector A
HSTCA_TDIHSTCA_TMSHSTCA_TCK
HSTCA_SCL
HSTCA_TX_n[0..29]
HSTCA_TDO
HSTCA_SDA
HSTCA_RX_p[0..29]HSTCA_RX_n[0..29]
HSTCA_TX_p[0..29]
POWER_ON
HSTCA_EN
HSTCA_CLKIN_2
HSTCA_CLKIN_n[0..1]HSTCA_CLKIN_p[0..1]
HSTCA_CLKOUT_2
HSTCA_CLKOUT_n[0..1]HSTCA_CLKOUT_p[0..1]
Page 7
05 HSTC Connector D
HSTCD_TDI
HSTCD_TX_n[0..29]
HSTCD_TMSHSTCD_TCK
HSTCD_SCL
HSTCD_TDO
HSTCD_RX_p[0..29]
HSTCD_SDA
HSTCD_RX_n[0..29]
HSTCD_TX_p[0..29]
POWER_ON
HSTCD_EN
HSTCD_CLKOUT_2
HSTCD_CLKOUT_n[0..1]HSTCD_CLKOUT_p[0..1]
HSTCD_CLKIN_2
HSTCD_CLKIN_n[0..1]HSTCD_CLKIN_p[0..1]
Page 5
03 HSTC Connector B
HSTCB_TDIHSTCB_TMS
HSTCB_RX_n[0..29]
HSTCB_TCK
HSTCB_SCL
HSTCB_TX_p[0..29]
HSTCB_TDO
HSTCB_SDA
HSTCB_TX_n[0..29]
HSTCB_RX_p[0..29]
POWER_ON
HSTCB_EN
HSTCB_CLKIN_n[0..1]HSTCB_CLKIN_p[0..1]
HSTCB_CLKOUT_2
HSTCB_CLKOUT_n[0..1]HSTCB_CLKIN_2
HSTCB_CLKOUT_p[0..1]
Page 8
06 DDR2 SO-DIMM
HSTCB_SCLHSTCB_SDA
HSTCB_RX_n[0..29]
HSTCB_TX_p[0..29]HSTCB_TX_n[0..29]
HSTCB_RX_p[0..29]
Page 13
08 USB DEVICE
OTG_DC_DACKOTG_HC_DACK
OTG_OE_n
OTG_D[0..31]
OTG_DC_DREQ
OTG_RESET_n
12MHZ
OTG_HC_DREQ
OTG_HC_IRQ
OTG_A[1..17]
OTG_DC_IRQ
OTG_CS_nOTG_WE_n
Page 6
04 HSTC Connector C
HSTCC_TDIHSTCC_TMS
HSTCC_RX_p[0..29]
HSTCC_TCK
HSTCC_SCL
HSTCC_TDO
HSTCC_RX_n[0..29]
HSTCC_SDA
HSTCC_TX_p[0..29]HSTCC_TX_n[0..29]
POWER_ON
HSTCC_EN
HSTCC_CLKOUT_n[0..1]
HSTCC_CLKIN_n[0..1]
HSTCC_CLKOUT_p[0..1]
HSTCC_CLKIN_p[0..1]
HSTCC_CLKOUT_2
HSTCC_CLKIN_2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HSTCA_RX_n20
HSTCA_RX_n18
HSTCA_RX_n19
HSTCA_RX_p20
HSTCA_RX_p18
HSTCA_RX_p19
HSTCA_RX_n29
HSTCA_RX_n25
HSTCA_RX_n28
HSTCA_RX_n27
HSTCA_RX_p29
HSTCA_RX_p25
HSTCA_RX_p27
HSTCA_RX_p28
HSTCA_RX_n24HSTCA_RX_p24
HSTCA_RX_n23HSTCA_RX_p23
HSTCA_RX_n22HSTCA_RX_p22
HSTCA_RX_n21HSTCA_RX_p21
HSTCA_RX_n12
HSTCA_RX_n17
HSTCA_RX_n13
HSTCA_RX_n14
HSTCA_RX_n15
HSTCA_RX_n16
HSTCA_RX_p12
HSTCA_RX_p17
HSTCA_RX_p13
HSTCA_RX_p14
HSTCA_RX_p15
HSTCA_RX_p16
HSTCA_RX_p1
HSTCA_RX_p2
HSTCA_RX_p3
HSTCA_RX_p4
HSTCA_RX_p5
HSTCA_RX_p6
HSTCA_RX_p7
HSTCA_RX_p0
HSTCA_RX_p8
HSTCA_RX_n1
HSTCA_RX_n2
HSTCA_RX_n3
HSTCA_RX_n4
HSTCA_RX_n5
HSTCA_RX_n0
HSTCA_RX_n6
HSTCA_RX_n7
HSTCA_RX_n8
HSTCA_RX_p11
HSTCA_RX_p9
HSTCA_RX_p10
HSTCA_RX_n11
HSTCA_RX_n9
HSTCA_RX_n10
HSTCA_CLKIN_n1HSTCA_CLKIN_p1
HSTCA_CLKIN_n0HSTCA_CLKIN_p0
HSTCA_CLKOUT_n1HSTCA_CLKOUT_p1
HSTCA_CLKOUT_n0HSTCA_CLKOUT_p0
HSTCA_TX_n14HSTCA_TX_p14
HSTCA_TX_n12HSTCA_TX_p12
HSTCA_TX_n15HSTCA_TX_p15
HSTCA_TX_n13HSTCA_TX_p13
HSTCA_TX_n16HSTCA_TX_p16
HSTCA_TX_n18HSTCA_TX_p18
HSTCA_TX_n17HSTCA_TX_p17
HSTCA_TX_n20HSTCA_TX_p20
HSTCA_TX_n19HSTCA_TX_p19
HSTCA_TX_n29
HSTCA_TX_n21
HSTCA_TX_n24
HSTCA_TX_n25
HSTCA_TX_n22
HSTCA_TX_n23
HSTCA_TX_n26
HSTCA_TX_n27
HSTCA_TX_n28
HSTCA_TX_p26
HSTCA_TX_p27
HSTCA_TX_p28
HSTCA_TX_p29
HSTCA_TX_p21
HSTCA_TX_p24
HSTCA_TX_p25
HSTCA_TX_p22
HSTCA_TX_p23
HSTCA_TX_n1
HSTCA_TX_n2
HSTCA_TX_n3
HSTCA_TX_n4
HSTCA_TX_n5
HSTCA_TX_n6
HSTCA_TX_n7
HSTCA_TX_n0
HSTCA_TX_n8
HSTCA_TX_n9
HSTCA_TX_n11
HSTCA_TX_n10
HSTCA_TX_p1
HSTCA_TX_p2
HSTCA_TX_p3
HSTCA_TX_p4
HSTCA_TX_p5
HSTCA_TX_p0
HSTCA_TX_p6
HSTCA_TX_p7
HSTCA_TX_p8
HSTCA_TX_p11
HSTCA_TX_p9
HSTCA_TX_p10
HSTCA2_TDO
HSTCA2_TCK
HSTCA_PSNT_n
HSTCA2_TMS
HSTCA_EN
HSTCA2_TDI
HSTCA_RX_p1
HSTCA_RX_p2
HSTCA_RX_p3
HSTCA_RX_p4
HSTCA_RX_p5
HSTCA_RX_p6
HSTCA_RX_p7
HSTCA_RX_p0
HSTCA_RX_p8
HSTCA_RX_n1
HSTCA_RX_n2
HSTCA_RX_n3
HSTCA_RX_n4
HSTCA_RX_n5
HSTCA_RX_n6
HSTCA_RX_n7
HSTCA_RX_n8
HSTCA_RX_n0
HSTCA_RX_p11
HSTCA_RX_p9
HSTCA_RX_p10
HSTCA_RX_n11
HSTCA_RX_n9
HSTCA_RX_n10
HSTCA_RX_n12
HSTCA_RX_n17
HSTCA_RX_n13
HSTCA_RX_n14
HSTCA_RX_n15
HSTCA_RX_n16
HSTCA_RX_p12
HSTCA_RX_p17
HSTCA_RX_p13
HSTCA_RX_p14
HSTCA_RX_p15
HSTCA_RX_p16
HSTCA_TX_n1
HSTCA_TX_n2
HSTCA_TX_n3
HSTCA_TX_n4
HSTCA_TX_n5
HSTCA_TX_n6
HSTCA_TX_n7
HSTCA_TX_n0
HSTCA_TX_n8
HSTCA_TX_p1
HSTCA_TX_p2
HSTCA_TX_p3
HSTCA_TX_p4
HSTCA_TX_p5
HSTCA_TX_p0
HSTCA_TX_p6
HSTCA_TX_p7
HSTCA_TX_p8
HSTCA_TX_n9
HSTCA_TX_n11
HSTCA_TX_n10
HSTCA_TX_p11
HSTCA_TX_p9
HSTCA_TX_p10
HSTCA_TX_n14HSTCA_TX_p14
HSTCA_TX_n12HSTCA_TX_p12
HSTCA_TX_n15HSTCA_TX_p15
HSTCA_TX_n13HSTCA_TX_p13
HSTCA_TX_n16HSTCA_TX_p16
HSTCA_TX_n17HSTCA_TX_p17
HSTCA_RX_n23HSTCA_RX_p23
HSTCA_RX_n22HSTCA_RX_p22
HSTCA_RX_n21HSTCA_RX_p21
HSTCA_RX_n29
HSTCA_RX_n25
HSTCA_RX_n28
HSTCA_RX_n27
HSTCA_RX_p29
HSTCA_RX_p25
HSTCA_RX_p27
HSTCA_RX_p28
HSTCA_RX_n24HSTCA_RX_p24
HSTCA_RX_n20
HSTCA_RX_n18
HSTCA_RX_n19
HSTCA_RX_p20
HSTCA_RX_p19
HSTCA_RX_p18
HSTCA_TX_n29
HSTCA_TX_n21
HSTCA_TX_n24
HSTCA_TX_n25
HSTCA_TX_n22
HSTCA_TX_n23
HSTCA_TX_n26
HSTCA_TX_n27
HSTCA_TX_n28
HSTCA_TX_p26
HSTCA_TX_p27
HSTCA_TX_p28
HSTCA_TX_p29
HSTCA_TX_p21
HSTCA_TX_p24
HSTCA_TX_p25
HSTCA_TX_p22
HSTCA_TX_p23
HSTCA_TX_n18
HSTCA_TX_n20HSTCA_TX_p20
HSTCA_TX_p18HSTCA_TX_n19HSTCA_TX_p19
HSTCA1_TDI
HSTCA1_TMS HSTCA1_TCK
HSTCA1_TDO
HSTCA_SDA HSTCA_SCL
HSTCA_PSNT_n
HSTCA1_TMSHSTCA1_TCK
HSTCA1_TDIHSTCA1_TDO
HSTCA2_TDIHSTCA2_TMSHSTCA2_TCK
HSTCA2_TDO
HSTCA_PSNT_n
POWER_ON
HSTCA_TX_n10
HSTCA_TX_n11
HSTCA_TX_n12
HSTCA_TX_n13
HSTCA_TX_n14
HSTCA_TX_n15
HSTCA_TX_n16
HSTCA_TX_n9
HSTCA_TX_n17
HSTCA_TX_p10
HSTCA_TX_p11
HSTCA_TX_p12
HSTCA_TX_p13
HSTCA_TX_p14
HSTCA_TX_p9
HSTCA_TX_p15
HSTCA_TX_p16
HSTCA_TX_p17
HSTCA_CLKOUT_n1HSTCA_CLKOUT_p1
HSTCA_TX_n29
HSTCA_TX_n21
HSTCA_TX_n24
HSTCA_TX_n25
HSTCA_TX_n22
HSTCA_TX_n23
HSTCA_TX_n26
HSTCA_TX_n27
HSTCA_TX_n28
HSTCA_TX_p26
HSTCA_TX_p27
HSTCA_TX_p28
HSTCA_TX_p29
HSTCA_TX_p21
HSTCA_TX_p24
HSTCA_TX_p25
HSTCA_TX_p22
HSTCA_TX_p23
HSTCA_TX_n18
HSTCA_TX_n20HSTCA_TX_p20
HSTCA_TX_n19
HSTCA_TX_p18
HSTCA_TX_p19
HSTCA_CLKIN_n1HSTCA_CLKIN_p1
HSTCA_RX_p26HSTCA_RX_n26
HSTCA_RX_p26HSTCA_RX_n26
HSTCA_CLKIN_n0HSTCA_CLKIN_p0
HSTCA_CLKIN_n1HSTCA_CLKIN_p1
HSTCA_CLKIN_2HSTCA_CLKOUT_2
HSTCA_CLKOUT_n1HSTCA_CLKOUT_p1
HSTCA_CLKOUT_n0HSTCA_CLKOUT_p0
HSTCA_TX_p[0..29]HSTCA_TX_n[0..29]HSTCA_RX_p[0..29]HSTCA_RX_n[0..29]
HSTCA_SDA
HSTCA_CLKIN_p[0..1]HSTCA_CLKIN_n[0..1]
HSTCA_SCL
HSTCA_TDO
HSTCA_CLKOUT_p[0..1]HSTCA_CLKOUT_n[0..1]
HSTCA_TMSHSTCA_TDI
HSTCA_TCK
POWER_ON
HSTCA_EN
HSTCA_CLKIN_2 HSTCA_CLKOUT_2
12V VCC33 VCC33 12V
VCC50
BA_VREF
VCC50
BA_VREF BA_VTTBA_VTT
VCC33
VCC3312V
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
High Speed Terasic Connector A Top and Bottom 1.1
DE3 Base Board
C
4 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
High Speed Terasic Connector A Top and Bottom 1.1
DE3 Base Board
C
4 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
High Speed Terasic Connector A Top and Bottom 1.1
DE3 Base Board
C
4 32Thursday, September 04, 2008
HSTC Connector A-Top HSTC Connector A-Bottom
R11 100R11 100
LINKA
LEDR
LINKA
LEDR
R17 100R17 100
R20 100R20 100
R10 100R10 100
R18 100R18 100
181
182
183
184
188
185
186
187
192
189
190
191
J1
QTH-090
181
182
183
184
188
185
186
187
192
189
190
191
J1
QTH-090
185185
181181
186186
182182
187187
183183
188188
184184
1 13 35 57 79 9
11 1113 1315 1517 1719 1921 2123 2325 2527 2729 2931 3133 3335 3537 3739 3941 4143 4345 4547 4749 4951 5153 5355 5557 5759 59
2244668810101212141416161818202022222424262628283030323234343636383840404242444446464848505052525454565658586060
61 6163 6365 6567 6769 6971 7173 7375 7577 7779 7981 8183 8385 8587 8789 8991 9193 9395 9597 9799 99
101 101103 103105 105107 107109 109111 111113 113115 115117 117119 119
6262646466666868707072727474767678788080828284848686888890909292949496969898100100102102104104106106108108110110112112114114116116118118120120
122122124124126126128128130130132132134134136136138138140140142142144144146146148148150150152152154154156156158158160160162162164164166166168168170170172172174174176176178178180180
121 121123 123125 125127 127129 129131 131133 133135 135137 137139 139141 141143 143145 145147 147149 149151 151153 153155 155157 157159 159161 161163 163165 165167 167169 169171 171173 173175 175177 177179 179
189 189190 190191 191192 192
R22 100R22 100
R12 100R12 100
R3 100R3 100
R5 100R5 100
R8 100R8 100
R2 100R2 100
C310uC310u
R9 100R9 100
C610u
C610u
C510u
C510u
R15 100R15 100
C210uC210u
C410uC410u
R6 100R6 100
C110uC110u
R23 100R23 100
181
182
183
184
188
185
186
187
189
192
190
191
J2
QSH-090
181
182
183
184
188
185
186
187
189
192
190
191
J2
QSH-090
11335577991111131315151717191921212323252527272929313133333535373739394141434345454747494951515353555557575959
2 24 46 68 8
10 1012 1214 1416 1618 1820 2022 2224 2426 2628 2830 3032 3234 3436 3638 3840 4042 4244 4446 4648 4850 5052 5254 5456 5658 5860 60
61616363656567676969717173737575777779798181838385858787898991919393959597979999101101103103105105107107109109111111113113115115117117119119
62 6264 6466 6668 6870 7072 7274 7476 7678 7880 8082 8284 8486 8688 8890 9092 9294 9496 9698 98
100 100102 102104 104106 106108 108110 110112 112114 114116 116118 118120 120
121121123123125125127127129129131131133133135135137137139139141141143143145145147147149149151151153153155155157157159159161161163163165165167167169169171171173173175175177177179179
122 122124 124126 126128 128130 130132 132134 134136 136138 138140 140142 142144 144146 146148 148150 150152 152154 154156 156158 158160 160162 162164 164166 166168 168170 170172 172174 174176 176178 178180 180
181 181182 182183 183184 184
185 185186 186187 187188 188
189189190190191191192192
JTAG_A
JTAG Controller
HSTC1_TDI
HSTC2_TDI
HSTC1_TMS
HSTC_TDO
HSTC2_TMS
HSTC1_TCK
HSTC2_TCK
HSTC_PSNT_nHSTC_EN
HSTC1_TDO
HSTC2_TDO
HSTC_TDIHSTC_TMSHSTC_TCK
R24
120
R24
120
R21 100R21 100
R4 100R4 100
R19 100R19 100
R1 100R1 100
R13 100R13 100
R7 100R7 100
R14 100R14 100
R16 100R16 100
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HSTCB_RX_p0HSTCB_RX_n0
HSTCB_CLKIN_n1HSTCB_CLKIN_p1
HSTCB_CLKIN_n0HSTCB_CLKIN_p0
HSTCB_CLKOUT_n1HSTCB_CLKOUT_p1
HSTCB_CLKOUT_n0HSTCB_CLKOUT_p0
HSTCB_TX_n0HSTCB_TX_p0
HSTCB2_TDO
HSTCB2_TCK
HSTCB_PSNT_n
HSTCB2_TMS
HSTCB_EN
HSTCB2_TDI
HSTCB_RX_p0HSTCB_RX_n0HSTCB_TX_n0
HSTCB_TX_p0
HSTCB1_TDI
HSTCB1_TMS HSTCB1_TCK
HSTCB1_TDO
HSTCB_SDA HSTCB_SCL
HSTCB_PSNT_n
HSTCB_RX_p1HSTCB_RX_n1HSTCB_TX_n1
HSTCB_TX_p1
HSTCB_RX_p2HSTCB_RX_n2HSTCB_TX_n2
HSTCB_TX_p2
HSTCB_RX_p3HSTCB_RX_n3HSTCB_TX_n3
HSTCB_TX_p3
HSTCB_RX_p4HSTCB_RX_n4HSTCB_TX_n4
HSTCB_TX_p4
HSTCB_RX_p5HSTCB_RX_n5HSTCB_TX_n5
HSTCB_TX_p5
HSTCB_RX_p6HSTCB_RX_n6HSTCB_TX_n6
HSTCB_TX_p6
HSTCB_RX_p7HSTCB_RX_n7HSTCB_TX_n7
HSTCB_TX_p7
HSTCB_RX_p8HSTCB_RX_n8HSTCB_TX_n8
HSTCB_TX_p8
HSTCB_RX_p9HSTCB_RX_n9
HSTCB_TX_p9HSTCB_TX_n9
HSTCB_RX_p10HSTCB_RX_n10
HSTCB_TX_p10HSTCB_TX_n10
HSTCB_RX_p11HSTCB_RX_n11
HSTCB_TX_p11HSTCB_TX_n11
HSTCB_RX_p12HSTCB_RX_n12
HSTCB_TX_p12HSTCB_TX_n12
HSTCB_RX_p13HSTCB_RX_n13
HSTCB_TX_p13HSTCB_TX_n13
HSTCB_RX_p14HSTCB_RX_n14
HSTCB_TX_p14HSTCB_TX_n14
HSTCB_RX_p15HSTCB_RX_n15
HSTCB_TX_p15HSTCB_TX_n15
HSTCB_RX_p16HSTCB_RX_n16
HSTCB_TX_p16HSTCB_TX_n16
HSTCB_RX_p17HSTCB_RX_n17
HSTCB_TX_p17HSTCB_TX_n17
HSTCB_TX_n18HSTCB_TX_p18
HSTCB_RX_n18HSTCB_RX_p18
HSTCB_TX_n19HSTCB_TX_p19
HSTCB_RX_n19HSTCB_RX_p19
HSTCB_TX_n20HSTCB_TX_p20
HSTCB_RX_n20HSTCB_RX_p20
HSTCB_TX_n21HSTCB_TX_p21
HSTCB_RX_n21HSTCB_RX_p21
HSTCB_TX_n22HSTCB_TX_p22
HSTCB_RX_n22HSTCB_RX_p22
HSTCB_TX_n23HSTCB_TX_p23
HSTCB_RX_n23HSTCB_RX_p23
HSTCB_TX_n24HSTCB_TX_p24
HSTCB_RX_n24HSTCB_RX_p24
HSTCB_TX_n25HSTCB_TX_p25
HSTCB_RX_n25HSTCB_RX_p25
HSTCB_TX_n26HSTCB_TX_p26
HSTCB_RX_n26HSTCB_RX_p26
HSTCB_TX_n27HSTCB_TX_p27
HSTCB_RX_n27HSTCB_RX_p27
HSTCB_TX_n28HSTCB_TX_p28
HSTCB_RX_n28HSTCB_RX_p28
HSTCB_TX_n29HSTCB_TX_p29
HSTCB_RX_n29HSTCB_RX_p29
HSTCB_TX_n27HSTCB_TX_p27
HSTCB_TX_n22HSTCB_TX_p22
HSTCB_TX_n28HSTCB_TX_p28
HSTCB_TX_n23HSTCB_TX_p23
HSTCB_TX_n18HSTCB_TX_p18
HSTCB_TX_n29HSTCB_TX_p29
HSTCB_TX_n24HSTCB_TX_p24
HSTCB_TX_n19HSTCB_TX_p19
HSTCB_TX_n25HSTCB_TX_p25
HSTCB_TX_n20HSTCB_TX_p20
HSTCB_TX_n26HSTCB_TX_p26
HSTCB_TX_n21HSTCB_TX_p21
HSTCB_RX_n27HSTCB_RX_p27
HSTCB_RX_n22HSTCB_RX_p22
HSTCB_RX_n28HSTCB_RX_p28
HSTCB_RX_n23HSTCB_RX_p23
HSTCB_RX_n18HSTCB_RX_p18
HSTCB_RX_n29HSTCB_RX_p29
HSTCB_RX_n24HSTCB_RX_p24
HSTCB_RX_n19HSTCB_RX_p19
HSTCB_RX_n25HSTCB_RX_p25
HSTCB_RX_n20HSTCB_RX_p20
HSTCB_RX_n26HSTCB_RX_p26
HSTCB_RX_n21HSTCB_RX_p21
HSTCB_RX_p1HSTCB_RX_n1 HSTCB_TX_n1
HSTCB_TX_p1
HSTCB_RX_p2HSTCB_RX_n2 HSTCB_TX_n2
HSTCB_TX_p2
HSTCB_RX_p3HSTCB_RX_n3 HSTCB_TX_n3
HSTCB_TX_p3
HSTCB_RX_p4HSTCB_RX_n4 HSTCB_TX_n4
HSTCB_TX_p4
HSTCB_RX_p5HSTCB_RX_n5 HSTCB_TX_n5
HSTCB_TX_p5
HSTCB_RX_p6HSTCB_RX_n6 HSTCB_TX_n6
HSTCB_TX_p6
HSTCB_RX_p7HSTCB_RX_n7 HSTCB_TX_n7
HSTCB_TX_p7
HSTCB_RX_p8HSTCB_RX_n8 HSTCB_TX_n8
HSTCB_TX_p8
HSTCB_RX_p9HSTCB_RX_n9 HSTCB_TX_n9
HSTCB_TX_p9
HSTCB_RX_p10HSTCB_RX_n10 HSTCB_TX_n10
HSTCB_TX_p10
HSTCB_RX_p11HSTCB_RX_n11 HSTCB_TX_n11
HSTCB_TX_p11
HSTCB_RX_p12HSTCB_RX_n12 HSTCB_TX_n12
HSTCB_TX_p12
HSTCB_RX_p13HSTCB_RX_n13 HSTCB_TX_n13
HSTCB_TX_p13
HSTCB_RX_p14HSTCB_RX_n14 HSTCB_TX_n14
HSTCB_TX_p14
HSTCB_RX_p15HSTCB_RX_n15 HSTCB_TX_n15
HSTCB_TX_p15
HSTCB_RX_p16HSTCB_RX_n16 HSTCB_TX_n16
HSTCB_TX_p16
HSTCB_RX_p17HSTCB_RX_n17 HSTCB_TX_n17
HSTCB_TX_p17
HSTCB_PSNT_n
HSTCB1_TCKHSTCB1_TMSHSTCB1_TDIHSTCB1_TDO
HSTCB2_TDOHSTCB2_TDI
HSTCB2_TCKHSTCB2_TMS
POWER_ON
HSTCB_TX_n14HSTCB_TX_p14
HSTCB_TX_n15HSTCB_TX_p15
HSTCB_TX_n10HSTCB_TX_p10
HSTCB_TX_n16HSTCB_TX_p16
HSTCB_TX_n9HSTCB_TX_p9
HSTCB_TX_n11HSTCB_TX_p11
HSTCB_TX_n17HSTCB_TX_p17
HSTCB_CLKOUT_n1HSTCB_CLKOUT_p1
HSTCB_TX_n12HSTCB_TX_p12
HSTCB_TX_n13HSTCB_TX_p13
HSTCB_TX_n27HSTCB_TX_p27
HSTCB_TX_n22HSTCB_TX_p22
HSTCB_TX_n28HSTCB_TX_p28
HSTCB_TX_n23HSTCB_TX_p23
HSTCB_TX_n18
HSTCB_TX_n29HSTCB_TX_p29
HSTCB_TX_n24
HSTCB_TX_p18
HSTCB_TX_p24
HSTCB_TX_n19HSTCB_TX_p19
HSTCB_TX_n25HSTCB_TX_p25
HSTCB_TX_n20HSTCB_TX_p20
HSTCB_TX_n26HSTCB_TX_p26
HSTCB_TX_n21HSTCB_TX_p21
HSTCB_CLKIN_n1HSTCB_CLKIN_p1
HSTCB_CLKOUT_2
HSTCB_CLKOUT_n0HSTCB_CLKOUT_p0
HSTCB_CLKOUT_n1HSTCB_CLKOUT_p1
HSTCB_CLKIN_n1HSTCB_CLKIN_p1
HSTCB_CLKIN_n0HSTCB_CLKIN_p0
HSTCB_CLKIN_2
HSTCB_TX_p[0..29]HSTCB_TX_n[0..29]HSTCB_RX_p[0..29]HSTCB_RX_n[0..29]
HSTCB_SDA
HSTCB_CLKIN_p[0..1]HSTCB_CLKIN_n[0..1]
HSTCB_SCL
HSTCB_TDO
HSTCB_CLKOUT_p[0..1]HSTCB_CLKOUT_n[0..1]
HSTCB_TMSHSTCB_TDI
HSTCB_TCK
POWER_ON
HSTCB_EN
HSTCB_CLKIN_2 HSTCB_CLKOUT_2
VCC3312V
VCC33
12V VCC33 VCC33 12V
VCC50
BB_VREF
VCC50
BB_VREF BB_VTTBB_VTT
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
High Speed Terasic Connector B Top and Bottom 1.1
DE3 Base BoardC
5 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
High Speed Terasic Connector B Top and Bottom 1.1
DE3 Base BoardC
5 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
High Speed Terasic Connector B Top and Bottom 1.1
DE3 Base BoardC
5 32Thursday, September 04, 2008
HSTC Connector B-Top HSTC Connector B-Bottom
C1110uC1110u
C710uC710u
R41 100R41 100
C910uC910u
R35 100R35 100
R42 100R42 100
R46 100R46 100
C1210uC1210u
R37 100R37 100
JTAG_B
JTAG Controller
HSTC1_TDI
HSTC2_TDI
HSTC1_TMS
HSTC_TDO
HSTC2_TMS
HSTC1_TCK
HSTC2_TCK
HSTC_PSNT_nHSTC_EN
HSTC1_TDO
HSTC2_TDO
HSTC_TDIHSTC_TMSHSTC_TCK
R31 100R31 100
R43 100R43 100
LINKB
LEDR
LINKB
LEDR
R28 100R28 100
R47 100R47 100
R39 100R39 100
R40 100R40 100
C1010uC1010u
R36 100R36 100
R34 100R34 100
R45 100R45 100
R32 100R32 100
R25 100R25 100
R38 100R38 100
R30 100R30 100
181
182
183
184
188
185
186
187
192
189
190
191
J3
QTH-090
181
182
183
184
188
185
186
187
192
189
190
191
J3
QTH-090
185185
181181
186186
182182
187187
183183
188188
184184
1 13 35 57 79 9
11 1113 1315 1517 1719 1921 2123 2325 2527 2729 2931 3133 3335 3537 3739 3941 4143 4345 4547 4749 4951 5153 5355 5557 5759 59
2244668810101212141416161818202022222424262628283030323234343636383840404242444446464848505052525454565658586060
61 6163 6365 6567 6769 6971 7173 7375 7577 7779 7981 8183 8385 8587 8789 8991 9193 9395 9597 9799 99
101 101103 103105 105107 107109 109111 111113 113115 115117 117119 119
6262646466666868707072727474767678788080828284848686888890909292949496969898100100102102104104106106108108110110112112114114116116118118120120
122122124124126126128128130130132132134134136136138138140140142142144144146146148148150150152152154154156156158158160160162162164164166166168168170170172172174174176176178178180180
121 121123 123125 125127 127129 129131 131133 133135 135137 137139 139141 141143 143145 145147 147149 149151 151153 153155 155157 157159 159161 161163 163165 165167 167169 169171 171173 173175 175177 177179 179
189 189190 190191 191192 192
R33 100R33 100
R48
120
R48
120
R26 100R26 100
R27 100R27 100
181
182
183
184
188
185
186
187
189
192
190
191
J4
QSH-090
181
182
183
184
188
185
186
187
189
192
190
191
J4
QSH-090
11335577991111131315151717191921212323252527272929313133333535373739394141434345454747494951515353555557575959
2 24 46 68 8
10 1012 1214 1416 1618 1820 2022 2224 2426 2628 2830 3032 3234 3436 3638 3840 4042 4244 4446 4648 4850 5052 5254 5456 5658 5860 60
61616363656567676969717173737575777779798181838385858787898991919393959597979999101101103103105105107107109109111111113113115115117117119119
62 6264 6466 6668 6870 7072 7274 7476 7678 7880 8082 8284 8486 8688 8890 9092 9294 9496 9698 98
100 100102 102104 104106 106108 108110 110112 112114 114116 116118 118120 120
121121123123125125127127129129131131133133135135137137139139141141143143145145147147149149151151153153155155157157159159161161163163165165167167169169171171173173175175177177179179
122 122124 124126 126128 128130 130132 132134 134136 136138 138140 140142 142144 144146 146148 148150 150152 152154 154156 156158 158160 160162 162164 164166 166168 168170 170172 172174 174176 176178 178180 180
181 181182 182183 183184 184
185 185186 186187 187188 188
189189190190191191192192
C810uC810u
R29 100R29 100
R44 100R44 100
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HSTCC_RX_p0HSTCC_RX_n0
HSTCC_CLKIN_n1HSTCC_CLKIN_p1
HSTCC_CLKIN_n0HSTCC_CLKIN_p0
HSTCC_CLKOUT_n1HSTCC_CLKOUT_p1
HSTCC_CLKOUT_n0HSTCC_CLKOUT_p0
HSTCC_TX_n0HSTCC_TX_p0
HSTCC2_TDO
HSTCC2_TCK
HSTCC_PSNT_n
HSTCC2_TMS
HSTCC_EN
HSTCC2_TDI
HSTCC_RX_p0HSTCC_RX_n0HSTCC_TX_n0
HSTCC_TX_p0
HSTCC1_TDI
HSTCC1_TMS HSTCC1_TCK
HSTCC1_TDO
HSTCC_SDA HSTCC_SCL
HSTCC_PSNT_n
HSTCC_RX_p1HSTCC_RX_n1HSTCC_TX_n1
HSTCC_TX_p1HSTCC_RX_p1HSTCC_RX_n1 HSTCC_TX_n1
HSTCC_TX_p1
HSTCC_RX_p2HSTCC_RX_n2
HSTCC_TX_p2HSTCC_TX_n2HSTCC_TX_p2HSTCC_RX_p2
HSTCC_RX_n2 HSTCC_TX_n2
HSTCC_RX_p3HSTCC_RX_n3
HSTCC_TX_p3HSTCC_TX_n3HSTCC_TX_p3HSTCC_RX_p3
HSTCC_RX_n3 HSTCC_TX_n3
HSTCC_RX_p4HSTCC_RX_n4
HSTCC_TX_p4HSTCC_TX_n4HSTCC_TX_p4HSTCC_RX_p4
HSTCC_RX_n4 HSTCC_TX_n4
HSTCC_RX_p5HSTCC_RX_n5
HSTCC_TX_p5HSTCC_TX_n5HSTCC_TX_p5HSTCC_RX_p5
HSTCC_RX_n5 HSTCC_TX_n5
HSTCC_RX_p6HSTCC_RX_n6
HSTCC_TX_p6HSTCC_TX_n6HSTCC_TX_p6HSTCC_RX_p6
HSTCC_RX_n6 HSTCC_TX_n6
HSTCC_RX_p7HSTCC_RX_n7
HSTCC_TX_p7HSTCC_TX_n7HSTCC_TX_p7HSTCC_RX_p7
HSTCC_RX_n7 HSTCC_TX_n7
HSTCC_RX_p8HSTCC_RX_n8
HSTCC_TX_p8HSTCC_TX_n8HSTCC_TX_p8HSTCC_RX_p8
HSTCC_RX_n8 HSTCC_TX_n8
HSTCC_RX_p9HSTCC_RX_n9
HSTCC_TX_p9HSTCC_TX_n9HSTCC_TX_p9HSTCC_RX_p9
HSTCC_RX_n9 HSTCC_TX_n9
HSTCC_TX_p10 HSTCC_RX_p10HSTCC_RX_n10HSTCC_TX_n10
HSTCC_TX_p10HSTCC_RX_p10HSTCC_RX_n10 HSTCC_TX_n10
HSTCC_TX_p11 HSTCC_RX_p11HSTCC_RX_n11HSTCC_TX_n11
HSTCC_TX_p11HSTCC_RX_p11HSTCC_RX_n11 HSTCC_TX_n11
HSTCC_TX_p12 HSTCC_RX_p12HSTCC_RX_n12HSTCC_TX_n12
HSTCC_TX_p12HSTCC_RX_p12HSTCC_RX_n12 HSTCC_TX_n12
HSTCC_TX_p13 HSTCC_RX_p13HSTCC_RX_n13HSTCC_TX_n13
HSTCC_TX_p13HSTCC_RX_p13HSTCC_RX_n13 HSTCC_TX_n13
HSTCC_TX_p14 HSTCC_RX_p14HSTCC_RX_n14HSTCC_TX_n14
HSTCC_TX_p14HSTCC_RX_p14HSTCC_RX_n14 HSTCC_TX_n14
HSTCC_TX_p15 HSTCC_RX_p15HSTCC_RX_n15HSTCC_TX_n15
HSTCC_TX_p15HSTCC_RX_p15HSTCC_RX_n15 HSTCC_TX_n15
HSTCC_TX_p16 HSTCC_RX_p16HSTCC_RX_n16HSTCC_TX_n16
HSTCC_TX_p16HSTCC_RX_p16HSTCC_RX_n16 HSTCC_TX_n16
HSTCC_TX_p17 HSTCC_RX_p17HSTCC_RX_n17HSTCC_TX_n17
HSTCC_TX_p17HSTCC_RX_p17HSTCC_RX_n17 HSTCC_TX_n17
HSTCC_TX_p18 HSTCC_RX_p18HSTCC_RX_n18HSTCC_TX_n18
HSTCC_TX_p18HSTCC_RX_p18HSTCC_RX_n18 HSTCC_TX_n18
HSTCC_TX_p19 HSTCC_RX_p19HSTCC_RX_n19HSTCC_TX_n19
HSTCC_TX_p19HSTCC_RX_p19HSTCC_RX_n19 HSTCC_TX_n19
HSTCC_TX_p20 HSTCC_RX_p20HSTCC_RX_n20HSTCC_TX_n20
HSTCC_TX_p20HSTCC_RX_p20HSTCC_RX_n20 HSTCC_TX_n20
HSTCC_TX_p21 HSTCC_RX_p21HSTCC_RX_n21HSTCC_TX_n21
HSTCC_TX_p21HSTCC_RX_p21HSTCC_RX_n21 HSTCC_TX_n21
HSTCC_TX_p22 HSTCC_RX_p22HSTCC_RX_n22HSTCC_TX_n22
HSTCC_TX_p22HSTCC_RX_p22HSTCC_RX_n22 HSTCC_TX_n22
HSTCC_TX_p23 HSTCC_RX_p23HSTCC_RX_n23HSTCC_TX_n23
HSTCC_TX_p23HSTCC_RX_p23HSTCC_RX_n23 HSTCC_TX_n23
HSTCC_TX_p24 HSTCC_RX_p24HSTCC_RX_n24HSTCC_TX_n24
HSTCC_TX_p24HSTCC_RX_p24HSTCC_RX_n24 HSTCC_TX_n24
HSTCC_TX_p25 HSTCC_RX_p25HSTCC_RX_n25HSTCC_TX_n25
HSTCC_TX_p25HSTCC_RX_p25HSTCC_RX_n25 HSTCC_TX_n25
HSTCC_TX_p26 HSTCC_RX_p26HSTCC_RX_n26HSTCC_TX_n26
HSTCC_TX_p26HSTCC_RX_p26HSTCC_RX_n26 HSTCC_TX_n26
HSTCC_TX_p27 HSTCC_RX_p27HSTCC_RX_n27HSTCC_TX_n27
HSTCC_TX_p27HSTCC_RX_p27HSTCC_RX_n27 HSTCC_TX_n27
HSTCC_TX_p28 HSTCC_RX_p28HSTCC_RX_n28HSTCC_TX_n28
HSTCC_TX_p28HSTCC_RX_p28HSTCC_RX_n28 HSTCC_TX_n28
HSTCC_TX_p29 HSTCC_RX_p29HSTCC_RX_n29HSTCC_TX_n29
HSTCC_TX_p29HSTCC_RX_p29HSTCC_RX_n29 HSTCC_TX_n29
HSTCC_PSNT_n
HSTCC1_TDIHSTCC1_TMSHSTCC1_TCK
HSTCC1_TDO
HSTCC2_TDIHSTCC2_TDO
HSTCC2_TMSHSTCC2_TCK
POWER_ON
HSTCC_TX_p13HSTCC_TX_n13
HSTCC_TX_p14HSTCC_TX_n14
HSTCC_TX_p15HSTCC_TX_n15
HSTCC_TX_n9HSTCC_TX_p9
HSTCC_TX_p16HSTCC_TX_n16
HSTCC_TX_n10HSTCC_TX_p10
HSTCC_CLKOUT_n1HSTCC_CLKOUT_p1
HSTCC_TX_p17HSTCC_TX_n17
HSTCC_TX_p11HSTCC_TX_n11
HSTCC_TX_p12HSTCC_TX_n12
HSTCC_TX_p27HSTCC_TX_n27
HSTCC_TX_p22HSTCC_TX_n22
HSTCC_TX_p28HSTCC_TX_n28
HSTCC_TX_p23HSTCC_TX_n23
HSTCC_TX_p18HSTCC_TX_n18
HSTCC_TX_p29HSTCC_TX_n29
HSTCC_TX_p24HSTCC_TX_n24
HSTCC_TX_p19HSTCC_TX_n19
HSTCC_TX_p25HSTCC_TX_n25
HSTCC_TX_p20HSTCC_TX_n20
HSTCC_TX_p26HSTCC_TX_n26
HSTCC_TX_p21HSTCC_TX_n21
HSTCC_CLKIN_n1HSTCC_CLKIN_p1
HSTCC_CLKOUT_2
HSTCC_CLKOUT_n1HSTCC_CLKOUT_p1
HSTCC_CLKOUT_n0HSTCC_CLKOUT_p0
HSTCC_CLKIN_n0HSTCC_CLKIN_p0
HSTCC_CLKIN_n1HSTCC_CLKIN_p1
HSTCC_CLKIN_2
HSTCC_TX_p[0..29]HSTCC_TX_n[0..29]HSTCC_RX_p[0..29]HSTCC_RX_n[0..29]
HSTCC_SDA
HSTCC_CLKIN_p[0..1]HSTCC_CLKIN_n[0..1]
HSTCC_SCL
HSTCC_TDO
HSTCC_CLKOUT_p[0..1]HSTCC_CLKOUT_n[0..1]
HSTCC_TMSHSTCC_TDI
HSTCC_TCK
POWER_ON
HSTCC_EN
HSTCC_CLKIN_2 HSTCC_CLKOUT_2
VCC33
12V VCC33 VCC33 12V
VCC50
BC_VREF
VCC50
BC_VREF BC_VTTBC_VTT
VCC3312V
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
High Speed Terasic Connector C Top and Bottom 1.1
DE3 Base BoardC
6 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
High Speed Terasic Connector C Top and Bottom 1.1
DE3 Base BoardC
6 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
High Speed Terasic Connector C Top and Bottom 1.1
DE3 Base BoardC
6 32Thursday, September 04, 2008
HSTC Connector C-Top HSTC Connector C-Bottom
C1710uC1710u
R68 100R68 100
R53 100R53 100
R69 100R69 100
R51 100R51 100
R60 100R60 100
R55 100R55 100
R58 100R58 100
C1510uC1510u
R49 100R49 100
R61 100R61 100
JTAG_C
JTAG Controller
HSTC1_TDI
HSTC2_TDI
HSTC1_TMS
HSTC_TDO
HSTC2_TMS
HSTC1_TCK
HSTC2_TCK
HSTC_PSNT_nHSTC_EN
HSTC1_TDO
HSTC2_TDO
HSTC_TDIHSTC_TMSHSTC_TCK
R71 100R71 100
C1610uC1610u
C1410uC1410u
C1810uC1810u
R70 100R70 100
R72
120
R72
120
R52 100R52 100
181
182
183
184
188
185
186
187
192
189
190
191
J5
QTH-090
181
182
183
184
188
185
186
187
192
189
190
191
J5
QTH-090
185185
181181
186186
182182
187187
183183
188188
184184
1 13 35 57 79 9
11 1113 1315 1517 1719 1921 2123 2325 2527 2729 2931 3133 3335 3537 3739 3941 4143 4345 4547 4749 4951 5153 5355 5557 5759 59
2244668810101212141416161818202022222424262628283030323234343636383840404242444446464848505052525454565658586060
61 6163 6365 6567 6769 6971 7173 7375 7577 7779 7981 8183 8385 8587 8789 8991 9193 9395 9597 9799 99
101 101103 103105 105107 107109 109111 111113 113115 115117 117119 119
6262646466666868707072727474767678788080828284848686888890909292949496969898100100102102104104106106108108110110112112114114116116118118120120
122122124124126126128128130130132132134134136136138138140140142142144144146146148148150150152152154154156156158158160160162162164164166166168168170170172172174174176176178178180180
121 121123 123125 125127 127129 129131 131133 133135 135137 137139 139141 141143 143145 145147 147149 149151 151153 153155 155157 157159 159161 161163 163165 165167 167169 169171 171173 173175 175177 177179 179
189 189190 190191 191192 192
R54 100R54 100
LINKC
LEDR
LINKC
LEDR
R66 100R66 100
R67 100R67 100
R56 100R56 100
R63 100R63 100
R50 100R50 100
R62 100R62 100
C1310uC1310u
R59 100R59 100
R57 100R57 100
R64 100R64 100
181
182
183
184
188
185
186
187
189
192
190
191
J6
QSH-090
181
182
183
184
188
185
186
187
189
192
190
191
J6
QSH-090
11335577991111131315151717191921212323252527272929313133333535373739394141434345454747494951515353555557575959
2 24 46 68 8
10 1012 1214 1416 1618 1820 2022 2224 2426 2628 2830 3032 3234 3436 3638 3840 4042 4244 4446 4648 4850 5052 5254 5456 5658 5860 60
61616363656567676969717173737575777779798181838385858787898991919393959597979999101101103103105105107107109109111111113113115115117117119119
62 6264 6466 6668 6870 7072 7274 7476 7678 7880 8082 8284 8486 8688 8890 9092 9294 9496 9698 98
100 100102 102104 104106 106108 108110 110112 112114 114116 116118 118120 120
121121123123125125127127129129131131133133135135137137139139141141143143145145147147149149151151153153155155157157159159161161163163165165167167169169171171173173175175177177179179
122 122124 124126 126128 128130 130132 132134 134136 136138 138140 140142 142144 144146 146148 148150 150152 152154 154156 156158 158160 160162 162164 164166 166168 168170 170172 172174 174176 176178 178180 180
181 181182 182183 183184 184
185 185186 186187 187188 188
189189190190191191192192
R65 100R65 100
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HSTCD_RX_p0HSTCD_RX_n0
HSTCD_CLKIN_n1HSTCD_CLKIN_p1
HSTCD_CLKIN_n0HSTCD_CLKIN_p0
HSTCD_CLKOUT_n1HSTCD_CLKOUT_p1
HSTCD_CLKOUT_n0HSTCD_CLKOUT_p0
HSTCD_TX_n0HSTCD_TX_p0
HSTCD2_TDO
HSTCD2_TCK
HSTCD_PSNT_n
HSTCD2_TMS
HSTCD_EN
HSTCD2_TDI
HSTCD_RX_p0HSTCD_RX_n0HSTCD_TX_n0
HSTCD_TX_p0
HSTCD1_TDI
HSTCD1_TMS HSTCD1_TCK
HSTCD1_TDO
HSTCD_SDA HSTCD_SCL
HSTCD_PSNT_n
HSTCD_RX_p1HSTCD_RX_n1HSTCD_TX_n1
HSTCD_TX_p1HSTCD_RX_p1HSTCD_RX_n1 HSTCD_TX_n1
HSTCD_TX_p1
HSTCD_RX_p2HSTCD_RX_n2HSTCD_TX_n2
HSTCD_TX_p2HSTCD_RX_p2HSTCD_RX_n2 HSTCD_TX_n2
HSTCD_TX_p2
HSTCD_RX_p3HSTCD_RX_n3HSTCD_TX_n3
HSTCD_TX_p3HSTCD_RX_p3HSTCD_RX_n3 HSTCD_TX_n3
HSTCD_TX_p3
HSTCD_RX_p4HSTCD_RX_n4HSTCD_TX_n4
HSTCD_TX_p4HSTCD_RX_p4HSTCD_RX_n4 HSTCD_TX_n4
HSTCD_TX_p4
HSTCD_RX_p5HSTCD_RX_n5HSTCD_TX_n5
HSTCD_TX_p5HSTCD_RX_p5HSTCD_RX_n5 HSTCD_TX_n5
HSTCD_TX_p5
HSTCD_RX_p6HSTCD_RX_n6HSTCD_TX_n6
HSTCD_TX_p6HSTCD_RX_p6HSTCD_RX_n6 HSTCD_TX_n6
HSTCD_TX_p6
HSTCD_RX_p7HSTCD_RX_n7HSTCD_TX_n7
HSTCD_TX_p7HSTCD_RX_p7HSTCD_RX_n7 HSTCD_TX_n7
HSTCD_TX_p7
HSTCD_RX_n8HSTCD_RX_p8
HSTCD_TX_n8HSTCD_TX_p8HSTCD_RX_p8
HSTCD_RX_n8HSTCD_TX_p8HSTCD_TX_n8
HSTCD_RX_n9HSTCD_RX_p9
HSTCD_TX_n9HSTCD_TX_p9HSTCD_RX_p9
HSTCD_RX_n9HSTCD_TX_p9HSTCD_TX_n9
HSTCD_RX_n10HSTCD_RX_p10
HSTCD_TX_n10HSTCD_TX_p10HSTCD_RX_p10
HSTCD_RX_n10HSTCD_TX_p10HSTCD_TX_n10
HSTCD_RX_n11HSTCD_RX_p11
HSTCD_TX_n11HSTCD_TX_p11HSTCD_RX_p11
HSTCD_RX_n11HSTCD_TX_p11HSTCD_TX_n11
HSTCD_RX_n12HSTCD_RX_p12
HSTCD_TX_n12HSTCD_TX_p12HSTCD_RX_p12
HSTCD_RX_n12HSTCD_TX_p12HSTCD_TX_n12
HSTCD_RX_n13HSTCD_RX_p13
HSTCD_TX_n13HSTCD_TX_p13HSTCD_RX_p13
HSTCD_RX_n13HSTCD_TX_p13HSTCD_TX_n13
HSTCD_RX_n14HSTCD_RX_p14
HSTCD_TX_n14HSTCD_TX_p14HSTCD_RX_p14
HSTCD_RX_n14HSTCD_TX_p14HSTCD_TX_n14
HSTCD_RX_n15HSTCD_RX_p15
HSTCD_TX_n15HSTCD_TX_p15HSTCD_RX_p15
HSTCD_RX_n15HSTCD_TX_p15HSTCD_TX_n15
HSTCD_RX_n16HSTCD_RX_p16
HSTCD_TX_n16HSTCD_TX_p16HSTCD_RX_p16
HSTCD_RX_n16HSTCD_TX_p16HSTCD_TX_n16
HSTCD_RX_n17HSTCD_RX_p17
HSTCD_TX_n17HSTCD_TX_p17HSTCD_RX_p17
HSTCD_RX_n17HSTCD_TX_p17HSTCD_TX_n17
HSTCD_RX_n18HSTCD_RX_p18
HSTCD_TX_n18HSTCD_TX_p18HSTCD_RX_p18
HSTCD_RX_n18HSTCD_TX_p18HSTCD_TX_n18
HSTCD_RX_n19HSTCD_RX_p19
HSTCD_TX_n19HSTCD_TX_p19HSTCD_RX_p19
HSTCD_RX_n19HSTCD_TX_p19HSTCD_TX_n19
HSTCD_RX_n20HSTCD_RX_p20
HSTCD_TX_n20HSTCD_TX_p20HSTCD_RX_p20
HSTCD_RX_n20HSTCD_TX_p20HSTCD_TX_n20
HSTCD_RX_n21HSTCD_RX_p21
HSTCD_TX_n21HSTCD_TX_p21HSTCD_RX_p21
HSTCD_RX_n21HSTCD_TX_p21HSTCD_TX_n21
HSTCD_RX_n22HSTCD_RX_p22
HSTCD_TX_n22HSTCD_TX_p22HSTCD_RX_p22
HSTCD_RX_n22HSTCD_TX_p22HSTCD_TX_n22
HSTCD_RX_n23HSTCD_RX_p23
HSTCD_TX_n23HSTCD_TX_p23HSTCD_RX_p23
HSTCD_RX_n23HSTCD_TX_p23HSTCD_TX_n23
HSTCD_RX_n24HSTCD_RX_p24
HSTCD_TX_n24HSTCD_TX_p24HSTCD_RX_p24
HSTCD_RX_n24HSTCD_TX_p24HSTCD_TX_n24
HSTCD_RX_n25HSTCD_RX_p25
HSTCD_TX_n25HSTCD_TX_p25HSTCD_RX_p25
HSTCD_RX_n25HSTCD_TX_p25HSTCD_TX_n25
HSTCD_RX_n26HSTCD_RX_p26
HSTCD_TX_n26HSTCD_TX_p26HSTCD_RX_p26
HSTCD_RX_n26HSTCD_TX_p26HSTCD_TX_n26
HSTCD_RX_n27HSTCD_RX_p27
HSTCD_TX_n27HSTCD_TX_p27HSTCD_RX_p27
HSTCD_RX_n27HSTCD_TX_p27HSTCD_TX_n27
HSTCD_RX_n28HSTCD_RX_p28
HSTCD_TX_n28HSTCD_TX_p28HSTCD_RX_p28
HSTCD_RX_n28HSTCD_TX_p28HSTCD_TX_n28
HSTCD_RX_n29HSTCD_RX_p29
HSTCD_TX_n29HSTCD_TX_p29HSTCD_RX_p29
HSTCD_RX_n29HSTCD_TX_p29HSTCD_TX_n29
HSTCD_PSNT_n
HSTCD1_TDIHSTCD1_TMSHSTCD1_TCK
HSTCD1_TDO
HSTCD2_TDIHSTCD2_TDO
HSTCD2_TMSHSTCD2_TCK
POWER_ON
HSTCD_TX_n11HSTCD_TX_p11
HSTCD_TX_n12HSTCD_TX_p12
HSTCD_TX_p17HSTCD_TX_n17
HSTCD_TX_n9HSTCD_TX_p9
HSTCD_TX_n13HSTCD_TX_p13
HSTCD_CLKOUT_n1HSTCD_CLKOUT_p1
HSTCD_TX_n14HSTCD_TX_p14
HSTCD_TX_n15HSTCD_TX_p15
HSTCD_TX_n16HSTCD_TX_p16
HSTCD_TX_n10HSTCD_TX_p10
HSTCD_TX_p28HSTCD_TX_n28
HSTCD_TX_p23HSTCD_TX_n23
HSTCD_TX_n18HSTCD_TX_p18
HSTCD_TX_p29HSTCD_TX_n29
HSTCD_TX_p24HSTCD_TX_n24
HSTCD_TX_p19HSTCD_TX_n19
HSTCD_TX_p25HSTCD_TX_n25
HSTCD_TX_p20HSTCD_TX_n20
HSTCD_TX_p26HSTCD_TX_n26
HSTCD_TX_p21HSTCD_TX_n21
HSTCD_TX_p27HSTCD_TX_n27
HSTCD_TX_p22HSTCD_TX_n22
HSTCD_CLKIN_n1HSTCD_CLKIN_p1
HSTCD_CLKOUT_2
HSTCD_CLKOUT_n1HSTCD_CLKOUT_p1
HSTCD_CLKOUT_n0HSTCD_CLKOUT_p0
HSTCD_CLKIN_n0HSTCD_CLKIN_p0
HSTCD_CLKIN_n1HSTCD_CLKIN_p1
HSTCD_CLKIN_2
HSTCD_TX_p[0..29]HSTCD_TX_n[0..29]HSTCD_RX_p[0..29]HSTCD_RX_n[0..29]
HSTCD_SDA
HSTCD_CLKIN_p[0..1]HSTCD_CLKIN_n[0..1]
HSTCD_SCL
HSTCD_TDO
HSTCD_CLKOUT_p[0..1]HSTCD_CLKOUT_n[0..1]
HSTCD_TMSHSTCD_TDI
HSTCD_TCK
POWER_ON
HSTCD_EN
HSTCD_CLKIN_2 HSTCD_CLKOUT_2VCC33
12V VCC33 VCC33 12V
VCC50
BD_VREF
VCC50
BD_VREF BD_VTTBD_VTT
VCC3312V
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
High Speed Terasic Connector D Top and Bottom 1.1
DE3 Base BoardC
7 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
High Speed Terasic Connector D Top and Bottom 1.1
DE3 Base BoardC
7 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
High Speed Terasic Connector D Top and Bottom 1.1
DE3 Base BoardC
7 32Thursday, September 04, 2008
HSTC Connector D-Top HSTC Connector D-Bottom
C2110uC2110u
R75 100R75 100
R74 100R74 100
C2310uC2310u
R86 100R86 100
R94 100R94 100
R85 100R85 100
R92 100R92 100
R90 100R90 100
R83 100R83 100
R80 100R80 100
181
182
183
184
188
185
186
187
189
192
190
191
J8
QSH-090
181
182
183
184
188
185
186
187
189
192
190
191
J8
QSH-090
11335577991111131315151717191921212323252527272929313133333535373739394141434345454747494951515353555557575959
2 24 46 68 8
10 1012 1214 1416 1618 1820 2022 2224 2426 2628 2830 3032 3234 3436 3638 3840 4042 4244 4446 4648 4850 5052 5254 5456 5658 5860 60
61616363656567676969717173737575777779798181838385858787898991919393959597979999101101103103105105107107109109111111113113115115117117119119
62 6264 6466 6668 6870 7072 7274 7476 7678 7880 8082 8284 8486 8688 8890 9092 9294 9496 9698 98
100 100102 102104 104106 106108 108110 110112 112114 114116 116118 118120 120
121121123123125125127127129129131131133133135135137137139139141141143143145145147147149149151151153153155155157157159159161161163163165165167167169169171171173173175175177177179179
122 122124 124126 126128 128130 130132 132134 134136 136138 138140 140142 142144 144146 146148 148150 150152 152154 154156 156158 158160 160162 162164 164166 166168 168170 170172 172174 174176 176178 178180 180
181 181182 182183 183184 184
185 185186 186187 187188 188
189189190190191191192192
JTAG_D
JTAG Controller
HSTC1_TDI
HSTC2_TDI
HSTC1_TMS
HSTC_TDO
HSTC2_TMS
HSTC1_TCK
HSTC2_TCK
HSTC_PSNT_nHSTC_EN
HSTC1_TDO
HSTC2_TDO
HSTC_TDIHSTC_TMSHSTC_TCK
R89 100R89 100
C2010uC2010u
R76 100R76 100
R77 100R77 100
181
182
183
184
188
185
186
187
192
189
190
191
J7
QTH-090
181
182
183
184
188
185
186
187
192
189
190
191
J7
QTH-090
185185
181181
186186
182182
187187
183183
188188
184184
1 13 35 57 79 9
11 1113 1315 1517 1719 1921 2123 2325 2527 2729 2931 3133 3335 3537 3739 3941 4143 4345 4547 4749 4951 5153 5355 5557 5759 59
2244668810101212141416161818202022222424262628283030323234343636383840404242444446464848505052525454565658586060
61 6163 6365 6567 6769 6971 7173 7375 7577 7779 7981 8183 8385 8587 8789 8991 9193 9395 9597 9799 99
101 101103 103105 105107 107109 109111 111113 113115 115117 117119 119
6262646466666868707072727474767678788080828284848686888890909292949496969898100100102102104104106106108108110110112112114114116116118118120120
122122124124126126128128130130132132134134136136138138140140142142144144146146148148150150152152154154156156158158160160162162164164166166168168170170172172174174176176178178180180
121 121123 123125 125127 127129 129131 131133 133135 135137 137139 139141 141143 143145 145147 147149 149151 151153 153155 155157 157159 159161 161163 163165 165167 167169 169171 171173 173175 175177 177179 179
189 189190 190191 191192 192
R73 100R73 100
C2210uC2210u
R88 100R88 100
R87 100R87 100
C2410uC2410u
R84 100R84 100
R96
120
R96
120
R81 100R81 100
R82 100R82 100
R93 100R93 100
R95 100R95 100
C1910uC1910u
R79 100R79 100
R91 100R91 100
LINKD
LEDR
LINKD
LEDR
R78 100R78 100
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR2_DQ13
DDR2_DQ14
DDR2_DM0
DDR2_DQ4
DDR2_DQ15
DDR2_DQ5
DDR2_DQ6DDR2_DQ7
DDR2_DM1
DDR2_DQ12
DDR2_CLK_n0DDR2_CLK_p0
DDR2_A11
DDR2_DQ23
DDR2_A4
DDR2_DQS_p3DDR2_DQS_n3
DDR2_A14DDR2_A15
DDR2_A6
DDR2_DQ28
DDR2_CKE1
DDR2_A0
DDR2_DQ29
DDR2_DM2
DDR2_A7
DDR2_DQ30
DDR2_DQ20
DDR2_DQ31
DDR2_DQ21
DDR2_A2
DDR2_DQ22
DDR2_CS_n0
DDR2_A13
DDR2_BA1
DDR2_ODT0
DDR2_DM4
DDR2_DQ60
DDR2_DQS_p7DDR2_DQS_n7
DDR2_DQ52
DDR2_DQ61
DDR2_DQ44
DDR2_CLK_n1
DDR2_DQ53
DDR2_DQ62
DDR2_DM6
DDR2_DQ36
DDR2_DQ45
DDR2_DQ54
DDR2_DQ63
DDR2_CLK_p1
DDR2_DQ46
DDR2_DQ37
DDR2_DQ55
DDR2_DQ47
DDR2_DQ38
DDR2_DQS_p5DDR2_DQS_n5
DDR2_DQ39
DDR2_DQ2DDR2_DQ3
DDR2_DQS_n0
DDR2_DQ8
DDR2_DQ0
DDR2_DQ9
DDR2_DQS_n1DDR2_DQS_p1
DDR2_DQ10DDR2_DQ11
DDR2_DQ1
DDR2_DQS_p0
DDR2_DQ24DDR2_DQ25
DDR2_DQ16DDR2_DQ17
DDR2_DQ18DDR2_DQ19
DDR2_DM3
DDR2_DQS_n2DDR2_DQS_p2
DDR2_BA2
DDR2_CKE0
DDR2_DQ26DDR2_DQ27
DDR2_BA0
DDR2_A12
DDR2_A5
DDR2_A8
DDR2_A1
DDR2_A9
DDR2_A3
DDR2_A10
DDR2_DQ40
DDR2_DQ49
DDR2_DQ32
DDR2_DQ41
DDR2_DQ34
DDR2_DQ42
DDR2_DQ33
DDR2_DM5
DDR2_DQ43
DDR2_DQ35
DDR2_DQS_n4DDR2_DQS_p4
DDR2_ODT1
DDR2_DQ48
DDR2_CS_n1
DDR2_DQ58
DDR2_DQS_p6DDR2_DQS_n6
DDR2_DQ50
DDR2_DQ59
DDR2_DQ51
DDR2_DM7
DDR2_DQ56DDR2_DQ57
BB_VREF
BB_VREF
BB_VCCIOBB_VCCIO
BB_VCCIOBB_VCCIO
BB_VCCIO BB_VCCIO
VCC33
DDR2_DQS_n[0..7]
DDR2_DQ[0..63]
DDR2_DQS_p[0..7]
DDR2_BA[0..2]
DDR2_CS_n[0..1]
DDR2_CAS_n
DDR2_WE_n
DDR2_A[0..15]
DDR2_DM[0..7]
DDR2_ODT[0..1]
DDR2_CLK_p[0..1]
DDR2_CKE[0..1]
DDR2_CLK_n[0..1]
DDR2_SCLDDR2_SDA
DDR2_RAS_n
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
DDR2 SO-DIMM 1.1
DE3 Base Board
32Thursday, September 04, 2008 8
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
DDR2 SO-DIMM 1.1
DE3 Base Board
32Thursday, September 04, 2008 8
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
DDR2 SO-DIMM 1.1
DE3 Base Board
32Thursday, September 04, 2008 8
BC4
0.1u
BC4
0.1u
SOCKET-SO-DIMM200
J9
SOCKET-SO-DIMM200
J9
VREF1VSS3DQ05DQ17VSS9DQS011DQS013VSS15DQ217DQ319VSS21DQ823DQ925VSS27DQS129DQS131VSS33DQ1035DQ1137VSS39
VSS41DQ1643DQ1745VSS47DQS249DQS251VSS53DQ1855DQ1957VSS59DQ2461DQ2563VSS65DM367NC169VSS71DQ2673DQ2775VSS77CKE079VDD81NC283BA285VDD87A1289A991A893VDD95A597A399A1101VDD103A10/AP105BA0107WE109VDD111CAS113S1115VDD117ODT1119VSS121DQ32123DQ33125VSS127DQS4129DQS4131VSS133DQ34135DQ35137VSS139DQ40141DQ41143VSS145DM5147VSS149DQ42151DQ43153VSS155DQ48157DQ49159VSS161TEST163VSS165DQS6167DQS6169VSS171DQ50173DQ51175VSS177DQ56179DQ57181VSS183DM7185VSS187DQ58189DQ59191VSS193SDA195SCL197VDDSPD199
VSS 2DQ4 4DQ5 6VSS 8DM0 10VSS 12DQ6 14DQ7 16VSS 18
DQ12 20DQ13 22
VSS 24DM1 26VSS 28CK0 30CK0 32VSS 34
DQ14 36DQ15 38
VSS 40
VSS 42DQ20 44DQ21 46
VSS 48NC0 50DM2 52VSS 54
DQ22 56DQ23 58
VSS 60DQ28 62DQ29 64
VSS 66DQS3 68DQS3 70
VSS 72DQ30 74DQ31 76
VSS 78CKE1 80VDD 82A15 84A14 86
VDD 88A11 90
A7 92A6 94
VDD 96A4 98A2 100A0 102
VDD 104BA1 106RAS 108
S0 110VDD 112
ODT0 114A13 116
VDD 118NC3 120VSS 122
DQ36 124DQ37 126
VSS 128DM4 130VSS 132
DQ38 134DQ39 136
VSS 138DQ44 140DQ45 142
VSS 144DQS5 146DQS5 148
VSS 150DQ46 152DQ47 154
VSS 156DQ52 158DQ53 160
VSS 162CK1 164CK1 166VSS 168DM6 170VSS 172
DQ54 174DQ55 176
VSS 178DQ60 180DQ61 182
VSS 184DQS7 186DQS7 188
VSS 190DQ62 192DQ63 194
VSS 196SA0 198SA1 200
BC12
0.1u
BC12
0.1u
BC8
0.1u
BC8
0.1u
BC6
0.1u
BC6
0.1u
BC7
0.1u
BC7
0.1u
BC10
0.1u
BC10
0.1u
C26
100u
C26
100u
BC13
0.1u
BC13
0.1u
BC5
0.1u
BC5
0.1u
BC1
0.1u
BC1
0.1u
BC11
0.1u
BC11
0.1u
C25
100u
C25
100u
BC9
0.1u
BC9
0.1u
BC3
0.1u
BC3
0.1u
BC2
0.1u
BC2
0.1u
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HSTCB_RX_p10HSTCB_RX_n10
HSTCB_TX_n21HSTCB_TX_p21
HSTCB_RX_p23HSTCB_RX_n23
HSTCB_RX_p16HSTCB_RX_n16
HSTCB_TX_n14HSTCB_TX_p14
HSTCB_RX_p5HSTCB_RX_n5
HSTCB_TX_n6HSTCB_TX_p6
HSTCB_RX_n0HSTCB_RX_p0
HSTCB_TX_n22
HSTCB_RX_p17HSTCB_RX_n17
HSTCB_TX_n15HSTCB_TX_p15
HSTCB_RX_p11HSTCB_RX_n11
HSTCB_TX_n7
HSTCB_TX_n0HSTCB_TX_p0
HSTCB_RX_p6HSTCB_RX_n6
HSTCB_TX_n16
HSTCB_RX_p18HSTCB_RX_n18
HSTCB_RX_n1HSTCB_RX_p1
HSTCB_TX_n8HSTCB_TX_p8
HSTCB_RX_p12HSTCB_RX_n12
HSTCB_TX_n23HSTCB_TX_p23
HSTCB_TX_n1
HSTCB_TX_n17HSTCB_TX_p17
HSTCB_TX_n9
HSTCB_RX_p19HSTCB_RX_n19
HSTCB_TX_p9
HSTCB_RX_n2HSTCB_RX_p2
HSTCB_RX_p7HSTCB_RX_n7
HSTCB_RX_p13HSTCB_RX_n13
HSTCB_TX_n18HSTCB_TX_p18
HSTCB_TX_n2HSTCB_TX_p2
HSTCB_TX_n10
HSTCB_RX_p20HSTCB_RX_n20
HSTCB_RX_p8HSTCB_RX_n8
HSTCB_RX_p14HSTCB_RX_n14
HSTCB_TX_n19
HSTCB_RX_n3HSTCB_RX_p3
HSTCB_TX_n3HSTCB_TX_p3
HSTCB_TX_n11HSTCB_TX_p11
HSTCB_RX_p21HSTCB_RX_n21
HSTCB_TX_n20HSTCB_TX_p20
HSTCB_TX_n12HSTCB_TX_p12
HSTCB_TX_n4
HSTCB_RX_p9HSTCB_RX_n9
HSTCB_RX_p15HSTCB_RX_n15
HSTCB_RX_p22HSTCB_RX_n22
HSTCB_RX_p4HSTCB_RX_n4
HSTCB_TX_n13
HSTCB_TX_n5HSTCB_TX_p5
HSTCB_TX_p22
HSTCB_TX_p7
HSTCB_TX_p16
HSTCB_TX_n27
HSTCB_TX_n28
HSTCB_TX_n29
HSTCB_TX_n24
HSTCB_TX_n25
HSTCB_TX_n26
HSTCB_TX_p27
HSTCB_TX_p28
HSTCB_TX_p29
HSTCB_TX_p24
HSTCB_TX_p25
HSTCB_TX_p26
HSTCB_TX_p10
HSTCB_TX_p1HSTCB_TX_p4
HSTCB_TX_p19
HSTCB_RX_p27
HSTCB_RX_p28
HSTCB_RX_p29
HSTCB_RX_p24
HSTCB_RX_p25
HSTCB_RX_p26
HSTCB_RX_n27
HSTCB_RX_n28
HSTCB_RX_n29
HSTCB_RX_n24
HSTCB_RX_n25
HSTCB_RX_n26
HSTCB_TX_p13
HSTCB_TX_p[0..29]HSTCB_TX_n[0..29]HSTCB_RX_p[0..29]HSTCB_RX_n[0..29]
HSTCB_SDAHSTCB_SCL
DDR2_DQS_p4DDR2_DQS_n4
DDR2_DQS_n5DDR2_DQS_p5
DDR2_DQS_p6DDR2_DQS_n6
DDR2_DQS_p7DDR2_DQS_n7
DDR2_DQ32
DDR2_DQ40
DDR2_DQ56
DDR2_DQ48
DDR2_DQ33
DDR2_DQ49
DDR2_DQ57
DDR2_DQ41
DDR2_DQ34
DDR2_DQ42
DDR2_DQ58
DDR2_DQ50
DDR2_DQ59
DDR2_DQ43
DDR2_DQ35
DDR2_DQ51
DDR2_DQ60
DDR2_DQ36
DDR2_DQ44
DDR2_DQ52
DDR2_DQ37
DDR2_DQ61
DDR2_DQ53
DDR2_DQ45
DDR2_DQ62
DDR2_DQ38
DDR2_DQ46
DDR2_DQ54
DDR2_DQ39
DDR2_DQ63
DDR2_DQ55
DDR2_DQ47
DDR2_DM4
DDR2_DM5
DDR2_DM6
DDR2_DM7
DDR2_DQ0
DDR2_DQS_p0DDR2_DQS_n0
DDR2_DQ1DDR2_DQ2DDR2_DQ3DDR2_DQ4DDR2_DQ5DDR2_DQ6DDR2_DQ7
DDR2_DM0
DDR2_DQS_n1DDR2_DQS_p1
DDR2_DQ8DDR2_DQ9DDR2_DQ10DDR2_DQ11DDR2_DQ12DDR2_DQ13DDR2_DQ14DDR2_DQ15
DDR2_DM1
DDR2_DQS_p2DDR2_DQS_n2
DDR2_DQ16DDR2_DQ17DDR2_DQ18DDR2_DQ19DDR2_DQ20DDR2_DQ21DDR2_DQ22DDR2_DQ23
DDR2_DM2
DDR2_DQS_n3DDR2_DQS_p3
DDR2_DQ24DDR2_DQ25DDR2_DQ26DDR2_DQ27DDR2_DQ28DDR2_DQ29DDR2_DQ30DDR2_DQ31
DDR2_DM3
DDR2_CLK_p0DDR2_CLK_n0
DDR2_ODT0
DDR2_CKE0
DDR2_CS_n0
DDR2_RAS_nDDR2_CAS_nDDR2_WE_n
DDR2_CS_n1
DDR2_CKE1
DDR2_ODT1
DDR2_CLK_p1DDR2_CLK_n1
DDR2_A0DDR2_A1DDR2_A2DDR2_A3DDR2_A4DDR2_A5DDR2_A6DDR2_A7DDR2_A8DDR2_A9DDR2_A10DDR2_A11DDR2_A12DDR2_A13
DDR2_A15DDR2_A14
DDR2_BA0DDR2_BA1DDR2_BA2
DDR2_SDADDR2_SCL
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
HSTC B to DDR2 SO-DIMM 1.1
DE3 Base Board
32Thursday, September 04, 2008 9
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
HSTC B to DDR2 SO-DIMM 1.1
DE3 Base Board
32Thursday, September 04, 2008 9
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
HSTC B to DDR2 SO-DIMM 1.1
DE3 Base Board
32Thursday, September 04, 2008 9
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
50M_OSC
EXT_CLK
OSC1_50
OSC_BAOSC_BBOSC_BCOSC_BD
OSC2_50
CLK_OUT VCC33
VCC33
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Onboard OSC and EXTERNAL CLOCK 1.1
DE3 Base BoardA
10 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Onboard OSC and EXTERNAL CLOCK 1.1
DE3 Base BoardA
10 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Onboard OSC and EXTERNAL CLOCK 1.1
DE3 Base BoardA
10 32Thursday, September 04, 2008
BC14
0.1u
BC14
0.1u
C27
1u
C27
1u
Y1
50MHZ
Y1
50MHZ
VCC 4
OUT 3GND2
EN1
R9749.9R9749.9
High-Speed Clock Buffer
Clock Buffer
OSC_BDBuffer_IN
OSC_BAOSC_BBOSC_BC
OSC2_50OSC1_50
J10
EXT_CLKIN
J10
EXT_CLKIN
R98DNIR98DNI
J11
PLL_CLKOUT
J11
PLL_CLKOUT
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DR6
DG6
DB6
DR7
DB7
DG7
DR1
DG1
DB1
DB2
DG2
DR2
DR0
DR3
DG3
DB3
DG0
DR4
DB4
DG4
DB0
DR5
DB5
DG5
LEDR3
LEDG3
LEDG0LEDB0
LEDG4LEDB4
LEDR4LEDB5
LEDR5
LEDG6
LEDR6LEDB6
LEDG7
LEDR7LEDB7
LEDR1
LEDG5
LEDG1
LEDB1
LEDG2
LEDR2
LEDB2
LEDB3
LEDR0
DR6
DG6
DB7
DR4
DB4DG4
DR5
DB5
DG5
DR7
DG7
DR1DG1
DB1
DB2DG2
DR2
DR0
DB3
DG0DB0
DG3
DR3
DB6
HEX0_D3HEX0_D4HEX0_D6HEX0_D5
HEX1_D2HEX1_D1HEX1_D0
HEX0_D2HEX0_D1HEX0_D0
HEX1_D5
HEX1_D4HEX1_D3
HEX1_D6
A0B0C0D0
DP0G0F0E0
B1A1
D1C1
E1F1G1DP1
A1B1C1
A0B0C0
DP1
G1F1
D1E1
D0
DP0
G0F0
E0
HEX0_D[0..6]
HEX1_D[0..6]
LEDR[0..7]
LEDG[0..7]
LEDB[0..7]
HEX0_DP
HEX1_DPVCC33
VCC33
VCC33
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Color LED and 7-Segment 1.1
DE3 Base BoardA
11 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Color LED and 7-Segment 1.1
DE3 Base BoardA
11 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Color LED and 7-Segment 1.1
DE3 Base BoardA
11 32Thursday, September 04, 2008
RN1 120RN1 12012345
678
RN4 120RN4 12012345
678
ed
dp
c
g
b
f
a
CA1
CA2
HEX1
7Segment Display
ed
dp
c
g
b
f
a
CA1
CA2
HEX1
7Segment Display
1
23
45
6
1098
7
R
G
B
LED1
LED-RGB
R
G
B
LED1
LED-RGB
R
G
B
LED2
LED-RGB
R
G
B
LED2
LED-RGB
RN7 1KRN7 1K
12345
678
R
G
B
LED0
LED-RGB
R
G
B
LED0
LED-RGB
R
G
B
LED6
LED-RGB
R
G
B
LED6
LED-RGB
ed
dp
c
g
b
f
a
CA1
CA2
HEX0
7Segment Display
ed
dp
c
g
b
f
a
CA1
CA2
HEX0
7Segment Display
1
23
45
6
1098
7
RN9 1KRN9 1K
12345
678
RN5 120RN5 12012345
678
RN6 120RN6 12012345
678
RN3 120RN3 12012345
678
RN10 1KRN10 1K
12345
678
R
G
B
LED7
LED-RGB
R
G
B
LED7
LED-RGB
R
G
B
LED3
LED-RGB
R
G
B
LED3
LED-RGB
R
G
B
LED4
LED-RGB
R
G
B
LED4
LED-RGB
RN2 120RN2 12012345
678
R
G
B
LED5
LED-RGB
R
G
B
LED5
LED-RGB
RN8 1KRN8 1K
12345
678
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RST_n
PB2PB3
PB1PB0
CONF
GND GNDGND GNDSW0 SW1 SW2 SW3
Button1Button2Button3
Button0
DIP_SW0DIP_SW1DIP_SW2DIP_SW3DIP_SW4DIP_SW5DIP_SW6DIP_SW7
CPU_RST_nnCONFIG
Button[0..3]
SW[0..3]
DIP_SW[0..7]
VCC33
VCC33
VCC33 VCC33
VCC33
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
DIP Swithc, Toggle Switch, Button Switch, CPU Reset, ReConfigure 1.1
DE3 Base BoardA
12 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
DIP Swithc, Toggle Switch, Button Switch, CPU Reset, ReConfigure 1.1
DE3 Base BoardA
12 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
DIP Swithc, Toggle Switch, Button Switch, CPU Reset, ReConfigure 1.1
DE3 Base BoardA
12 32Thursday, September 04, 2008
DEV_CLRn
nCONFIG
RECONFIGURE
TACT SW
RECONFIGURE
TACT SW
4 3
21
BUTTON0
TACT SW
BUTTON0
TACT SW
4 3
21
BUTTON1
TACT SW
BUTTON1
TACT SW
4 3
21
R127
100K
R127
100K
R100 120R100 120
RN15
100K
RN15
100K
1 2 3 45678
BUTTON3
TACT SW
BUTTON3
TACT SW
4 3
21
ON
1
SW4
SW-DIP16
ON
1
SW4
SW-DIP16
12345678
161514131211109
C32 1uC32 1u
CPU_RESET
TACT SW
CPU_RESET
TACT SW
4 3
21
C34 1uC34 1u
SW0
SLIDE SW
SW0
SLIDE SW
123
4
5C30 1uC30 1u
C31 1uC31 1u
SW1
SLIDE SW
SW1
SLIDE SW
123
4
5
RN12 120RN12 120
1234 5
678
R101 120R101 120
C28
10u
C28
10u
C29 1uC29 1u
R99
100K
R99
100K
RN11
100K
RN11
100K
12345 6 7 8
RN13
120
RN13
120
12345 6 7 8
RN14
100K
RN14
100K
1 2 3 45678 BC15
0.1u
BC15
0.1u
C33 1uC33 1u
SW2
SLIDE SW
SW2
SLIDE SW
123
4
5
U1
SN74AUC17
U1
SN74AUC17
1A12A33A54A95A116A13
1Y 22Y 43Y 64Y 85Y 106Y 12
GND 7
VCC14 ETP 15
SW3
SLIDE SW
SW3
SLIDE SW
123
4
5
BUTTON2
TACT SW
BUTTON2
TACT SW
4 3
21
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SD_DAT0
SD_DAT3SD_CMD
SD_DAT2
SD_DAT1
SD_WPn
SD_CLK
VCC33
VCC33
VCC33
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
SD Card Socket 1.1
DE3 Base BoardA
13 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
SD Card Socket 1.1
DE3 Base BoardA
13 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
SD Card Socket 1.1
DE3 Base BoardA
13 32Thursday, September 04, 2008
C35
10u
C35
10u
RN16
10K
RN16
10K
1 2 3 45678
912345678
11
J12
SD Card Socket
912345678
11
J12
SD Card Socket
DAT3CMDVSSVCCCLKVSSDAT0DAT1
DAT2
VSSWPVSSVSSVSSVSS
BC16
0.1u
BC16
0.1u
R102
10K
R102
10K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
GPIO_D0
GPIO_D14GPIO_D15
GPIO_D1
GPIO_D10GPIO_D12
GPIO_D11GPIO_D13
GPIO_D25
GPIO_D28 GPIO_D29GPIO_D26 GPIO_D27
GPIO_D30 GPIO_D31
GPIO_D24
GPIO_D42
GPIO_D58GPIO_D57
GPIO_D44
GPIO_D59GPIO_D60
GPIO_D55
GPIO_D53
GPIO_D62GPIO_D61
GPIO_D41
GPIO_D39
GPIO_D63
GPIO_D49
GPIO_D36
GPIO_D51
GPIO_D35
GPIO_D52
GPIO_D37
GPIO_D45GPIO_D43
GPIO_D54
GPIO_D38
GPIO_D40
GPIO_D50GPIO_D48
GPIO_D56
GPIO_D46GPIO_D47
GPIO_D32GPIO_D33
GPIO_D34GPIO_D2 GPIO_D3GPIO_D4 GPIO_D5GPIO_D6 GPIO_D7
GPIO_D8 GPIO_D9
GPIO_D23
GPIO_D21
GPIO_D17GPIO_D19
GPIO_D22
GPIO_D16GPIO_D18GPIO_D20
VCC50
VCC33 VCC33
VCC50
GPIO_D[0..31] GPIO_D[32..63]
GPIO_CLKINn0
GPIO_CLKOUTn0
GPIO_CLKINp0
GPIO_CLKOUTp0
GPIO_CLKINn1
GPIO_CLKOUTn1GPIO_CLKOUTp1
GPIO_CLKINp1
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
GPIO Connector 1.1
DE3 Base BoardA
14 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
GPIO Connector 1.1
DE3 Base BoardA
14 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
GPIO Connector 1.1
DE3 Base BoardA
14 32Thursday, September 04, 2008
(GPIO 0) (GPIO 1)
J13
BOX Header 2X20M
J13
BOX Header 2X20M
1 23 45 67 89 10
1113
1214161820222426
27
151719212325
28293133353739
303234363840
J14
BOX Header 2X20M
J14
BOX Header 2X20M
1 23 45 67 89 10
1113
1214161820222426
27
151719212325
28293133353739
303234363840
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HSTCA_RX_p10
HSTCA_RX_n10
HSTCA_RX_p11
HSTCA_RX_n11
HSTCA_RX_p12HSTCA_RX_n12
HSTCA_RX_p13HSTCA_RX_n13
HSTCA_RX_p14HSTCA_RX_n14
HSTCA_RX_n0
HSTCA_RX_p15HSTCA_RX_n15
HSTCA_RX_n1
HSTCA_RX_p0
HSTCA_RX_p1HSTCA_RX_p2
HSTCA_RX_p3
HSTCA_RX_n2
HSTCA_RX_n3
HSTCA_CLKIN_n0HSTCA_CLKIN_p0
HSTCA_CLKOUT_p0HSTCA_CLKOUT_n0
HSTCA_CLKOUT_p1HSTCA_CLKOUT_n1
HSTCA_CLKIN_p1HSTCA_CLKIN_n1
HSTCA_RX_p4
HSTCA_RX_n4
HSTCA_RX_p5HSTCA_RX_n5
HSTCA_TX_p15
HSTCA_TX_p4
HSTCA_TX_p5HSTCA_TX_p6
HSTCA_TX_p7
HSTCA_TX_p8HSTCA_TX_p9
HSTCA_TX_p10
HSTCA_TX_p0
HSTCA_TX_p11
HSTCA_TX_p12
HSTCA_TX_p1
HSTCA_TX_p13
HSTCA_TX_p2
HSTCA_TX_p14
HSTCA_TX_p3
HSTCA_RX_p6HSTCA_RX_n6
HSTCA_RX_p7HSTCA_RX_n7
HSTCA_TX_n15
HSTCA_TX_n4
HSTCA_TX_n0
HSTCA_TX_n5HSTCA_TX_n6
HSTCA_TX_n7
HSTCA_TX_n8HSTCA_TX_n9
HSTCA_TX_n10HSTCA_TX_n11
HSTCA_TX_n12
HSTCA_TX_n1
HSTCA_TX_n13
HSTCA_TX_n2
HSTCA_TX_n14
HSTCA_TX_n3
HSTCA_RX_p8HSTCA_RX_n8
HSTCA_RX_p9HSTCA_RX_n9
HSTCA_RX_n[0..15]
HSTCA_TX_p[0..15]HSTCA_TX_n[0..15]
HSTCA_RX_p[0..15]
HSTCA_CLKIN_p[0..1]HSTCA_CLKIN_n[0..1]
HSTCA_CLKOUT_p[0..1]HSTCA_CLKOUT_n[0..1]
GPIO_D0
GPIO_D8
GPIO_D16
GPIO_D24
GPIO_D32
GPIO_D40
GPIO_D56
GPIO_D48
GPIO_D1
GPIO_D9
GPIO_D41
GPIO_D33
GPIO_D25
GPIO_D17
GPIO_D49
GPIO_D57
GPIO_D34
GPIO_D42
GPIO_D10
GPIO_D2
GPIO_D58
GPIO_D50
GPIO_D18
GPIO_D26
GPIO_D35
GPIO_D59
GPIO_D3
GPIO_D11
GPIO_D43
GPIO_D27
GPIO_D19
GPIO_D51
GPIO_D12
GPIO_D4
GPIO_D60
GPIO_D36
GPIO_D52
GPIO_D20
GPIO_D28
GPIO_D44
GPIO_D13
GPIO_D53
GPIO_D37
GPIO_D61
GPIO_D5
GPIO_D45
GPIO_D29
GPIO_D21
GPIO_D62
GPIO_D38
GPIO_D54
GPIO_D14
GPIO_D22
GPIO_D30
GPIO_D46
GPIO_D6
GPIO_D63
GPIO_D23
GPIO_D15
GPIO_D55
GPIO_D39
GPIO_D7
GPIO_D47
GPIO_D31
GPIO_CLKINn0
GPIO_CLKOUTn0
GPIO_CLKINn1
GPIO_CLKOUTn1
GPIO_CLKINp0
GPIO_CLKOUTp0
GPIO_CLKOUTp1
GPIO_CLKINp1
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
HSTC A to GPIO 1.1
DE3 Base Board
32Thursday, September 04, 2008 15
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
HSTC A to GPIO 1.1
DE3 Base Board
32Thursday, September 04, 2008 15
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
HSTC A to GPIO 1.1
DE3 Base Board
32Thursday, September 04, 2008 15
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
OTG_D15OTG_D14OTG_D13OTG_D12OTG_D11OTG_D10OTG_D9OTG_D8OTG_D7OTG_D6
OTG_D4OTG_D5
OTG_D3OTG_D2OTG_D1OTG_D0
OTG_D16OTG_D17OTG_D18OTG_D19OTG_D20OTG_D21OTG_D22OTG_D23OTG_D24OTG_D25OTG_D26OTG_D27OTG_D28OTG_D29OTG_D30OTG_D31
OTG_A1OTG_A2OTG_A3OTG_A4OTG_A5OTG_A6OTG_A7OTG_A8OTG_A9OTG_A10OTG_A11OTG_A12OTG_A13OTG_A14OTG_A15OTG_A16OTG_A17
VBUS3
USB_ID
USB_ID
DM2
VBUS2
DP1DM1
VBUS1
DP3DM3
USB_ID
PSW2
OC1
PSW3
OTG_HC_IRQ
OTG_CS_n
OTG_DC_IRQ
OTG_WE_nOTG_OE_n
OTG_HC_DACKOTG_DC_DACK
DP2
PSW1
OC2
OC3
OTG_D[0..31]
OTG_HC_IRQOTG_DC_IRQ
OTG_DC_DREQ
OTG_HC_DREQ
OTG_A[1..17]
OTG_WE_nOTG_OE_n
OTG_RESET_n
OTG_CS_n
OTG_DC_DACK
OTG_HC_DACK
12MHZ
U_VCC33
U_VCC33VCC33U_VCC5VCC50
U_VCC33
U_VCC33 U_VCC5
U_VCC33
VBUS1
VBUS1
VBUS2
VBUS3
VBUS3VBUS2
U_VCC5
U_VCC5
U_VCC5
U_VCC5
U_VCC33
U_VCC5
VBUS1 VBUS1
VBUS2VBUS2
VBUS3VBUS3
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
ISP 1761 1.1
DE3 Base BoardB
16 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
ISP 1761 1.1
DE3 Base BoardB
16 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
ISP 1761 1.1
DE3 Base BoardB
16 32Thursday, September 04, 2008
JP1: OTG modeOpen : DEVICEClose : HOST
VBUS
D-
D+
ID
GND
Mini-USB AB
J15
Jack-Mini-USB-AB
VBUS
D-
D+
ID
GND
Mini-USB AB
J15
Jack-Mini-USB-AB
123
5
7 6
4
89
R109 10KR109 10K
R11110K R11110KR11010K R11010K
R116 100R116 100
D3
BAT54SDW
D3
BAT54SDW
1
2
6
3 4
5
C44
100u
C44
100u
L1 BEADL1 BEAD
C39 10uC39 10u
BC30
0.1u
BC30
0.1u
BC18 0.1uBC18 0.1u
BC28
0.1u
BC28
0.1u
USB3 LEDBUSB3 LEDB
BC27
0.1u
BC27
0.1u
R114 100R114 100
R113 10KR113 10K
USB2 LEDBUSB2 LEDB
C40
10u
C40
10u
R119 4.7KR119 4.7K
BC33
0.1u
BC33
0.1u
R108 10KR108 10K
BC17 0.1uBC17 0.1u
BC23 0.1uBC23 0.1u
U2
ISP1761ET
U2
ISP1761ET
A1H16A2H15A3H14A4F16A5F15A6F14A7E15A8D16A9C16A10C15A11B16A12B15A13A15A14B14A15A14A16A13A17C12
BAT_ON C10
C_A B4C_B A5
CLKINF1
CSA12
DATA0R3DATA1T3DATA2R4DATA3P5DATA4T5DATA5R5DATA6R6DATA7P7DATA8T7DATA9T8DATA10P9DATA11T9DATA12T10DATA13P11DATA14T11DATA15R11DATA16R12DATA17T13DATA18R13DATA19T14DATA20T15DATA21R15DATA22T16DATA23R16DATA24P16DATA25N15DATA26M15DATA27M16DATA28L16DATA29L15DATA30K16DATA31K14
DC_DACKB8 DC_DREQA9
DC_IRQA10
DC_SUSPEND/WAKEUP C6
DM1 H1
DM2 L1
DM3 P1
DP1 J2
DP2 M2
DP3 R1
HC_DACKA8 HC_DREQB9
HC_IRQB10
HC_SUSPEND/WAKEUP A7
ID B2
OC1/VBUS B3
OC2 A3
OC3 C2
PSW1 J1
PSW2 M1
PSW3 T1
RDB12
REF5V A2
REG1V8 B1REG1V8 B7REG1V8 R8REG1V8 G16
REG3V3 D1
RESETB6RREF1 G1RREF2 K1RREF3 N1
TEST J16
WRB11
XTAL1E1XTAL2F2
GN
D_O
SCE3
GND_REF1 G2GND_REF2 K2GND_REF3 N2
GN
DA
J3G
ND
AH
2
GN
DA
A1
GN
DA
R2
GN
DA
L3G
ND
AL2
GN
DA
P2
GN
DA
B5
GN
DC
R9
GN
DC
G15
GN
DC
A6
GN
DD
A16
GN
DD
A11
GN
DD
G3
GN
DD
T2
GN
DD
E16
GN
DD
R14
GN
DD
T6
GN
DD
N16
GN
DD
K15
GN
DD
R10
VCC
5VC
1VC
C5V
D2
VCC
INA4
VCC
IOC
8
VCC
IOM
14
VCC
IOT4
VCC
IOB1
3
VCC
IOJ1
5
VCC
IOP1
5
VCC
IOT1
2
VCC
IOR
7
VCC
IOE2
VCC
IOD
15
C38 10uC38 10u
BC29
0.1u
BC29
0.1u
R118 100R118 100
R117 10KR117 10K
R125 12KR125 12K
BC34
0.1u
BC34
0.1u
R123 12KR123 12K
D4
PMG2005EB
D4
PMG2005EB
BC31
0.1u
BC31
0.1u
R105 10KR105 10K
L2 BEADL2 BEAD
BC20 0.1uBC20 0.1u
BC26
0.1u
BC26
0.1u
R122 560R122 560
R11210K R11210K
L3 BEADL3 BEAD
BC25 0.1uBC25 0.1u
R107 10KR107 10K
BC32
0.1u
BC32
0.1u
R115 10KR115 10K
R126 0R126 0
BC19 0.1uBC19 0.1u
Q1 FDN338PQ1 FDN338P
BC22 0.1uBC22 0.1u
R120 560R120 560
R124 12KR124 12K
JP1 SIP2JP1 SIP21 2
R121 560R121 560
VBUS
D-
D+
GND
J17
USB A-TYPE
VBUS
D-
D+
GND
J17
USB A-TYPE
1234
56
VBUS
D-
D+
GND
J16
USB A-TYPE
VBUS
D-
D+
GND
J16
USB A-TYPE
1234
56
C43
100u
C43
100u
D1
BAT54SDW
D1
BAT54SDW
1
2
6
3 4
5
C42
100u
C42
100u
Q2 FDN338PQ2 FDN338P
BC24 0.1uBC24 0.1u
C41
10u
C41
10u
USB1 LEDBUSB1 LEDBC37 10uC37 10u
C45
47p
C45
47p
Q3 FDN338PQ3 FDN338P
R103 10KR103 10K
C36 0.22uC36 0.22u
R128 22R128 22
D2
BAT54SDW
D2
BAT54SDW
1
2
6
3 4
5
R106 10KR106 10K
BC21 0.1uBC21 0.1u
BC35
0.1u
BC35
0.1u
R104 10KR104 10K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HSTCA_RDN2AHSTCA_RUP2AHSTCD_RDN1A
HSTCD_RUP1A
HSTCD_RDN1AHSTCD_RUP1A
HSTCD_RX_p2HSTCD_RX_n2
HSTCD_RX_p3HSTCD_RX_n3
HSTCD_RX_p0HSTCD_RX_n0
HSTCD_RX_n8HSTCD_RX_p8
HSTCD_RX_p4HSTCD_RX_n4
HSTCD_RX_p5HSTCD_RX_n5
HSTCD_RX_p6HSTCD_RX_n6
HSTCD_RX_p7HSTCD_RX_n7
HSTCD_RX_p1HSTCD_RX_n1
HSTCD_TX_n2HSTCD_TX_p2HSTCD_TX_n3HSTCD_TX_p3
HSTCD_TX_p8HSTCD_TX_n8
HSTCD_TX_n0HSTCD_TX_p0
HSTCD_TX_n4HSTCD_TX_p4HSTCD_TX_n5HSTCD_TX_p5HSTCD_TX_n6HSTCD_TX_p6HSTCD_TX_n7HSTCD_TX_p7
HSTCD_TX_n1HSTCD_TX_p1
JVC0JVC1JVC2JVC3
HSTCA_RDN2A
HSTCA_RX_p2HSTCA_RX_n2
HSTCA_RX_p3
HSTCA_RX_p5
HSTCA_RX_n3
HSTCA_RX_n5
HSTCA_RX_p1HSTCA_RX_n1
HSTCA_RX_p4HSTCA_RX_n4
HSTCA_RX_p0HSTCA_RX_n0HSTCA_RUP2A
HSTCA_RX_p6
HSTCA_RX_p8
HSTCA_RX_n6
HSTCA_RX_n8HSTCA_RX_p7HSTCA_RX_n7
HSTCA_TX_n1
HSTCA_TX_n2
HSTCA_TX_n3
HSTCA_TX_n4
HSTCA_TX_n5
HSTCA_TX_n0
HSTCA_TX_p1
HSTCA_TX_p2
HSTCA_TX_p3
HSTCA_TX_p4
HSTCA_TX_p5
HSTCA_TX_p0
HSTCA_TX_n6
HSTCA_TX_n7
HSTCA_TX_n8
HSTCA_TX_p6
HSTCA_TX_p7
HSTCA_TX_p8
OTG_A6
OTG_A7
OTG_A8
OTG_A9
OTG_A10
OTG_A11
OTG_A12OTG_A13OTG_A15
OTG_A1
OTG_A16OTG_A17
OTG_A2OTG_A3
OTG_A4
OTG_A5
OTG_A14
OTG_D11
OTG_D10
OTG_D9
OTG_D8
OTG_D7
OTG_D6
OTG_D4OTG_D5
OTG_D3
OTG_D2OTG_D0
OTG_D1OTG_D13
OTG_D12
OTG_D16
OTG_D15
OTG_D14OTG_D17
OTG_D18
OTG_D19
OTG_D20
OTG_D23OTG_D24
OTG_D25
OTG_D26
OTG_D22
OTG_D27OTG_D28OTG_D29OTG_D30
OTG_D31
OTG_D21
OTG_D[0..31]OTG_A[1..17]
HSTCD_TX_p[0..8]HSTCD_TX_n[0..8]HSTCD_RX_p[0..8]HSTCD_RX_n[0..8]
HSTCD_CLKIN_p0HSTCD_CLKIN_n0
CPU_RST_n
OSC1_50
HSTCD_CLKOUT_2
HSTCA_TX_p[0..8]HSTCA_TX_n[0..8]HSTCA_RX_p[0..8]HSTCA_RX_n[0..8]
JVC[0..3]
HSTCA_CLKIN_n0HSTCA_CLKIN_p0
HSTCA_CLKOUT_2
OTG_CS_n
OTG_WE_nOTG_OE_n
OTG_RESET_n
OTG_HC_IRQ
OTG_DC_IRQOTG_HC_DREQ
OTG_DC_DREQOTG_HC_DACKOTG_DC_DACK
HSTCA_SDAHSTCA_SCL
HSTCD_SDAHSTCD_SCL
BA_VCCIOBD_VCCIO
DATA
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
EP2C70 BANK1 AND BANK 2 1.1
DE3 Base BoardB
17 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
EP2C70 BANK1 AND BANK 2 1.1
DE3 Base BoardB
17 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
EP2C70 BANK1 AND BANK 2 1.1
DE3 Base BoardB
17 32Thursday, September 04, 2008
R131 49.9R131 49.9R129 49.9R129 49.9
Bank 2A
Bank 2C
U3B
EP3SL150F1152
Bank 2A
Bank 2C
U3B
EP3SL150F1152
DIFFIO_RX_L33nAF34DIFFIO_RX_L33pAG33
DIFFIO_RX_L34nAE32DIFFIO_RX_L34pAE31
DIFFIO_RX_L35n,DQ24LAG34DIFFIO_RX_L35p,DQ24LAH33
DIFFIO_RX_L36n,DQSn24LAF32DIFFIO_RX_L36p,DQS24LAF31
DIFFIO_RX_L37n,DQ24LAH34DIFFIO_RX_L37p,DQ24LAJ34
DIFFIO_RX_L38n,DQ25LAG32DIFFIO_RX_L38p,DQ25LAG31
DIFFIO_RX_L39n,DQSn25LAK34DIFFIO_RX_L39p,DQS25LAK33
DIFFIO_RX_L40n,DQ25LAJ32DIFFIO_RX_L40p,DQ25LAJ31
DIFFIO_RX_L41n,DQ26LAL34DIFFIO_RX_L41p,DQ26LAM34
DIFFIO_RX_L42n,DQSn26LAH31DIFFIO_RX_L42p,DQS26LAH30
DIFFIO_RX_L43n,DQ26LAL33DIFFIO_RX_L43p,DQ26LAL32
DIFFIO_RX_L44n,RDN2AAK32DIFFIO_RX_L44p,RUP2AAK31
DIFFIO_TX_L33n AA25DIFFIO_TX_L33p AA24
DIFFIO_TX_L34n AC29DIFFIO_TX_L34p AC28
DIFFIO_TX_L35n,DQ24L AD31DIFFIO_TX_L35p,DQ24L AD30
DIFFIO_TX_L36n,DQ24L AB25DIFFIO_TX_L36p,DQ24L AB24
DIFFIO_TX_L37n,DQ24L AB27DIFFIO_TX_L37p,DQ24L AB26
DIFFIO_TX_L38n,DQ25L AE30DIFFIO_TX_L38p,DQ25L AE29
DIFFIO_TX_L39n,DQ25L AD29DIFFIO_TX_L39p,DQ25L AD28
DIFFIO_TX_L40n,DQ25L AF29DIFFIO_TX_L40p,DQ25L AF28
DIFFIO_TX_L41n,DQ26L AE28DIFFIO_TX_L41p,DQ26L AE27
DIFFIO_TX_L42n,DQ26L AD27DIFFIO_TX_L42p,DQ26L AD26
DIFFIO_TX_L43n,DQ26L AC26DIFFIO_TX_L43p,DQ26L AC25
DIFFIO_TX_L44n AG30DIFFIO_TX_L44p AG29
CLK2n,DIFFIO_RX_L23nW34CLK2p,DIFFIO_RX_L23pW33
DIFFIO_RX_L24n,DQ17LY34DIFFIO_RX_L24p,DQ17LAA33
DIFFIO_RX_L25n,DQSn17LY32DIFFIO_RX_L25p,DQS17LY31
DIFFIO_RX_L26n,DQ17LAA34DIFFIO_RX_L26p,DQ17LAB33
DIFFIO_RX_L27n,DQ18LAA32DIFFIO_RX_L27p,DQ18LAA31
DIFFIO_RX_L28n,DQSn18LAB34DIFFIO_RX_L28p,DQS18LAC34
DIFFIO_RX_L29n,DQ18LAB32DIFFIO_RX_L29p,DQ18LAB31
DIFFIO_RX_L30n,DQ19LAD34DIFFIO_RX_L30p,DQ19LAD33
DIFFIO_RX_L31n,DQSn19LAC32DIFFIO_RX_L31p,DQS19LAC31
DIFFIO_RX_L32n,DQ19LAE34DIFFIO_RX_L32p,DQ19LAE33
DIFFIO_TX_L24n,DQ17L W27DIFFIO_TX_L24p,DQ17L W26
DIFFIO_TX_L25n,DQ17L V25DIFFIO_TX_L25p,DQ17L V24
DIFFIO_TX_L26n,DQ17L W31DIFFIO_TX_L26p,DQ17L W30
DIFFIO_TX_L27n,DQ18L Y29DIFFIO_TX_L27p,DQ18L Y28
DIFFIO_TX_L28n,DQ18L W24DIFFIO_TX_L28p,DQ18L Y23
DIFFIO_TX_L29n,DQ18L AA30DIFFIO_TX_L29p,DQ18L AA29
DIFFIO_TX_L30n,DQ19L Y26DIFFIO_TX_L30p,DQ19L Y25
DIFFIO_TX_L31n,DQ19L AA28DIFFIO_TX_L31p,DQ19L AA27
DIFFIO_TX_L32n,DQ19L AB30DIFFIO_TX_L32p,DQ19L AB29
PLL_L3_CLKOUT0n,DIFFIO_TX_L23n V29PLL_L3_FB_CLKOUT0p,DIFFIO_TX_L23p W28
CLK3nV34CLK3pV33
R130 49.9R130 49.9
Bank 1A
Bank 1C
U3A
EP3SL150F1152
Bank 1A
Bank 1C
U3A
EP3SL150F1152
DIFFIO_RX_L1n,RDN1AE32DIFFIO_RX_L1p,RUP1AE31DIFFIO_RX_L2n,DQ1LF32DIFFIO_RX_L2p,DQ1LF31DIFFIO_RX_L3n,DQSn1LC34DIFFIO_RX_L3p,DQS1LC33DIFFIO_RX_L4n,DQ1LH32DIFFIO_RX_L4p,DQ1LH31DIFFIO_RX_L5n,DQ2LD34DIFFIO_RX_L5p,DQ2LD33DIFFIO_RX_L6n,DQSn2LJ32DIFFIO_RX_L6p,DQS2LJ31DIFFIO_RX_L7n,DQ2LE34DIFFIO_RX_L7p,DQ2LF33DIFFIO_RX_L8n,DQ3LF34DIFFIO_RX_L8p,DQ3LG33DIFFIO_RX_L9n,DQSn3LK32DIFFIO_RX_L9p,DQS3LK31DIFFIO_RX_L10n,DQ3LG34DIFFIO_RX_L10p,DQ3LH34DIFFIO_RX_L11nJ34DIFFIO_RX_L11pJ33DIFFIO_RX_L12nK34DIFFIO_RX_L12pK33
DIFFIO_TX_L1n G31DIFFIO_TX_L1p G30
DIFFIO_TX_L2n,DQ1L J30DIFFIO_TX_L2p,DQ1L J29DIFFIO_TX_L3n,DQ1L K28DIFFIO_TX_L3p,DQ1L K27DIFFIO_TX_L4nDQ1L N25
DIFFIO_TX_L4p,DQ1L M24DIFFIO_TX_L5n,DQ2L M27DIFFIO_TX_L5p,DQ2L M26DIFFIO_TX_L6n,DQ2L K30DIFFIO_TX_L6p,DQ2L K29DIFFIO_TX_L7n,DQ2L L29DIFFIO_TX_L7p,DQ2L L28DIFFIO_TX_L8n,DQ3L M28DIFFIO_TX_L8p,DQ3L N27DIFFIO_TX_L9n,DQ3L N26DIFFIO_TX_L9p,DQ3L P25
DIFFIO_TX_L10n,DQ3L L32DIFFIO_TX_L10p,DQ3L L31
DIFFIO_TX_L11n N24DIFFIO_TX_L11p P23DIFFIO_TX_L12n M30DIFFIO_TX_L12p M29
CLK0n,DIFFIO_RX_L22nV32CLK0p,DIFFIO_RX_L22pV31
DIFFIO_RX_L13n,DQ8LN32DIFFIO_RX_L13p,DQ8LM31DIFFIO_RX_L14n,DQSN8LL34DIFFIO_RX_L14p,DQS8LM33DIFFIO_RX_L15n,DQ8LP32DIFFIO_RX_L15p,DQ8LN31DIFFIO_RX_L16n,DQ9LM34DIFFIO_RX_L16p,DQ9LN33DIFFIO_RX_L17n,DQSN9LR32DIFFIO_RX_L17p,DQS9LP31DIFFIO_RX_L18n,DQ9LN34DIFFIO_RX_L18p,DQ9LP34DIFFIO_RX_L19n,DATA2R34DIFFIO_RX_L19p,DATA3R33DIFFIO_RX_L20n,DATA6T32DIFFIO_RX_L20p,DATA7R31DIFFIO_RX_L21n,DEV_OEU32DIFFIO_RX_L21p,DEV_CLRnU31
DIFFIO_TX_L13n.DQ8L N30DIFFIO_TX_L13p,DQ8L N29DIFFIO_TX_L14n,DQ8L P29DIFFIO_TX_L14p,DQ8L P28DIFFIO_TX_L15n,DQ8L R26DIFFIO_TX_L15p,DQ8L R25DIFFIO_TX_L16n,DQ9L R24DIFFIO_TX_L16p,DQ9L T23DIFFIO_TX_L17n,DQ9L R28DIFFIO_TX_L17p,DQ9L R27
DIFFIO_TX_L18n,CLKUSR R30DIFFIO_TX_L18p,DQ9L R29
DIFFIO_TX_L19n,DATA0 T28DIFFIO_TX_L19p,DATA1 T27DIFFIO_TX_L20n,DATA4 T25DIFFIO_TX_L20p,DATA5 T24
DIFFIO_TX_L21n,INIT_DONE T26DIFFIO_TX_L21p,CRC_ERROR U25
PLL_L2_CLKOUT0n,DIFFIO_TX_L22n T30PLL_L2_FB_CLKOUT0p,DIFFIO_TX_L22p T29
CLK1nT34CLK1pT33
R132 49.9R132 49.9
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A AHSTCA_RDN3AHSTCA_RUP3A
HSTCB_RDN4AHSTCB_RUP4A
HSTCA_RX_n23HSTCA_RX_p23
HSTCA_RX_p18HSTCA_RX_n18
HSTCA_RX_n24HSTCA_RX_p24
HSTCA_RX_n19HSTCA_RX_p19
HSTCA_RX_p25HSTCA_RX_n25
HSTCA_RX_p20HSTCA_RX_n20
HSTCA_RX_n27HSTCA_RX_p27
HSTCA_RX_n22HSTCA_RX_p22
HSTCA_RDN3AHSTCA_RUP3A
HSTCA_RX_n21HSTCA_RX_p21
HSTCA_RX_p29HSTCA_RX_n29
HSTCA_RX_n28HSTCA_RX_p28
HSTCA_TX_n27HSTCA_TX_p27
HSTCA_CLKOUT_p1HSTCA_CLKOUT_n1
HSTCA_TX_n20HSTCA_TX_p20
HSTCA_TX_n29
HSTCA_TX_n28HSTCA_TX_p28
HSTCA_TX_p29
HSTCA_TX_n21
HSTCA_TX_n22
HSTCA_TX_n23
HSTCA_TX_p21
HSTCA_TX_p22
HSTCA_TX_p23
HSTCA_TX_n18HSTCA_TX_p18
HSTCA_TX_n25HSTCA_TX_p25
HSTCA_CLKOUT_n0HSTCA_CLKOUT_p0
HSTCA_TX_n19HSTCA_TX_p19
HSTCB_RX_n18HSTCB_RX_p18
HSTCB_RX_n19HSTCB_RX_p19
HSTCB_RDN4AHSTCB_RUP4A
HSTCB_RX_p15HSTCB_RX_n15
HSTCB_RX_n20HSTCB_RX_p20
HSTCB_RX_p28HSTCB_RX_n28
HSTCB_RX_p9HSTCB_RX_n9
HSTCB_RX_p27HSTCB_RX_n27
HSTCB_RX_p16HSTCB_RX_n16
HSTCB_RX_p21HSTCB_RX_n21
HSTCB_RX_p26HSTCB_RX_n26
HSTCB_RX_p10HSTCB_RX_n10
HSTCB_RX_p17HSTCB_RX_n17
HSTCB_RX_p22HSTCB_RX_n22
HSTCB_RX_p11HSTCB_RX_n11
HSTCB_RX_p29HSTCB_RX_n29
HSTCB_RX_n23HSTCB_RX_p23
HSTCB_RX_p12HSTCB_RX_n12
HSTCB_RX_p24HSTCB_RX_n24
HSTCB_RX_p13HSTCB_RX_n13
HSTCB_RX_p25HSTCB_RX_n25
HSTCB_RX_p14HSTCB_RX_n14 HSTCB_TX_n14
HSTCB_TX_p14
HSTCB_TX_n25HSTCB_TX_p25
HSTCB_TX_n19HSTCB_TX_p19
HSTCB_TX_n28HSTCB_TX_p28HSTCB_TX_n29HSTCB_TX_p29
HSTCB_TX_n13HSTCB_TX_p13
HSTCB_TX_n26HSTCB_TX_p26
HSTCB_TX_n18HSTCB_TX_p18
HSTCB_TX_p12HSTCB_TX_n12
HSTCB_TX_n24HSTCB_TX_p24
HSTCB_TX_n11HSTCB_TX_p11
HSTCB_TX_n23HSTCB_TX_p23
HSTCB_TX_n17HSTCB_TX_p17
HSTCB_TX_n10HSTCB_TX_p10
HSTCB_TX_n22HSTCB_TX_p22
HSTCB_CLKOUT_n1HSTCB_CLKOUT_p1
HSTCB_TX_p16HSTCB_TX_n16
HSTCB_TX_n27HSTCB_TX_p27
HSTCB_TX_n21HSTCB_TX_p21
HSTCB_CLKOUT_n0HSTCB_CLKOUT_p0
HSTCB_TX_n15HSTCB_TX_p15
HSTCB_TX_n9HSTCB_TX_p9
HSTCB_TX_n20HSTCB_TX_p20
HSTCA_TX_n24HSTCA_TX_p24
HSTCA_TX_n26HSTCA_TX_p26
HSTCA_RX_p26HSTCA_RX_n26
HSTCA_RX_p11HSTCA_RX_n11
HSTCA_RX_p10HSTCA_RX_n10
HSTCA_RX_n16HSTCA_RX_p16
HSTCA_RX_p17HSTCA_RX_n17
HSTCA_RX_n15HSTCA_RX_p15HSTCA_RX_n14HSTCA_RX_p14
HSTCA_RX_n12HSTCA_RX_p12
HSTCA_RX_n13HSTCA_RX_p13
HSTCA_RX_p9HSTCA_RX_n9
HSTCA_TX_n16HSTCA_TX_p16
HSTCA_TX_n11HSTCA_TX_p11
HSTCA_TX_n17HSTCA_TX_p17
HSTCA_TX_n12HSTCA_TX_p12
HSTCA_TX_n13HSTCA_TX_p13
HSTCA_TX_n9HSTCA_TX_p9
HSTCA_TX_n14HSTCA_TX_p14
HSTCA_TX_n15HSTCA_TX_p15
HSTCA_TX_n10HSTCA_TX_p10
HSTCA_CLKOUT_p[0..1]HSTCA_CLKOUT_n[0..1]
HSTCA_TX_p[9..29]HSTCA_TX_n[9..29]HSTCA_RX_p[9..29]HSTCA_RX_n[9..29]
HSTCA_CLKIN_2OSC_BA HSTCA_CLKIN_p1
HSTCA_CLKIN_n1
HSTCB_CLKOUT_p[0..1]HSTCB_CLKOUT_n[0..1]
HSTCB_TX_n[9..29]HSTCB_RX_p[9..29]HSTCB_RX_n[9..29]
HSTCB_TX_p[9..29]
OSC_BBHSTCB_CLKIN_2 HSTCB_CLKIN_n1
HSTCB_CLKIN_p1
BA_VCCIOBB_VCCIO
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
EP2C70 BANK3 AND BANK 4 1.1
DE3 Base BoardB
18 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
EP2C70 BANK3 AND BANK 4 1.1
DE3 Base BoardB
18 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
EP2C70 BANK3 AND BANK 4 1.1
DE3 Base BoardB
18 32Thursday, September 04, 2008
R135 49.9R135 49.9R136 49.9R136 49.9
R133 49.9R133 49.9
Bank 4B
Bank 4C
Bank 4A
U3D
EP3SL150F1152
Bank 4B
Bank 4C
Bank 4A
U3D
EP3SL150F1152
DIFFIO_RX_B39nAD12DIFFIO_RX_B39pAC12
DIFFIO_RX_B40n,DQ24BAJ12DIFFIO_RX_B40p,DQ24BAH12
DIFFIO_RX_B41n,DQSn24BAJ11DIFFIO_RX_B41p,DQS24BAH11
DIFFIO_RX_B42n,DQ24BAL9DIFFIO_RX_B42p,DQ24BAK9
DIFFIO_RX_B43n,DQ25BAP4DIFFIO_RX_B43p,DQ25BAN4
DIFFIO_RX_B44n,DQSn25BAP3DIFFIO_RX_B44p,DQS25BAN3
DIFFIO_RX_B45n,DQ25BAM5DIFFIO_RX_B45p,DQ25BAL5
DIFFIO_RX_B46n,DQ26BAK7DIFFIO_RX_B46p,DQ26BAJ7
DIFFIO_RX_B47n,DQSn26BAJ8DIFFIO_RX_B47p,DQS26BAH8
DIFFIO_RX_B48n,RDN4AAH9DIFFIO_RX_B48p,RUP4AAG9
DIFFOUT_B78n AD13DIFFOUT_B78p AE12
DIFFOUT_B80n,DQ24B AJ13DIFFOUT_B80p,DQ24B AG12
DIFFOUT_B82n,DQ24B AL8DIFFOUT_B82p,DQ24B AJ10
DIFFOUT_B84n,DQ24B AJ9DIFFOUT_B84p,DQ24B AL7
DIFFOUT_B86n,DQ25B AP5DIFFOUT_B86p,DQ25B AP2
DIFFOUT_B88n,DQ25B AN6DIFFOUT_B88p,DQ25B AM6
DIFFOUT_B90n,DQ25B AM4DIFFOUT_B90p,DQ25B AL4
DIFFOUT_B92n,DQ26B AK6DIFFOUT_B92p,DQ26B AJ6
DIFFOUT_B94n,DQ26B AF11DIFFOUT_B94p,DQ26B AE11
DIFFOUT_B96n,DQ26B AF10DIFFOUT_B96p,DQ26B AE10
DIFFIO_RX_B33n,DQ19BAP10DIFFIO_RX_B33p,DQ19BAN10
DIFFIO_RX_B34n,DQSn19BAN9DIFFIO_RX_B34p,DQS19BAM9
DIFFIO_RX_B35n,DQ19BAF14DIFFIO_RX_B35p,DQ19BAF13
DIFFIO_RX_B36n,DQ20BAL12DIFFIO_RX_B36p,DQ20BAK12
DIFFIO_RX_B37n,DQSn20BAL11DIFFIO_RX_B37p,DQS20BAL10
DIFFIO_RX_B38n,DQ20BAP7DIFFIO_RX_B38p,DQ20BAN7
DIFFOUT_B66n,DQ19B AP11DIFFOUT_B66p,DQ19B AP9
DIFFOUT_B68n,DQ19B AF15DIFFOUT_B68p,DQ19B AE15
DIFFOUT_B70n,DQ19B AE14DIFFOUT_B70p,DQ19B AE13
DIFFOUT_B72n,DQ20B AM11DIFFOUT_B72p,DQ20B AK10
DIFFOUT_B74n,DQ20B AP8DIFFOUT_B74p,DQ20B AM8
DIFFOUT_B76n,DQ20B AM7DIFFOUT_B76p,DQ20B AP6
CLK6n,DIFFIO_RX_B25nAP16CLK6p,DIFFIO_RX_B25pAN16 CLK7n,DIFFOUT_B50n AP15
CLK7p,DIFFOUT_B50p AN15
DIFFIO_RX_B27nAM16DIFFIO_RX_B27pAL16
DIFFIO_RX_B28nAK16DIFFIO_RX_B28pAJ16
DIFFIO_RX_B29nAM14DIFFIO_RX_B29pAL14
DIFFIO_RX_B30n,DQ16BAJ15DIFFIO_RX_B30p,DQ16BAH15
DIFFIO_RX_B31n,DQSN16BAJ14DIFFIO_RX_B31p,DQS16BAH14
DIFFIO_RX_B32n,DQ16BAP12DIFFIO_RX_B32p,DQ16BAN12
DIFFOUT_B56n AM15DIFFOUT_B56p AL15
DIFFOUT_B58n AL13DIFFOUT_B58p AK13
DIFFOUT_B60n,DQ16B AK15DIFFOUT_B60p,DQ16B AG15
DIFFOUT_B62n,DQ16B AN13DIFFOUT_B62p,DQ16B AP14
DIFFOUT_B64n,DQ16B AP13DIFFOUT_B64p,DQ16B AM12
PLL_B2_CLKOUT0n,DIFFOUT_B52n AF16PLL_B2_CLKOUT0p,DIFFOUT_B52p AE16
PLL_B2_CLKOUT3,DIFFOUT_B54p AD15PLL_B2_CLKOUT4,DIFFOUT_B54n AD16
PLL_B2_FBn/CLKOUT2,DIFFIO_RX_B26nAM17PLL_B2_FBp/CLKOUT1,DIFFIO_RX_B26pAL17
Bank 3A
Bank 3B
Bank 3C
U3C
EP3SL150F1152
Bank 3A
Bank 3B
Bank 3C
U3C
EP3SL150F1152
DIFFIO_RX_B1n,RDN3AAK28DIFFIO_RX_B1p,RUP3AAJ28DIFFIO_RX_B2n,DQSn1BAM32DIFFIO_RX_B2p,DQS1BAM31DIFFIO_RX_B3n,DQ1BAN30DIFFIO_RX_B3p,DQ1BAM30DIFFIO_RX_B4n,DQ2BAH24DIFFIO_RX_B4p,DQ2BAG24DIFFIO_RX_B5n,DQSn2BAP33DIFFIO_RX_B5p,DQS2BAN33DIFFIO_RX_B6n,DQ2BAP31DIFFIO_RX_B6p,DQ2BAN31DIFFIO_RX_B7n,DQ3BAL27DIFFIO_RX_B7p,DQ3BAL26DIFFIO_RX_B8n,DQSn3BAP28DIFFIO_RX_B8p,DQS3BAN28DIFFIO_RX_B9n,DQ3BAP27DIFFIO_RX_B9p,DQ3BAN27DIFFIO_RX_B10nAD22DIFFIO_RX_B10pAC22
DIFFOUT_B1n,DQ1B AH27DIFFOUT_B1p,DQ1B AJ27DIFFOUT_B3n,DQ1B AJ29DIFFOUT_B3p,DQ1B AJ26DIFFOUT_B5n,DQ1B AL29DIFFOUT_B5p,DQ1B AM29DIFFOUT_B7n,DQ2B AH26DIFFOUT_B7p,DQ2B AF24DIFFOUT_B9n,DQ2B AH25DIFFOUT_B9p,DQ2B AF23
DIFFOUT_B11n,DQ2B AP32DIFFOUT_B11p,DQ2B AP30DIFFOUT_B13n,DQ3B AK27DIFFOUT_B13p,DQ3B AL28DIFFOUT_B15n,DQ3B AK25DIFFOUT_B15p,DQ3B AM26DIFFOUT_B17n,DQ3B AM28DIFFOUT_B17p,DQ3B AP29
DIFFOUT_B19n AE24DIFFOUT_B19p AE23
DIFFIO_RX_B11n,DQ7BAJ22DIFFIO_RX_B11p,DQ7BAH22DIFFIO_RX_B12n,DQSn7BAM24DIFFIO_RX_B12p,DQS7BAL24DIFFIO_RX_B13n,DQ7BAM23DIFFIO_RX_B13p,DQ7BAL23DIFFIO_RX_B14n,DQ8BAG21DIFFIO_RX_B14p,DQ8BAF21DIFFIO_RX_B15n,DQSn8BAP25DIFFIO_RX_B15p,DQS8BAN25DIFFIO_RX_B16n,DQ8BAP24DIFFIO_RX_B16p,DQ8BAN24
DIFFOUT_B21n,DQ7B AH23DIFFOUT_B21p,DQ7B AJ24DIFFOUT_B23n,DQ7B AJ23DIFFOUT_B23p,DQ7B AK22DIFFOUT_B25n,DQ7B AK24DIFFOUT_B25p,DQ7B AL25DIFFOUT_B27n,DQ8B AE22DIFFOUT_B27p,DQ8B AE21DIFFOUT_B29n,DQ8B AD21DIFFOUT_B29p,DQ8B AE20DIFFOUT_B31n,DQ8B AP26DIFFOUT_B31p,DQ8B AP23
CLK4n,DIFFIO_RX_B24nAP18CLK4p,DIFFIO_RX_B24pAN18 CLK5n,DIFFOUT_B47n AP19
CLK5p,DIFFOUT_B47p AN19
DIFFIO_RX_B17n,DQ11BAL21DIFFIO_RX_B17p,DQ11BAK21DIFFIO_RX_B18n,DQSn11BAP22DIFFIO_RX_B18p,DQS11BAN22DIFFIO_RX_B19n,DQ11BAP21DIFFIO_RX_B19p,DQ11BAN21DIFFIO_RX_B20nAM19DIFFIO_RX_B20pAL19DIFFIO_RX_B21nAF20DIFFIO_RX_B21pAF19DIFFIO_RX_B22nAH19DIFFIO_RX_B22pAG19
DIFFOUT_B33n,DQ11B AL22DIFFOUT_B33p,DQ11B AM22DIFFOUT_B35n,DQ11B AJ20DIFFOUT_B35p,DQ11B AJ21DIFFOUT_B37n,DQ11B AM21DIFFOUT_B37p,DQ11B AP20
DIFFOUT_B39n AL20DIFFOUT_B39p AM18DIFFOUT_B41n AK18DIFFOUT_B41p AL18
PLL_B1_CLKOUT0n,DIFFOUT_B45n AE18PLL_B1_CLKOUT0p,DIFFOUT_B45p AD18
PLL_B1_CLKOUT3,DIFFOUT_B43p AD19PLL_B1_CLKOUT4,DIFFOUT_B43n AE19
PLL_B1_FBn/CLKOUT2,DIFFIO_RX_B23nAK19PLL_B1_FBp/CLKOUT1,DIFFIO_RX_B23pAJ19
R134 49.9R134 49.9
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HSTCC_RDN6AHSTCC_RUP6A
HSTCB_RDN5AHSTCB_RUP5A
HSTCB_RX_p5HSTCB_RX_n5
HSTCB_RX_p1HSTCB_RX_n1HSTCB_RX_p0HSTCB_RX_n0
HSTCB_RX_p2HSTCB_RX_n2
HSTCB_RX_p3HSTCB_RX_n3
HSTCB_RX_p4HSTCB_RX_n4
HSTCB_RX_p6HSTCB_RX_n6
HSTCB_RX_p7HSTCB_RX_n7
HSTCB_RX_p8HSTCB_RX_n8
HSTCB_RUP5AHSTCB_RDN5A
HSTCB_TX_n6HSTCB_TX_p6HSTCB_TX_n7HSTCB_TX_p7HSTCB_TX_n8HSTCB_TX_p8
HSTCB_TX_n5HSTCB_TX_p5
HSTCB_TX_n0HSTCB_TX_p0HSTCB_TX_n1HSTCB_TX_p1HSTCB_TX_n2HSTCB_TX_p2HSTCB_TX_n3HSTCB_TX_p3HSTCB_TX_n4HSTCB_TX_p4
LEDB0LEDB1LEDB2LEDB3
HSTCC_RDN6AHSTCC_RUP6A
HSTCC_RX_p4HSTCC_RX_n4
HSTCC_RX_p5HSTCC_RX_n5
HSTCC_RX_p6HSTCC_RX_n6
HSTCC_RX_p0HSTCC_RX_n0
HSTCC_RX_p7HSTCC_RX_n7
HSTCC_RX_p1HSTCC_RX_n1
HSTCC_RX_p8HSTCC_RX_n8
HSTCC_RX_p2HSTCC_RX_n2
HSTCC_RX_p3HSTCC_RX_n3
HSTCC_TX_p4HSTCC_TX_n4
HSTCC_TX_p5HSTCC_TX_n5
HSTCC_TX_p6HSTCC_TX_n6
HSTCC_TX_n0HSTCC_TX_p0
HSTCC_TX_p7HSTCC_TX_n7
HSTCC_TX_n1HSTCC_TX_p1
HSTCC_TX_p8HSTCC_TX_n8
HSTCC_TX_p2HSTCC_TX_n2
HSTCC_TX_p3HSTCC_TX_n3
DIP_SW3
DIP_SW4DIP_SW5
DIP_SW7DIP_SW6
DIP_SW2
HEX0_D3
HEX0_D6HEX0_D4
HEX0_D2
HEX0_D1HEX0_D0HEX0_D5
SW0SW1
SW2
SW3
LEDR7
LEDR3
LEDR0LEDR4
LEDR5LEDR6
LEDR1
LEDR2
LEDG0LEDG1
LEDG2LEDG3
LEDG4
LEDG5
LEDG6
LEDG7
LEDB4LEDB5
LEDB6LEDB7
HEX1_D0
HEX1_D1HEX1_D2
HEX1_D3
HEX1_D6
HEX1_D4
HEX1_D5
Button0
Button2Button3Button1
DIP_SW0DIP_SW1
HSTCB_RX_p[0..8]HSTCB_TX_n[0..8]HSTCB_TX_p[0..8]
HSTCB_RX_n[0..8]
HEX0_DPHEX1_DP
OSC2_50
HSTCB_CLKIN_p0HSTCB_CLKIN_n0
LEDR[0..7]LEDG[0..7]LEDB[0..7]HEX0_D[0..6]HEX1_D[0..6]Button[0..3]SW[0..3]DIP_SW[0..7]
CLK_OUT
HSTCB_CLKOUT_2
HSTCC_RX_p[0..8]HSTCC_TX_n[0..8]HSTCC_TX_p[0..8]
HSTCC_RX_n[0..8]
HSTCC_CLKIN_n0HSTCC_CLKIN_p0
EXT_CLK
HSTCC_CLKOUT_2
SD_DAT0
SD_DAT3SD_CMDSD_DAT2
SD_DAT1
SD_CLK
SD_WPn
HSTCC_SDAHSTCC_SCL
HSTCB_SDAHSTCB_SCL
BC_VCCIOBB_VCCIO
TEMP_DATATEMP_CLK
TEMP_INTn
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
EP2C70 BANK5 AND BANK 6 1.1
DE3 Base BoardB
19 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
EP2C70 BANK5 AND BANK 6 1.1
DE3 Base BoardB
19 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
EP2C70 BANK5 AND BANK 6 1.1
DE3 Base BoardB
19 32Thursday, September 04, 2008
R137 49.9R137 49.9R138 49.9R138 49.9 R139 49.9R139 49.9R140 49.9R140 49.9
Bank 5A
Bank 5C
U3E
EP3SL150F1152
Bank 5A
Bank 5C
U3E
EP3SL150F1152
DIFFIO_RX_R1n,RDN5AAK3DIFFIO_RX_R1p,RUP5AAK4DIFFIO_RX_R2n,DQ1RAM1DIFFIO_RX_R2p,DQ1RAM2DIFFIO_RX_R3n,DQSN1RAJ3DIFFIO_RX_R3p,DQS1RAJ4DIFFIO_RX_R4n,DQ1RAL1DIFFIO_RX_R4p,DQ1RAL2DIFFIO_RX_R5n,DQ2RAG3DIFFIO_RX_R5p,DQ2RAG4DIFFIO_RX_R6n,DQSn2RAK1DIFFIO_RX_R6p,DQS2RAJ2DIFFIO_RX_R7n,DQ2RAJ1DIFFIO_RX_R7p,DQ2RAH2DIFFIO_RX_R8n,DQ3RAF3DIFFIO_RX_R8p,DQ3RAF4DIFFIO_RX_R9n,DQSn3RAH1DIFFIO_RX_R9p,DQS3RAG1DIFFIO_RX_R10n,DQ3RAF1DIFFIO_RX_R10p,DQ3RAF2DIFFIO_RX_R11nAE3DIFFIO_RX_R11pAE4DIFFIO_RX_R12nAE1DIFFIO_RX_R12pAE2
DIFFIO_TX_R1n AH4DIFFIO_TX_R1p AH5
DIFFIO_TX_R2n,DQ1R AE7DIFFIO_TX_R2p,DQ1R AE8DIFFIO_TX_R3n,DQ1R AF5DIFFIO_TX_R3p,DQ1R AF6DIFFIO_TX_R4n,DQ1R AC8DIFFIO_TX_R4p,DQ1R AC9DIFFIO_TX_R5n,DQ2R AE5DIFFIO_TX_R5p,DQ2R AE6DIFFIO_TX_R6n,DQ2R AB10DIFFIO_TX_R6p,DQ2R AC11DIFFIO_TX_R7n,DQ2R AD6DIFFIO_TX_R7p,DQ2R AD7DIFFIO_TX_R8n,DQ3R AC7DIFFIO_TX_R8p,DQ3R AB8DIFFIO_TX_R9n,DQ3R AB9DIFFIO_TX_R9p,DQ3R AA10
DIFFIO_TX_R10n,DQ3R AC5DIFFIO_TX_R10p,DQ3R AC6
DIFFIO_TX_R11n AB11DIFFIO_TX_R11p AA12DIFFIO_TX_R12n AD3DIFFIO_TX_R12p AD4
CLK9n,DIFFIO_RX_R22nU3CLK9p,DIFFIO_RX_R22pU4
DIFFIO_RX_R13n,DQ8RAB3DIFFIO_RX_R13p,DQ8RAC4DIFFIO_RX_R14n,DQSn8RAD1DIFFIO_RX_R14p,DQS8RAC2DIFFIO_RX_R15n,DQ8RAA3DIFFIO_RX_R15p,DQ8RAB4DIFFIO_RX_R16n,DQ9RAC1DIFFIO_RX_R16p,DQ9RAB2DIFFIO_RX_R17n,DQSn9RY3DIFFIO_RX_R17p,DQS9RAA4DIFFIO_RX_R18n,DQ9RAB1DIFFIO_RX_R18p,DQ9RAA1DIFFIO_RX_R19n,DQ10RW3DIFFIO_RX_R19p,DQ10RY4DIFFIO_RX_R20n,DQSn10RY1DIFFIO_RX_R20p,DQS10RY2DIFFIO_RX_R21n,DQ10RV3DIFFIO_RX_R21p,DQ10RV4
DIFFIO_TX_R13n,DQ8R AB5DIFFIO_TX_R13p,DQ8R AB6DIFFIO_TX_R14n,DQ8R AA6DIFFIO_TX_R14p,DQ8R AA7DIFFIO_TX_R15n,DQ8R Y9DIFFIO_TX_R15p,DQ8R Y10DIFFIO_TX_R16n,DQ9R Y7DIFFIO_TX_R16p,DQ9R Y8DIFFIO_TX_R17n,DQ9R Y11DIFFIO_TX_R17p,DQ9R W12DIFFIO_TX_R18n,DQ9R Y5DIFFIO_TX_R18p,DQ9R Y6
DIFFIO_TX_R19n,DQ10R W7DIFFIO_TX_R19p,DQ10R W8DIFFIO_TX_R20n,DQ10R W10DIFFIO_TX_R20p,DQ10R W11DIFFIO_TX_R21n,DQ10R W5DIFFIO_TX_R21p,DQ10R W6
PLL_R3_CLKOUT0n,DIFFIO_TX_R22n W9PLL_R3_FB_CLKOUT0p,DIFFIO_TX_R22p V10
CLK8nW1CLK8pW2
Bank 6A
Bank 6C
U3F
EP3SL150F1152
Bank 6A
Bank 6C
U3F
EP3SL150F1152
DIFFIO_RX_R33nJ1DIFFIO_RX_R33pH2
DIFFIO_RX_R34nK3DIFFIO_RX_R34pK4
DIFFIO_RX_R35n,DQ24RH1DIFFIO_RX_R35p,DQ24RG2
DIFFIO_RX_R36n,DQSn24RJ3DIFFIO_RX_R36P,DQS24RJ4
DIFFIO_RX_R37n,DQ24RG1DIFFIO_RX_R37p,DQ24RF1
DIFFIO_RX_R38n,DQ25RH3DIFFIO_RX_R38p,DQ25RH4
DIFFIO_RX_R39n,DQSn25RE1DIFFIO_RX_R39p,DQS25RE2
DIFFIO_RX_R40n,DQ25RF3DIFFIO_RX_R40p,DQ25RF4
DIFFIO_RX_R41n,DQ26RG4DIFFIO_RX_R41p,DQ26RG5
DIFFIO_RX_R42n,DQSn26RD1DIFFIO_RX_R42p,DQS26RC1
DIFFIO_RX_R43n,DQ26RD2DIFFIO_RX_R43p,DQ26RD3
DIFFIO_RX_R44n,RDN6AE3DIFFIO_RX_R44p,RUP6AE4
DIFFIO_TX_R33n P10DIFFIO_TX_R33p P11
DIFFIO_TX_R34n M6DIFFIO_TX_R34p M7
DIFFIO_TX_R35n,DQ24R L4DIFFIO_TX_R35p,DQ24R L5
DIFFIO_TX_R36n,DQ24R L6DIFFIO_TX_R36p,DQ24R L7
DIFFIO_TX_R37n,DQ24R N8DIFFIO_TX_R37p,DQ24R N9
DIFFIO_TX_R38n,DQ25R K5DIFFIO_TX_R38p,DQ25R K6
DIFFIO_TX_R39n,DQ25R N10DIFFIO_TX_R39p,DQ25R N11
DIFFIO_TX_R40n,DQ25R J6DIFFIO_TX_R40p,DQ25R J7
DIFFIO_TX_R41n,DQ26R K7DIFFIO_TX_R41p,DQ26R K8
DIFFIO_TX_R42n,DQ26R M9DIFFIO_TX_R42p,DQ26R M10
DIFFIO_TX_R43n,DQ26R L8DIFFIO_TX_R43p,DQ26R L9
DIFFIO_TX_R44n H5DIFFIO_TX_R44p H6
CLK11n,DIFFIO_RX_R23nT1CLK11p,DIFFIO_RX_R23pT2
DIFFIO_RX_R24n,DQ17RR1DIFFIO_RX_R24p,DQ17RP2
DIFFIO_RX_R25n,DQSn17RR3DIFFIO_RX_R25p,DQS17RR4
DIFFIO_RX_R26n,DQ17RP1DIFFIO_RX_R26p,DQ17RN2
DIFFIO_RX_R27n,DQ18RP3DIFFIO_RX_R27p,DQ18RP4
DIFFIO_RX_R28n,DQSn18RN1DIFFIO_RX_R28p,DQS18RM1
DIFFIO_RX_R29n,DQ18RN3DIFFIO_RX_R29p,DQ18RN4
DIFFIO_RX_R30n,DQ19RL1DIFFIO_RX_R30p,DQ19RL2
DIFFIO_RX_R31n,DQSn19RM3DIFFIO_RX_R31p,DQS19RM4
DIFFIO_RX_R32n,DQ19RK1DIFFIO_RX_R32p,DQ19RK2
DIFFIO_TX_R24n,DQ17R U6DIFFIO_TX_R24p,DQ17R T7
DIFFIO_TX_R25n,DQ17R T8DIFFIO_TX_R25p,DQ17R T9
DIFFIO_TX_R26n,DQ17R T4DIFFIO_TX_R26p,DQ17R T5
DIFFIO_TX_R27n,DQ18R R6DIFFIO_TX_R27p,DQ18R R7
DIFFIO_TX_R28n,DQ18R P5DIFFIO_TX_R28p,DQ18R P6
DIFFIO_TX_R29n,DQ18R T11DIFFIO_TX_R29p,DQ18R R12
DIFFIO_TX_R30n,DQ19R R9DIFFIO_TX_R30p,DQ19R R10
DIFFIO_TX_R31n,DQ19R P7DIFFIO_TX_R31p,DQ19R P8
DIFFIO_TX_R32n,DQ19R N5DIFFIO_TX_R32p,DQ19R N6
PLL_R2_CLKOUT0n,DIFFIO_TX_R23n U10PLL_R2_FB_CLKOUT0p,DIFFIO_TX_R23p U11
CLK10nU1CLK10pU2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HSTCC_RDN7AHSTCC_RUP7A
HSTCD_RDN8AHSTCD_RUP8A
HSTCC_RX_n29HSTCC_RX_p29
HSTCC_RX_n15HSTCC_RX_p15
HSTCC_RX_p22HSTCC_RX_n22
HSTCC_RX_p16HSTCC_RX_n16
HSTCC_RX_p23HSTCC_RX_n23
HSTCC_RX_p17HSTCC_RX_n17
HSTCC_RX_p24HSTCC_RX_n24
HSTCC_RX_p18HSTCC_RX_n18
HSTCC_RX_p28HSTCC_RX_n28
HSTCC_RX_p25HSTCC_RX_n25
HSTCC_RX_p10HSTCC_RX_n10HSTCC_RX_p11HSTCC_RX_n11
HSTCC_RX_p12HSTCC_RX_n12
HSTCC_RX_p9HSTCC_RX_n9
HSTCC_RX_p19HSTCC_RX_n19
HSTCC_RX_p26HSTCC_RX_n26
HSTCC_RX_p13HSTCC_RX_n13
HSTCC_RX_p20HSTCC_RX_n20
HSTCC_RX_p27HSTCC_RX_n27
HSTCC_RX_p14HSTCC_RX_n14
HSTCC_RX_p21HSTCC_RX_n21
HSTCC_RDN7AHSTCC_RUP7A
HSTCC_TX_p16HSTCC_TX_n16
HSTCC_TX_p23HSTCC_TX_n23
HSTCC_TX_p10HSTCC_TX_n10
HSTCC_TX_p17HSTCC_TX_n17
HSTCC_TX_p24HSTCC_TX_n24
HSTCC_CLKOUT_n1HSTCC_CLKOUT_p1
HSTCC_CLKOUT_n0HSTCC_CLKOUT_p0
HSTCC_TX_p11HSTCC_TX_n11
HSTCC_TX_p18HSTCC_TX_n18
HSTCC_TX_p29HSTCC_TX_n29HSTCC_TX_p28HSTCC_TX_n28
HSTCC_TX_p25HSTCC_TX_n25
HSTCC_TX_p12HSTCC_TX_n12
HSTCC_TX_p19HSTCC_TX_n19
HSTCC_TX_p26HSTCC_TX_n26
HSTCC_TX_p13HSTCC_TX_n13
HSTCC_TX_p20HSTCC_TX_n20
HSTCC_TX_p27HSTCC_TX_n27
HSTCC_TX_p14HSTCC_TX_n14
HSTCC_TX_p21HSTCC_TX_n21
HSTCC_TX_n15HSTCC_TX_p15
HSTCC_TX_p22HSTCC_TX_n22
HSTCC_TX_p9HSTCC_TX_n9
HSTCD_RX_p28HSTCD_RX_n28
HSTCD_RX_p27HSTCD_RX_n27
HSTCD_RX_p21HSTCD_RX_n21
HSTCD_RX_n29HSTCD_RX_p29
HSTCD_RX_p22HSTCD_RX_n22
HSTCD_RX_p11HSTCD_RX_n11
HSTCD_RX_p10HSTCD_RX_n10
HSTCD_RX_p9HSTCD_RX_n9
HSTCD_RX_p23HSTCD_RX_n23
HSTCD_RX_n16HSTCD_RX_p16
HSTCD_RX_p13HSTCD_RX_n13
HSTCD_RX_p12HSTCD_RX_n12
HSTCD_RX_p14HSTCD_RX_n14HSTCD_RX_p15HSTCD_RX_n15
HSTCD_RX_p17HSTCD_RX_n17
HSTCD_RX_p24HSTCD_RX_n24
HSTCD_RX_p18HSTCD_RX_n18
HSTCD_RDN8AHSTCD_RUP8A
HSTCD_RX_p25HSTCD_RX_n25
HSTCD_RX_p19HSTCD_RX_n19
HSTCD_RX_p26HSTCD_RX_n26
HSTCD_RX_p20HSTCD_RX_n20
HSTCD_TX_p23HSTCD_TX_n23
HSTCD_TX_p17HSTCD_TX_n17
HSTCD_TX_p15HSTCD_TX_n15HSTCD_TX_p16HSTCD_TX_n16
HSTCD_TX_p24HSTCD_TX_n24
HSTCD_CLKOUT_n1HSTCD_CLKOUT_p1
HSTCD_TX_p18HSTCD_TX_n18
HSTCD_TX_p25HSTCD_TX_n25
HSTCD_TX_p19HSTCD_TX_n19
HSTCD_TX_p26HSTCD_TX_n26
HSTCD_TX_n10HSTCD_TX_p10HSTCD_TX_n9HSTCD_TX_p9
HSTCD_TX_p20HSTCD_TX_n20
HSTCD_TX_p27HSTCD_TX_n27
HSTCD_TX_p28HSTCD_TX_n28
HSTCD_TX_p29HSTCD_TX_n29
HSTCD_TX_p11HSTCD_TX_n11
HSTCD_TX_p21HSTCD_TX_n21
HSTCD_CLKOUT_n0HSTCD_CLKOUT_p0
HSTCD_TX_p22HSTCD_TX_n22
HSTCD_TX_n13HSTCD_TX_p13
HSTCD_TX_n14HSTCD_TX_p14
HSTCD_TX_n12HSTCD_TX_p12
HSTCC_CLKOUT_p[0..1]HSTCC_CLKOUT_n[0..1]
HSTCC_RX_p[9..29]HSTCC_TX_n[9..29]HSTCC_TX_p[9..29]
HSTCC_RX_n[9..29]
HSTCC_CLKIN_2OSC_BC HSTCC_CLKIN_p1
HSTCC_CLKIN_n1
HSTCD_CLKOUT_p[0..1]HSTCD_CLKOUT_n[0..1]
HSTCD_RX_p[9..29]HSTCD_TX_n[9..29]HSTCD_TX_p[9..29]
HSTCD_RX_n[9..29]
HSTCD_CLKIN_2OSC_BD
HSTCD_CLKIN_n1HSTCD_CLKIN_p1
BC_VCCIOBD_VCCIO
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
EP2C70 BANK7 AND BANK 8 1.1
DE3 Base BoardB
20 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
EP2C70 BANK7 AND BANK 8 1.1
DE3 Base BoardB
20 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
EP2C70 BANK7 AND BANK 8 1.1
DE3 Base BoardB
20 32Thursday, September 04, 2008
R141 49.9R141 49.9
Bank 8B
Bank 8C
Bank 8A
U3H
EP3SL150F1152
Bank 8B
Bank 8C
Bank 8A
U3H
EP3SL150F1152
DIFFIO_RX_T39nL23DIFFIO_RX_T39pM23
DIFFIO_RX_T40n,DQ24TF23DIFFIO_RX_T40p,DQ24TG23
DIFFIO_RX_T41n,DQSn24TF24DIFFIO_RX_T41p,DQS24TG24
DIFFIO_RX_T42n,DQ24TD26DIFFIO_RX_T42p,DQ24TE26
DIFFIO_RX_T43n,DQ25TA31DIFFIO_RX_T43p,DQ25TB31
DIFFIO_RX_T44n,DQSn25TA32DIFFIO_RX_T44p,DQS25TB32
DIFFIO_RX_T45n,DQ25TC30DIFFIO_RX_T45p,DQ25TD30
DIFFIO_RX_T46n,DQ26TE28DIFFIO_RX_T46p,DQ26TF28
DIFFIO_RX_T47n,DQSn26TE29DIFFIO_RX_T47p,DQS26TF29
DIFFIO_RX_T48n,RDN8AG26DIFFIO_RX_T48p,RUP8AH26
DIFFOUT_T78n K23DIFFOUT_T78p L22
DIFFOUT_T80n,DQ24T H23DIFFOUT_T80p,DQ24T F22
DIFFOUT_T82n,DQ24T D27DIFFOUT_T82p,DQ24T F25
DIFFOUT_T84n,DQ24T D28DIFFOUT_T84p,DQ24T F26
DIFFOUT_T86n,DQ25T A33DIFFOUT_T86p,DQ25T A30
DIFFOUT_T88n,DQ25T B29DIFFOUT_T88p,DQ25T C29
DIFFOUT_T90n,DQ25T D31DIFFOUT_T90p,DQ25T C31
DIFFOUT_T92n,DQ26T G27DIFFOUT_T92p,DQ26T F27
DIFFOUT_T94n,DQ26T K24DIFFOUT_T94p,DQ26T J24
DIFFOUT_T96n,DQ26T K25DIFFOUT_T96p,DQ26T J25
DIFFIO_RX_T33n,DQ19TA25DIFFIO_RX_T33p,DQ19TB25
DIFFIO_RX_T34n,DQSn19TB26DIFFIO_RX_T34p,DQS19TC26
DIFFIO_RX_T35n,DQ19TJ21DIFFIO_RX_T35p,DQ19TJ22
DIFFIO_RX_T36n,DQ20TD24DIFFIO_RX_T36p,DQ20TD25
DIFFIO_RX_T37n,DQSn20TD23DIFFIO_RX_T37p,DQS20TE23
DIFFIO_RX_T38n,DQ20TA28DIFFIO_RX_T38p,DQ20TB28
DIFFOUT_T66n,DQ19T A26DIFFOUT_T66p,DQ19T A24
DIFFOUT_T68n,DQ19T J20DIFFOUT_T68p,DQ19T K20
DIFFOUT_T70n,DQ19T K22DIFFOUT_T70p,DQ19T K21
DIFFOUT_T72n,DQ20T E25DIFFOUT_T72p,DQ20T C24
DIFFOUT_T74n,DQ20T C27DIFFOUT_T74p,DQ20T A27
DIFFOUT_T76n,DQ20T A29DIFFOUT_T76p,DQ20T C28
CLK14n,DIFFIO_RX_T25nA19CLK14p,DIFFIO_RX_T25pB19 CLK15n,DIFFOUT_T50n A20
CLK15p,DIFFOUT_T50p B20
DIFFIO_RX_T27nC19DIFFIO_RX_T27pD19
DIFFIO_RX_T28nE19DIFFIO_RX_T28pF19
DIFFIO_RX_T29nC21DIFFIO_RX_T29pD21
DIFFIO_RX_T30n,DQ16TF20DIFFIO_RX_T30p,DQ16TG20
DIFFIO_RX_T31n,DQSn16TF21DIFFIO_RX_T31p,DQS16TG21
DIFFIO_RX_T32n,DQ16TA23DIFFIO_RX_T32p,DQ16TB23
DIFFOUT_T56n D20DIFFOUT_T56p C20
DIFFOUT_T58n E22DIFFOUT_T58p D22
DIFFOUT_T60n,DQ16T H20DIFFOUT_T60p,DQ16T E20
DIFFOUT_T62n,DQ16T A21DIFFOUT_T62p,DQ16T A22
DIFFOUT_T64n,DQ16T C23DIFFOUT_T64p,DQ16T B22
PLL_T1_CLKOUT0n,DIFFOUT_T52n J19PLL_T1_CLKOUT0p,DIFFOUT_T52p K19
PLL_T1_CLKOUT3,DIFFOUT_T54p L19PLL_T1_CLKOUT4,DIFFOUT_T54n L20
PLL_T1_FBn/CLKOUT2,DIFFIO_RX_T26nC18PLL_T1_FBp/CLKOUT1,DIFFIO_RX_T26pD18
R144 49.9R144 49.9R143 49.9R143 49.9
Bank 7B
Bank 7C
Bank 7A
U3G
EP3SL150F1152
Bank 7B
Bank 7C
Bank 7A
U3G
EP3SL150F1152
DIFFIO_RX_T1n,RDN7AE7DIFFIO_RX_T1p,RUP7AF7DIFFIO_RX_T2n,DQSn1TC3DIFFIO_RX_T2p,DQS1TC4DIFFIO_RX_T3n,DQ1TB5DIFFIO_RX_T3p,DQ1TC5DIFFIO_RX_T4n,DQ2TG11DIFFIO_RX_T4p,DQ2TH11DIFFIO_RX_T5n,DQSn2TA2DIFFIO_RX_T5p,DQS2TB2DIFFIO_RX_T6n,DQ2TA4DIFFIO_RX_T6p,DQ2TB4DIFFIO_RX_T7n,DQ3TC9DIFFIO_RX_T7p,DQ3TD9DIFFIO_RX_T8n,DQSn3TA7DIFFIO_RX_T8p,DQS3TB7DIFFIO_RX_T9n,DQ3TA8DIFFIO_RX_T9p,DQ3TB8DIFFIO_RX_T10nK11DIFFIO_RX_T10pK12
DIFFOUT_T1n,DQ1T F8DIFFOUT_T1p,DQ1T F6DIFFOUT_T3n,DQ1T F9DIFFOUT_T3p,DQ1T G8DIFFOUT_T5n,DQ1T C6DIFFOUT_T5p,DQ1T D6DIFFOUT_T7n,DQ2T J11DIFFOUT_T7p,DQ2T G9DIFFOUT_T9n,DQ2T J12DIFFOUT_T9p,DQ2T G10
DIFFOUT_T11n,DQ2T A5DIFFOUT_T11p,DQ2T A3DIFFOUT_T13n,DQ3T D7DIFFOUT_T13p,DQ3T E8DIFFOUT_T15n,DQ3T E10DIFFOUT_T15p,DQ3T D8DIFFOUT_T17n,DQ3T A6DIFFOUT_T17p,DQ3T C7
DIFFOUT_T19n M13DIFFOUT_T19p L13
DIFFIO_RX_T11n,DQ7TF12DIFFIO_RX_T11p,DQ7TF13DIFFIO_RX_T12n,DQSn7TC11DIFFIO_RX_T12p,DQS7TD11DIFFIO_RX_T13n,DQ7TC12DIFFIO_RX_T13p,DQ7TD12DIFFIO_RX_T14n,DQ8TH14DIFFIO_RX_T14p,DQ8TJ14DIFFIO_RX_T15n,DQSn8TA10DIFFIO_RX_T15p,DQS8TB10DIFFIO_RX_T16n,DQ8TA11DIFFIO_RX_T16p,DQ8TB11
DIFFOUT_T21n,DQ7T G12DIFFOUT_T21p,DQ7T F11DIFFOUT_T23n,DQ7T G13DIFFOUT_T23p,DQ7T E11DIFFOUT_T25n,DQ7T D13DIFFOUT_T25p,DQ7T D10DIFFOUT_T27n,DQ8T K14DIFFOUT_T27p,DQ8T K13DIFFOUT_T29n,DQ8T K15DIFFOUT_T29p,DQ8T L14DIFFOUT_T31n,DQ8T A12DIFFOUT_T31p,DQ8T A9
CLK12n,DIFFIO_RX_T24nA17CLK12p,DIFFIO_RX_T24pB17 CLK13n,DIFFOUT_T47n A16
CLK13p,DIFFOUT_T47p B16
DIFFIO_RX_T17n,DQ11TE14DIFFIO_RX_T17p,DQ11TF14DIFFIO_RX_T18n,DQSn11TA13DIFFIO_RX_T18p,DQS11TB13DIFFIO_RX_T19n,DQ11TA14DIFFIO_RX_T19p,DQ11TB14DIFFIO_RX_T20nC16DIFFIO_RX_T20pD16DIFFIO_RX_T21nJ16DIFFIO_RX_T21pJ15DIFFIO_RX_T22nG16DIFFIO_RX_T22pH16
DIFFOUT_T33n,DQ11T D14DIFFOUT_T33p/DQ11T E13DIFFOUT_T35n,DQ11T F15DIFFOUT_T35p,DQ11T D15DIFFOUT_T37n/DQ11T A15DIFFOUT_T37p,DQ11T C14
DIFFOUT_T39n C17DIFFOUT_T39p C15DIFFOUT_T41n D17DIFFOUT_T41p E17
PLL_T2_CLKOUT0n,DIFFOUT_T45n K17PLL_T2_CLKOUT0p,DIFFOUT_T45p L17
PLL_T2_CLKOUT3,DIFFOUT_T43p K16PLL_T2_CLKOUT4,DIFFOUT_T43n L16
PLL_T2_FBn/CLKOUT2,DIFFIO_RX_T23nE16PLL_T2_FBp/CLKOUT1,DIFFIO_RX_T23pF16
R142 49.9R142 49.9
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MSEL1MSEL2
MSEL0MSEL1MSEL2
MSEL0
ASDOnCSODCLK
ASDOnCSO
DCLK
nSTATUSCONF_DONE
nCE
nCE
PORSELnIO_PULLUP
PORSEL
CONF_DONE
TEMPDIODEnTEMPDIODEp
nSTATUS
TEMP_DATATEMP_CLK
TEMPDIODEnTEMPDIODEp
TEMP_OVERn
TEMP_INTnTEMP_OVERn
TEMP_OVERn
Stratix3_TCKStratix3_TMSStratix3_TDIStratix3_TDO
Stratix3_TCK
Stratix3_TMSStratix3_TDIStratix3_TCK
Stratix3_TMS
Stratix3_TDIStratix3_TDO
CONF_DONE
nCONFIG
nIO_PULLUP
FPGA_TDO
nCONFIG FPGA_TCK
FPGA_TDIFPGA_TMS
VREF1C
BA_VREFBA_VCCIO BB_VCCIO BC_VCCIO BD_VCCIO
BB_VREF BD_VREFBC_VREF
VCC33
VCC33
VCCL
VCC11
BA_VCCPD
BB_VCCPD
BC_VCCPD
BD_VCCPD
VCC11T
VCC11B
VCC11L
VCC11R
VCC11TVCC11BVCC11LVCC11R
VCC11
VCCL
VCCPT_25
VCLKIN_25
VCCA_25
VCCA_25
VCCPT_25 VCLKIN_25
VCCBAT_25
VCCBAT_25
VCC11T VCC11B VCC11RVCC11L
VCCL
VCCL
VCCL
VCC11
VCC11
BA_VREF BB_VREF BD_VREFBC_VREF
BA_VCCIO
BB_VCCIO BC_VCCIO
BD_VCCIO VCC33
VCCPT_25 VCCA_25
VCCPT_25
BA_VCCIO BC_VCCIOBD_VCCIOVCC33 VCC33 VCC33 VCC33
BD_VCCPDVCC33
BD_VREF
VREF2C
VREF5C
VREF6C
VREF6CVREF1C VREF2C VREF5C
VCC33
VCC33
VCC33
BD_VCCPDBD_VCCPD
VCC33 BD_VCCPD
BD_VCCPD
VCC33
12V
VCC33
VCC33
VCLKIN_25
VCCBAT_25
BA_VCCPD BB_VCCPD BD_VCCPDBC_VCCPD VCC33
BA_VCCPD
VCC33
VCC33
VCC33
TEMP_DATATEMP_CLK
TEMP_INTn
DATA
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
EP3SL150 POWER, CONFIG and Configuration Devices 1.1
DE3 Base BoardC
21 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
EP3SL150 POWER, CONFIG and Configuration Devices 1.1
DE3 Base BoardC
21 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
EP3SL150 POWER, CONFIG and Configuration Devices 1.1
DE3 Base BoardC
21 32Thursday, September 04, 2008
R165 10KR165 10K
BC97
0.1u
BC97
0.1u
C50
10u
C50
10u
BC112
0.1u
BC112
0.1u
VCCAVCCB
ENGND
U6
TXB0104PWR
VCCAVCCB
ENGND
U6
TXB0104PWR
45
213121110
14
7 8
1
3
BC79
0.1u
BC79
0.1u
C49
100u
C49
100u
C65
1u
C65
1u
BC105
0.1u
BC105
0.1u
BC90
0.1u
BC90
0.1u
BC111
0.1u
BC111
0.1u
BC100
0.1u
BC100
0.1u
R153 10KR153 10K
CONF_DONE
LEDB
CONF_DONE
LEDB
BC50
0.1u
BC50
0.1u
BC45
0.1u
BC45
0.1u
Q4
FDV305N
Q4
FDV305N1
23
BC73
0.1u
BC73
0.1u
C61
1u
C61
1u
BC81
0.1u
BC81
0.1u
BC102
0.1u
BC102
0.1u
R163 10KR163 10K
BC41
0.1u
BC41
0.1u
R145 0R145 0
BC74
0.1u
BC74
0.1u
BC106
0.1u
BC106
0.1u
R162 10KR162 10K
BC86
0.1u
BC86
0.1u
BC70
0.1u
BC70
0.1u
BC42
0.1u
BC42
0.1u
BC104
0.1u
BC104
0.1u
BC68
0.1u
BC68
0.1u
R156 DNIR156 DNI
BC120
0.1u
BC120
0.1u
R166 200R166 200
L4 BEADL4 BEAD
R151 10KR151 10K
BC78
0.1u
BC78
0.1u
BC94
0.1u
BC94
0.1u
BC40
0.1u
BC40
0.1u
BC54
0.1u
BC54
0.1u
VCC
GND
U32
74HC1G04
VCC
GND
U32
74HC1G04
2 345
R167
120
R167
120
C53
10u
C53
10u
BC117
0.1u
BC117
0.1u
BC67
0.1u
BC67
0.1u
C63
1u
C63
1u
L6 BEADL6 BEAD
BC119
0.1u
BC119
0.1u
C60
1u
C60
1u
C56
1u
C56
1u
C67
1u
C67
1u
BC51
0.1u
BC51
0.1u
R155 1KR155 1K
R154 10KR154 10K
BC92
0.1u
BC92
0.1u
BC53
0.1u
BC53
0.1u
BC89
0.1u
BC89
0.1u
BC47
0.1u
BC47
0.1u
BC95
0.1u
BC95
0.1u
BC99
0.1u
BC99
0.1u
BC88
0.1u
BC88
0.1u
BC96
0.1u
BC96
0.1u
R164 10KR164 10K
BC57
0.1u
BC57
0.1u
BC63
0.1u
BC63
0.1u
C48
100u
C48
100u
C46
100u
C46
100u
C69 DNIC69 DNI
L7 BEADL7 BEAD
BC80
0.1u
BC80
0.1u
R146 1KR146 1K
BC77
0.1u
BC77
0.1u
BC44
0.1u
BC44
0.1u
BC114
0.1u
BC114
0.1u
BC43
0.1u
BC43
0.1u
BC36
0.1u
BC36
0.1u
L5 BEADL5 BEAD
C68 DNIC68 DNI
C51
10u
C51
10u
R246 120R246 120
BC72
0.1u
BC72
0.1u
BC58
0.1u
BC58
0.1u
BC98
0.1u
BC98
0.1u
R150 10KR150 10K
BC85
0.1u
BC85
0.1u
BC48
0.1u
BC48
0.1u
1.2, 1.5, 1.8, 2.0, 2.5, 3.0, 3.3V1.8, 2.5, 3.0, 3.3V
2.5, 3.0, 3.3V
Analog 2.5V
2.5V
2.5V
Power & GroundAnalog 2.5V
Bank I/O reference voltage
1.1V
1.1V
0.9 or 1.1V
U3J
EP3SL150F1152
1.2, 1.5, 1.8, 2.0, 2.5, 3.0, 3.3V1.8, 2.5, 3.0, 3.3V
2.5, 3.0, 3.3V
Analog 2.5V
2.5V
2.5V
Power & GroundAnalog 2.5V
Bank I/O reference voltage
1.1V
1.1V
0.9 or 1.1V
U3J
EP3SL150F1152
VCC AB16VCC AB18VCC AB20
VCC N15VCC N17VCC N19VCC R13VCC T22VCC U13VCC V22VCC W13VCC Y22
VCC_CLKIN3CAG18VCC_CLKIN4CAE17VCC_CLKIN7CH17VCC_CLKIN8CK18
VCCA_PLL_B1AH18 VCCA_PLL_B2AH17 VCCA_PLL_L2U28 VCCA_PLL_L3V28 VCCA_PLL_R2U7 VCCA_PLL_R3V7
VCCA_PLL_T1G18 VCCA_PLL_T2G17
VCCBATG6
VCCD_PLL_B1 AF18VCCD_PLL_B2 AF17VCCD_PLL_L2 U26VCCD_PLL_L3 V26VCCD_PLL_R2 U9VCCD_PLL_R3 V9
VCCD_PLL_T1 J18VCCD_PLL_T2 J17
VC
CIO
1AB
34V
CC
IO1A
G32
VC
CIO
1AH
29V
CC
IO1A
L26
VC
CIO
1AN
28
VC
CIO
1CM
32V
CC
IO1C
T31
VC
CIO
1CU
34V
CC
IO1C
V30
VC
CIO
2AA
B28
VC
CIO
2AA
D25
VC
CIO
2AA
G28
VC
CIO
2AA
H32
VC
CIO
2AA
N34
VC
CIO
2CA
D32
VC
CIO
2CW
25V
CC
IO2C
W29
VC
CIO
2CW
32
VC
CIO
3AA
F25
VC
CIO
3AA
J25
VC
CIO
3AA
L30
VC
CIO
3AA
M27
VC
CIO
3BA
F22
VC
CIO
3BA
M25
VC
CIO
3CA
H21
VC
CIO
3CA
J18
VC
CIO
3CA
M20
VC
CIO
4AA
F12
VC
CIO
4AA
H10
VC
CIO
4AA
L6V
CC
IO4A
AM
3
VC
CIO
4BA
H13
VC
CIO
4BA
M10
VC
CIO
4CA
G16
VC
CIO
4CA
M13
VC
CIO
4CA
P17
VC
CIO
5AA
B7
VC
CIO
5AA
D9
VC
CIO
5AA
G6
VC
CIO
5AA
H3
VC
CIO
5AA
N1
VC
CIO
5CA
C3
VC
CIO
5CU
5V
CC
IO5C
V1
VC
CIO
5CW
4
VC
CIO
6AB
1V
CC
IO6A
G3
VC
CIO
6AH
7V
CC
IO6A
L10
VC
CIO
6AN
7
VC
CIO
6CL3
VC
CIO
6CT1
0V
CC
IO6C
T3V
CC
IO6C
T6
VC
CIO
7AC
8V
CC
IO7A
D5
VC
CIO
7AF1
0V
CC
IO7A
J10
VC
CIO
7BC
10V
CC
IO7B
J13
VC
CIO
7CC
13V
CC
IO7C
F17
VC
CIO
7CG
14
VC
CIO
8AC
32V
CC
IO8A
D29
VC
CIO
8AG
25V
CC
IO8A
J23
VC
CIO
8BC
25V
CC
IO8B
G22
VC
CIO
8CA
18V
CC
IO8C
C22
VC
CIO
8CH
19
VCCL AA13VCCL AA15VCCL AA17VCCL AA19VCCL AA21VCCL AB14VCCL AB22
VCCL N13VCCL N21VCCL P14VCCL P16VCCL P18VCCL P20VCCL P22VCCL R15VCCL R17VCCL R19VCCL R21VCCL T14VCCL T16VCCL T18VCCL T20VCCL U15VCCL U17VCCL U19VCCL U21VCCL V14VCCL V16VCCL V18VCCL V20VCCL W15VCCL W17VCCL W19VCCL W21VCCL Y14VCCL Y16VCCL Y18VCCL Y20
VCCPD1AN23VCCPD1CR23VCCPD2AAA23VCCPD2CW23VCCPD3AAC23VCCPD3BAC21VCCPD3CAC19VCCPD4AAC13VCCPD4BAC15VCCPD4CAC17VCCPD5AAB12VCCPD5CY12VCCPD6AP12VCCPD6CT12VCCPD7AM12VCCPD7BM14VCCPD7CM16VCCPD8AM22VCCPD8BM20VCCPD8CM18
VCCPGMAD10VCCPGMAD24
VCCPTAG27VCCPTAG7
VCCPTAJ17 VCCPTF18 VCCPTH8 VCCPTJ27 VCCPTU29 VCCPTV6
VR
EF1
AJ2
6V
RE
F1C
P26
VR
EF2
AA
A26
VR
EF2
CV
27
VR
EF3
AA
G25
VR
EF3
BA
G22
VR
EF3
CA
H20
VR
EF4
AA
G10
VR
EF4
BA
G13
VR
EF4
CA
H16
VR
EF5
AA
F7V
RE
F5C
AA
9
VR
EF6
AP
9V
RE
F6C
U8
VR
EF7
AH
10V
RE
F7B
H13
VR
EF7
CG
15
VR
EF8
AH
25V
RE
F8B
H22
VR
EF8
CG
19
GN
DA
A22
GNDH27
GN
DA
G5
GN
DA
A20
GNDH9
GND AG26
GNDJ5 GNDJ2
GND AK17
GND AK2
GND AK20
GNDE9
GNDF2
GND AK29
GN
DY
27G
ND
Y30
GN
DY
33
GND AG23
GND AN14GND AN17
GNDH30GNDH33
GN
DP
30G
ND
P33
GN
DR
11G
ND
R14
GN
DR
16G
ND
R18
GND AK23GND AK26G
ND
AA
11
GN
DR
5G
ND
R8
GN
DA
A14
GN
DA
A16
GN
DA
A18
GN
DA
A2
GN
DT2
1G
ND
U12
GN
DA
A5
GN
DA
A8
GN
DA
B13
GN
DA
B15
GN
DA
B17
GN
DA
B19
GN
DA
B21
GN
DA
B23
GN
DA
C14
GN
DA
C16
GN
DA
C18
GN
DA
C20
GN
DA
C24
GN
DA
C27
GN
DA
C30
GN
DA
C33
GN
DA
D11
GN
DA
D14
GN
DA
D17
GN
DA
D2
GN
DA
D20
GN
DA
D23
GN
DA
D5
GN
DA
D8
GN
DA
F27
GN
DA
F30
GN
DA
F33
GN
DA
F9
GN
DA
G11
GN
DA
G14
GN
DA
G17
GN
DA
G2
GN
DA
G20
GN
DL3
3
GN
DM
11G
ND
M15
GN
DA
G8
GND AJ30GND AJ33
GND AK11GND AK14
GN
DM
8
GN
DN
12G
ND
N14
GN
DN
16G
ND
N18
GN
DN
20
GND AK5GND AK8
GND AM33
GND AN11
GN
DP
19G
ND
P21
GND AN2
GND AN20GND AN23GND AN26GND AN29GND AN32
GND AN5GND AN8
GNDB12GNDB15GNDB18GNDB21GNDB24GNDB27
GNDB3
GNDB30GNDB33
GNDB6GNDB9
GNDC2
GNDE12GNDE15GNDE18GNDE21GNDE24GNDE27GNDE30GNDE33
GNDE6
GN
DV
12G
ND
V13
GNDF5
GNDH12GNDH15GNDH18GNDH21GNDH24
GN
DV
5G
ND
V8
GN
DW
14G
ND
W16
GN
DW
18G
ND
W20
GNDJ8GNDL12GNDL15
GN
DL1
8G
ND
L21
GN
DL2
4G
ND
L27
GN
DL3
0
GN
DT1
7G
ND
T19
GN
DV
2
GN
DM
17G
ND
M19
GN
DM
2
GN
DM
21
GN
DM
5
GN
DU
23G
ND
U24
GN
DU
27G
ND
U30
GN
DU
33
GN
DV
11
GN
DN
22G
ND
P13
GN
DP
15G
ND
P17
GN
DV
19G
ND
V17
GN
DP
24G
ND
P27
GN
DU
14G
ND
U16
GN
DU
20G
ND
U22
GN
DT1
5
GN
DV
15
GN
DR
2
GN
DR
20G
ND
R22
GN
DY
17G
ND
Y19
GN
DT1
3
GN
DV
21G
ND
V23
GN
DY
24
GN
DY
13G
ND
W22
GN
DY
15
GN
DY
21
BC116
0.1u
BC116
0.1u
BC110
0.1u
BC110
0.1u
C55
1u
C55
1u
BC108
0.1u
BC108
0.1u
BC182
0.1u
BC182
0.1u
BC118
0.1u
BC118
0.1u
R160 1KR160 1K
BC107
0.1u
BC107
0.1u
BC71
0.1u
BC71
0.1u
BC91
0.1u
BC91
0.1u
Control Signal
U3I
EP3SL150F1152
Control Signal
U3I
EP3SL150F1152
CONF_DONEAH29
DCLKAL3
nSTATUSAH28
MSEL0 K10MSEL1 J9MSEL2 K9
nCEAE26
nCONFIGAE25
nIO_PULLUP AF8PORSEL AF26TCKF30
TDIG28TEMPDIODEn D4TEMPDIODEp E5
TMSH28TRSTJ28
ASDO AH6
DNU U18
nCEO AJ5nCSO AE9
TDOG29
BC49
0.1u
BC49
0.1u
BC84
0.1u
BC84
0.1u
R149 10KR149 10K
BC38
0.1u
BC38
0.1u
R157 1KR157 1K
JP2SIP2JP2SIP2
12
R1612.2K R1612.2K
C58
1u
C58
1u
C64
1u
C64
1u
R152 DNIR152 DNI
BC101
0.1u
BC101
0.1u
BC59
0.1u
BC59
0.1u
BC39
0.1u
BC39
0.1u
C52
10u
C52
10u
R148 10KR148 10K
BC115
0.1u
BC115
0.1u
BC1210.1uBC1210.1u
BC103
0.1u
BC103
0.1u
BC52
0.1u
BC52
0.1u
BC65
0.1u
BC65
0.1u
R159 DNIR159 DNIR158 DNIR158 DNI
L8 BEADL8 BEAD
BC62
0.1u
BC62
0.1u
C62
1u
C62
1u
BC69
0.1u
BC69
0.1u
C59
1u
C59
1u
BC83
0.1u
BC83
0.1u
C47
100u
C47
100u
BC56
0.1u
BC56
0.1u
BC60
0.1u
BC60
0.1u
BC109
0.1u
BC109
0.1u
BC61
0.1u
BC61
0.1u
BC75
0.1u
BC75
0.1u
L9 BEADL9 BEAD
C66
1u
C66
1u
BC46
0.1u
BC46
0.1u
115
91412 11
34
106
U5
MAX1619
115
91412 11
34
106
U5
MAX1619
VCC
GND
DXPDXN
ADD1 GNDGND
OVERT
ADD0
ALERTSMBDATASMBCLK
STBY
EXP
BC82
0.1u
BC82
0.1u
C57
1u
C57
1u
BC113
0.1u
BC113
0.1u
BC93
0.1u
BC93
0.1u
L10 BEADL10 BEAD
BC66
0.1u
BC66
0.1u
U4
EPCS64
U4
EPCS64
VCC1VCC2
nCS 7
DATA 8
VCC9GND10 ASDI 15
DCLK 16
BC55
0.1u
BC55
0.1u
OVT
LEDR
OVT
LEDR
BC76
0.1u
BC76
0.1u
BC87
0.1u
BC87
0.1u
BC64
0.1u
BC64
0.1u
R147 10KR147 10K
C54
1u
C54
1u
BC37
0.1u
BC37
0.1u
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
POWER_ON
BB_VREF
12V
VCC33
VCC50 VCC33VCC33
VCC33 BB_VTT
BB_VCCIO
VCC50
VCC33 VCCL
BB_VCCIO
BC_VCCIO
BA_VCCIO
BD_VCCIO
VCC25
VCCPT_25
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
POWER 1.1
DE3 Base Board
22 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
POWER 1.1
DE3 Base Board
22 32Thursday, September 04, 2008
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
POWER 1.1
DE3 Base Board
22 32Thursday, September 04, 2008
Power Input
LTM4601
LTM4604
LTC3026
LT1963A
C102
10u
C102
10u
BC132
0.1u
BC132
0.1u
2567
834
LP2996
REG102567
834
LP2996
REG10
SDVSENSE
VREFVDDQAVINPVIN
VTTGNDGND
3
4
1
5
2
6
SW5
SW-PUSH
3
4
1
5
2
6
SW5
SW-PUSH
R187
120
R187
120
J18
BOX Header 2X6M
J18
BOX Header 2X6M
1 23 45 67 89 10
11 12
LTC Power
LTC Power
VIN1
GN
D
VOUT1
VIN2
Power_ON VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
POWER
LEDB
POWER
LEDBC101
10u
C101
10u