OPTO Link

using Altera Stratix GX transceiver

Jerzy ZielińskiPERG group Warsaw

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agenda

Stratix GX Short Introduction Transmission Basic Block Diagram Hardware-Only Based Optical link Internal Interface in Stratix GX FPGA

Environment Implementation 2.5Gbps optical link, with Matlab based GUI

using Internal Interface Transmission parameters measurement

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Altera Stratix GX Introduction

Up to 20 channels for 3.125 Gbps transceiver blocks Up to 41,250 Logic Elements, 3 Mb RAM and 638 I/O pins High performance architecture Build in source-synchronous transfer protocols Serial light protocol ready

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Stratix/Stratix GX Development Board

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Transmission Basic Block Diagram

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Hardware-Only Couter Test

8bit Word Basic Transmission without 8b/10b coding Errors on Differential Lines Errors during Transmission

8bit Word Transmission with 8b/10b coding No Error in Hardware-Based-Visual-Only Test

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Only-Hardware Counter Test

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Internal Interface

FPGA Environment Multi-Protocol External Communication Command & Status Words Internal Interface BUS Internal Interface with Components Communication

Stratix GX OPTO component Internal Interface Implementation Ready Full Integration with Internal Interface Communication Other Components Communication Possible

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Internal InterfaceInside FPGA

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Matlab based GUI

Connection Initialization

TransmissionControl

TransmissionInitialization

LatencyMeasurement

I/O Read

Bit-Error-RateMeasurement

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Matlab based GUI

2.5Gbps optical link, with Matlab based Graphical User Interface using Internal Interface Transmision Initialization Transmitted Word Control Bit Error Rate Tests Latency Measurement

GUI-to-HARDWARE Full Control

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Transmission Parameters

Transmission Rate 2.5Gbps Word Length 8bit Clock Frequency 156.25MHz

First Transmitted After 200ns Latency 30 c.c.

~200ns

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Future Plans

16bit Channel Mode

Multi-Channel Transmission Component

Link to Xilinx Virtex II PRO, using the same Transmission Protocol

OPTO Link

using Altera Stratix GX transceiver

Jerzy ZielińskiPERG group Warsaw