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EE290C - Spring 2004Advanced Topics in Circuit DesignHigh-Speed Electrical Interfaces

Lecture #19Chip-Level Issues

Serial/Parallel tradeoffsClock distribution

Jared Zerbe3/30/04

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Agenda : Chip-Level IssuesSerial & parallel

Points of viewSharing functions & key differentiators

Multi-drop bussesOn-chip clocking

Chip clock distribution, termination, jitterFailover clocking

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Generic View : Point to Point Parallel Interfaces vs. Serial Links

Parallel InterfacesLinks logically grouped (bus)

Source-synchronous clock

Skew between links an issue

Serial LinksIndependent connections

Clock embedded with dataRequires encoding scheme overhead e.g. 8B/10BAsynchronous clocking

No link to link skew issues

Clock

Data

Clock

Data

Clock

Data I/O I/OData +Clock Clock

Data

Clock

Data I/O I/O

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Serial/Parallel : Point of ViewThe best engineering solution doesn’t always winWhat makes sense in a system all depends on your point of view…Typical systems using links fall into one of three catagories

1. Legacy upgrades2. Future-legacy3. Green-field

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Legacy upgradeMake my existing system run faster

Have to live with environment available…including not only channel but clocks

You can have a 5-10 year span from BP design to Si!Interested in scaling performance while changing nothing else

Power, area, pins, etcTypically require low-performance mode to support legacy linksConventionally generations are 4x in performance

2x happens sometimes but is rareNot much parallel-bus scaling

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Future LegacyGive me something that is “standard now”

…but can be upgraded laterAKA

“I don’t want to spend a lot of $$”“I don’t want to build a system which is going to be obsolete”

Not usually leading-edge performanceWeak parallel standards usually limit use of parallel busses here

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Green Field DesignA blank sheet or “green field” to design

Can look at completely new topology/architectureUsually interested in figure of merit

Highest Gb/mW or Gb/mm^2 or Gb/cm^2 or Gb/$$Cross-sectional bandwidth thru PCB

Doesn’t always mean cost-insensitive!Parallel can win here by sharing functions

Shared structures can be more efficientSystem vs. Silicon complexity can be traded off

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Simple Parallel Clock Sharing

Source – synchronous clock, simple distributionIssue

Board data skews, on-chip clock tree skews limit to ~1-1.5G

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Parallel Sharing : PLL Phasors

Shared PLLsCan use a common-PLL and distribute phase-vectors to each linkEach link needs a phase-mixer/CDR for recovery

Yeung, JSSC 11/2000

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Parallel Sharing : CDR Outputs

Shared CDRsSingle link phase-tracks, others follow

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Parallel Sharing : Power Supplies

Can regulate an entire shared power supplyExpensive, but has a big gain

An regulated inverter has %UI delay, not ps delay

Wei, JSSC 11/2000

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Serial / Parallel tradeoffs

Shared EqualizationEqualization : similar traces mean similar S21’sStill requires a FIR per channel; can share coefficients

CommonCoefficients

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Serial & Parallel : Key Differentiators

Latency : a significant differenceSerialization and deserialization takes time

If the data is inherently parallel, it takes less time to send it parallelReally a line-rate vs. on-chip clock rate issuePlesiochronous often = coding = high-latency

When is this bit…

…available here?

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Key Differentiators Con’tBandwidth granularity

What is the smallest chunk of bandwidth required?Parallel busses are big blocks

Source data : aggregation from many sources or one?CDRs : Plesiochronous or Mesochronous sources?

Cost functionChip to chip? Are chip I/O’s “free”?Board-to-board? Are connector pins expensive?Simple issues like this can greatly affect the tradeoff

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Agenda : Chip-Level IssuesSerial & parallel

Points of viewSharing functions & key differentiators

Multi-drop bussesOn-chip clocking

Chip clock distribution, termination, jitterFailover clocking

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Multi-drop busses

Multiple devices sharing same interconnectEach driver sees Zo/2 when it drivesTopology is good for memory interconnect, some multiprocessor interconnectCan be very efficient use of wires viz. connectivityMust watch stub discontinuities

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Multi-Drop Channel Characteristics

Attenuation gets much worse as devices are addedMultiple poles at same frequency

Loss can be terrible at high speeds

0.00

0.20

0.40

0.60

0.80

1.00

1e+008 1e+009

Nor

mal

ized

am

plitu

de

Freq (Hz)

"low_CL""1_drop""2_drop""4_drop""8_drop"

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Direct Rambus : Single-Ended + Reference

Single-ended open-drain current-mode driversVery efficient on device pin-count, channel-wiring Large amount of bandwidth from a single very small device

Common referenceNoise limits : how well this functions viz. differential

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Direct Rambus : Clocking

Source-synchronous clocking in both directionsDLLs remove common on-chip buffer delaysMinimized clock & data skews within the bus

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Agenda : Chip-Level IssuesSerial & parallel

Points of viewSharing functions & key differentiators

Multi-drop bussesOn-chip clocking

Chip clock distribution, termination, jitterFailover clocking

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On Chip Clock Distribution

On a big chip there is distribution both before PLLsand after PLLsWhat is the PLL jitter characteristic?

LC VCO – notchRing VCO – Low-pass

Ref Clk PhasedetectorKpd

Icp

Icp R

C

VCOKvco/s

Clockbuffer

N÷

+−

105 106 107 108 109 1010

-30

-20

-10

0

10

frequency [Hz]

Noi

se tr

ansf

er fu

nctio

ns [d

B]

fromVCO supply

frominput clock

fromclock buffer supply

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Why Does This Matter?

Distribution = buffering = delayDelay in a clock buffer = PSR jitter succeptability

CMOS : ~1% Vdd variation = ~1% in delay variationKeep your buffers short & your power supplies clean

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Buffered Distribution to PLLsPLLs with ring VCOs can filter high frequency buffer noise

But pass low frequency noiseSolution

Eliminate bufferingDesign buffers with low-frequency noise removed

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Mansuri Clock Buffer Idea for PSR

Mansuri, JSSC 11/2003

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Clock Buffer Delay vs. VSG

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Failover Clocking

Critical in some systems where reliability is keyNo single point of failure

Multiple clock phases are averaged to create input to PLL phase-detector