advanced vlsi chap8-3

7/28/2019 ADVANCED VLSI CHAP8-3

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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf

Register-transfer design

A register-transfer system is a sequential

machine.

Register-transfer design is structural

complex combinations of state machines

may not be easily described solely by a

large state transition graph. Register-transfer design concentrates on

functionality, not details of logic design.


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Register-transfer system example

A register-transfer machine has combinational

logic connecting registers:

DQ combinational

logic

D QD Q combinational

logic

combinational

logic


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Block diagrams

Block diagrams specify structure: wire bundleof width 5


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Register-transfer simulation

Simulates to clock-cycle accuracy. Doesnt

guarantee timing.

Important to get proper function of

machine before jumping into detailed logic

design. (But be sure to take into account

critical delays when choosing register-transfer organization.)


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Simulation coding

Hardware description languages are

typically supported by a simulation

system: VHDL, Verilog, etc.Simulation engine takes care of scheduling

events during simulation.

Can hand-code a simulation in aprogramming language.

Must be sure that register-transfer events

happen in proper order.


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Sample VHDL code

sync: process begin

wait until CLOCKevent and CLOCK=1;

state

out1


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Sample C simulator

while (TRUE) {

switch (state) {

case S0:

x = a + b;

state = S1;

next;

case S1:

...}

}

loop executed once

per clock cycle

each case corresponds

to a state; sets outputs,

next state


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Data path-controller systems

One good way to structure a system is as a

data path and a controller:

data path executes regular operations(arithmetic, etc.), holds registers with data-

oriented state;

controller evaluates irregular functions, setscontrol signals for data path.


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Data and control are equivalent

We can rewrite control into data and visa

versa:

control: if i1 = 0 then o1


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Data operators

Arithmetic operations are easy to spot in

hardware description languages:

x


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Conditionals and multiplexers

if x = 0 then

reg1


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Alternate data path-controller

systems

controller

data path

one controller,

one data path

controller

data path

controller

data path

two communicating

data path-controller

systems


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ASM charts

An ASM chart is a register-transfer

description.

ASM charts let us describe functionwithout choosing a partitioning between

control and data.

Once we have specified the function, wecan refine it into a block diagram which

partitions data and control.


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Sample ASM chart


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ASM state

An ASM state specifies a machine state

and a set of actions in that state. All actions

occur in parallel.

s1 x = a + b

y = c - d + e

o1 = 1

name of state (notation only)


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Actions in state

Actions in a state are unconditionally

executed.

A state can execute as many actions as youwant, but you must eventually supply

hardware for all those actions.

A register may be assigned to only once ina state (single-assignment rule).


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Implementing operations in an

ASM state

state with one addition

two additions requires two adders


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Sequences of states

States are linked by transitions.

States are executed sequentially. Each state

may take independent actions (includingassigning to a variable assigned to in a

previous state).

s1x = a + b

s2x = c + d

y = a + d


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Data paths from states

Maximum amount of hardware in data path

is determined by state which executes the

most functionality. Function units implementing data

operations may be reused across states, but

multiplexers will be required to routevalues to the shared function units.


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Function unit sharing example

mux allows +

to compute

a+b, a+c


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Conditionals

Conditional chooses which state to execute

next based on primary input or present

state value. Can be drawn in either of two ways:

a = bx

00 01 10 11T

F


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Execution of conditionals

An ASM chart describes a Moore

sequential machine. If the logic associated

with an ASM chart fragment doesntcorrespond to a legal sequential machine,

then it isnt a legal ASM chart.

Conditional can evaluate only present stateor primary input value on present cycle.

I l i ASM b h i


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Implementing an ASM branch in

a Moore machine

ASM chart

state transition

graph of

controller


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Mealy machines and ASM

Mealy machine requires a conditional

output.

ASM notation for conditional output:

i10

y = c + d

E t ti d t th d


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Extracting data path and

controller

ASM chart notation helps identify data,

control.

Once you choose what values andoperations go into the data path, you can

determine by elimination what goes into

the controller. Structure of the ASM chart gives structure

of controller state transition graph.


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Data path-controller extraction


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Pipelines

Provide higher utilization of logic:

Combinational logic


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Pipeline metrics

Throughput: rate at

which new values

enter the system. Initiation interval: time

between successive

inputs.

Latency: delay frominput to output.

Delay through logic

is D, n blocks.

L = D. T = n/D.

P = D/n.

Cl k i d d th h t


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Clock period and throughput vs.

pipeline depth


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Simple pipelines

Pure pipelines have no control.

Choose latency, throughput.

Choose register locations with retiming.

Overhead:

Setup, hold times.

Power.


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Bad cutset for pipelining


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Utilization

Must fill, drain pipe at start and end of

computation.

Given D cycles of data, n-stage pipe:U = D/(D+n)


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Complex pipelines

Actions in pipeline depend on data or

external events.

Data dependencies may be forward orbackward.

Actions on pipe:

Stall values.

Abort operation.

Bypass values.

Pipeline with feedforward


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Pipeline with feedforward

constraint


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Pipeline with feedback constraint


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Pipeline with shared hardware


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Pipeline control

Controllers are

necessary when pipe

stages takeconditions.

Unconditional pipe

stage controller has

one state, onetransition.


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Pipeline with distributed control


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Pipeline controller with condition

Distributed control for pipeline


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Distributed control for pipeline

flush


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Control for hardware sharing

Product machine for distributed


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Product machine for distributed

control

Distributed control is

hard to verify

because state is notcentralized.

Product machine

form identifies global

control actions. Can verify using

symbolic simulation,

model checking.

advanced vlsi chap8-3

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