advanced vlsi chap8-2-verilog

7/28/2019 ADVANCED VLSI CHAP8-2-verilog

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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf

Topics

Verilog register-transfer modeling:

basics using traffic light controller;

synthesis.


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Verilog

Verilog was designed as an efficient

simulation language.

Relatively simple, terse syntax.

Most popular HDL in use today.


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Verilog formulas

a & b Boolean AND

a | b Boolean OR

~a Boolean NOTa = b Assignment

a == b Equality

#1 timea


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Verilog constants

Bit constant:

0, 1

Bit vector constant:

4b1010


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Some useful constructs

define aconst 2b00

constant vector

$monitor($time,,a=%b, b=%b,a,b);

value monitor output#1 a=0; b=0

#2 a=1; b=0sequence of waveforms


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Four-valued OR function

0 1 X z

0 0 1 x x

1 1 1 1 1

X x 1 x x

Z x 1 x x


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Four-valued AND function

0 1 X z

0 0 0 x x

1 0 1 x x

X x x x x

Z x x x x


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Verilog structural model

Module adder(a,b,cin,sum,cout);

input a, b, cin;

output sum, cout;xor #2 s(sum,a,b,cin); // sum

and #1 // carry out

c1(x1,a,b); c2(x2,a,cin);

c3(x3,b,cin);or #1

c4(cout,x1,x2,x3);

endmodule

Time delay for output

Output

wireInput wires


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If statements

if (b | c) then

y = 1;

elsey


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Conditional assignments

if (b | c) then

y = 1;

elsez = a | b;

Simulation:

Condition is tested

based on current signalstates.

Only one net gets an

event.

Synthesis: Creates dont-cares for

y and z.


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Loop statement

A loop performs an operation over an array

of signals:

for (i=0; i


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always statement

always guards execution of a block of

statements.

Block is always executed on the logicalcondition.

always @(sigval) begin ..

end


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Structure of a Verilog model

Module statement.

Declares I/O pin names.

Declarations:

inputs and outputs;

registers.

Body.


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A synthesizable Verilog

archtiecture

Declarations of pins and registers.

Definitions of constants (similar to C

#define statement). define GREEN 2b11

Combinational and sequential portions.

Within @always statements.


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Verilog combinational portion

always @(ctrl_state or short or long or

cars) begin

when HG: begin // state hwy-green

highway_light = GREEN;

farm_light = RED;

if (cars & long) then

begin ctrl_next = HY; start_timer =1; end

else begin ctrl_next - HG;

start_timer = 0; end

end


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Verilog sequential portion

always @(posedge clock or negedge reset)

if (~reset)

ctrl_state


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Testbench structure

Unit under test

(UUT)

testbench

tester


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Verilog testbed organization

Module declaration.

Two components: UUT and tester.

Definition of UUT.

Definition of tester.


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Testbench tester process

initial

begin

$monitor($time,,a=%b,a);

#1 a=0; b=0; cin=0;

#1 a=1; b=0; cin=0;

#2 a=1; b=1; cin=1;

endendmodule

Test inputs

Prints signal values

advanced vlsi chap8-2-verilog

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