advanced vlsi chap8-2-vhdl

7/28/2019 ADVANCED VLSI CHAP8-2-vhdl

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Modern VLSI Design 4e: Chapter 8 Copyright 2008 Wayne Wolf

Topics

VHDL register-transfer modeling:

basics using traffic light controller;

synthesis.


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VHDL

Combines a general-purpose programming

language and an HDL.

Modeled on Ada programming language.

VHDL is a rich language:

modules;

abstract data types.

VHDL is case-insensitive.


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Abstract data types

package lights is

---this is a comment

subtype light is bit_vector(0 to1);

constant red : light : B00;

constant green : light : B01;constant yellow : light : B10;

end lights;


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VHDL entities

An entity defines the interface to the

module.

May plug various descriptions into the

entity interface:

behavioral;

RT;

gate.


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VHDL constants

Bit constant:

0, 1

Bit vector constant:

B0101


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Traffic light entity declaration

entity tlc_fsm is

port( CLOCK: in BIT; -- machine clock

reset : in BIT; -- global resetcars : in BIT; -- car signal

short, long : in BIT;

highway_light : out light := green;

farm_light : out light := red;

start_timer : out BIT

);


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VHDL processes

A process is a unit of parallel execution.

All processes in an entity execute in parallel.

Processes are used to build up behavior.

Our RT model will have at least two

processes:

combinational process for the logic;

sequential process for the flip-flops.


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VHDL process example

combin : process(state,hg)

begin

highway_light


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VHDL formulas

a and b Boolean AND

a or b Boolean OR

not a Boolean NOT

a


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VHDL data types

std_logic Binary signal

std_logic_vector Binary signal vector


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Operations in the process

if (b or c) = 1

then

y


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Conditional assignments

if (b or c) = 1

then

y


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Some useful constructs

avec: out std_logic_vector(11 downto 0)

vector

constant zerovec: std_logic_vector(0 to7) := B00000000;

constant vectorsum


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Structure of a VHDL model

Library use statements.

Entity declaration.

Architecture declaration.

Processes, etc. that form the architecture.

An entity may have multiple instantiations.


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A synthesizable VHDL

archtiecture

Declarations of types and signals.

Combinational process.

May be several combinational processes that

communicate via signals.

Synchronous process.


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A synthesizable synchronous

process

sync: process(CLOCK)

begin

wait until CLOCKevent and CLOCK= 1;

ctrl_state


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Testbench structure

Unit under test

(UUT)

testbench

tester


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VHDL testbed organization

Library calls.

Entity declaration.

Generally has no inputs or outputs.

Architecture section.

UUT is a component.

Testbench logic is a process.


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Testbench tester process

tester: process

begin

reset

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