addressing modes mtt48 3 - 16 cpu08 core motorola cpu08 addressing modes
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Addressing Modes MTT48 3 - 1CPU08 CoreMotorola
CPU08ADDRESSING
MODES
Addressing Modes MTT48 3 - 3CPU08 CoreMotorola
• Inherent• Immediate• Direct• Extended• Indexed• Relative• Memory to Memory
ADDRESSING MODES
Addressing Modes MTT48 3 - 4CPU08 CoreMotorola
Inherent Addressing
Has no operand
Operates mostly on CPU registers or bits
Example:
CLRA
* opcode location
Memory
program space
data space
ocl*
ocl + 1
4 F
X X
X X
X X
A
CPU
0 0
X X
Addressing Modes MTT48 3 - 5CPU08 CoreMotorola
Immediate Addressing
Specifies value directly, not an address of the value• Indicated by #
Has one operand• Contained in the byte or bytes immediately following opcode
Example:
LDA #$FF
Memory
program space
data space
ocl
ocl + 1
A 6
F F
X X
X X
A
CPU
F F
X X
Addressing Modes MTT48 3 - 6CPU08 CoreMotorola
Direct Addressing
Specifies 8 bit address of operand• Upper byte of 16 bit address is assumed to be $00• Used to access first 256 bytes of memory
Address contained in the byte immediately following opcode
Example:
LDA $50
Memory
program space
data space
ocl
ocl + 1
B 6
5 0
X X
A A 0050
0051
A
CPU
A A
X X
Addressing Modes MTT48 3 - 7CPU08 CoreMotorola
Extended Addressing
Specifies 16 bit address of operand• Used to access address greater $00FF memory
Address contained in the two bytes immediately following opcode
Example:
LDA $0400
Memory
program space
data space
ocl
ocl + 1
C 6
0 4
X X
A A 0400
0401
ocl + 20 0
A
CPU
X X
A A
Addressing Modes MTT48 3 - 8CPU08 CoreMotorola
Indexed Addressing- NO Offset -
Specifies H:X index register contains the address of the operand
Example:CLR ,X
CPU
H:X04 00
Memory
program space
ocl
ocl + 1
7 F
X X
data space
X X 0400
ocl + 2X X
0 0 0400
Addressing Modes MTT48 3 - 9CPU08 CoreMotorola
Indexed Addressing- 8 Bit Offset-
Unsigned 8 bit offset + unsigned H:X register = memory location• H:X register is unaffected• 8 bit offset is the byte immediately following opcode
Example:
CLR 10,X
CPU
H:X04 00
Memory
program space
ocl
ocl + 1
6 F
0 A
data space
X X 040A
ocl + 2X X
0 0 040A
Addressing Modes MTT48 3 - 10CPU08 CoreMotorola
Indexed Addressing- 16 Bit Offset -
Unsigned 16 bit offset + unsigned H:X register = memory location• H:X register is unaffected• 16 bit offset is the two bytes immediately following opcode
Example:
STA $0100,X
Memory
program space
ocl
ocl + 1
D 7
0 1
data space
X X 0150
ocl + 20 0
5 5 0150
CPU
H:X00 50
55A
Addressing Modes MTT48 3 - 11CPU08 CoreMotorola
Indexed Addressing- 8 & 16 Bit Offsets -
Commonly used to access elements of data structures• Offset would be base address of structure• Index register would contain displacement to the Nth element
ORG $100Table FCB $10, $20, $30, $40 .......
• • * Calculate displacement for element N in A • CLRH TAX LDA Table,X
NOTE: If Table were in the first 256 bytes of
memory, most assemblers would use an
8-bit offset instruction
••••
0100 Table
H:X=N
element 1
element 2
element 3
element n
element n+1
element n+2
element n+3
Addressing Modes MTT48 3 - 12CPU08 CoreMotorola
Indexed Addressing- Using Stack pointer and 8-Bit Offset -
Unsigned 8 bit offset + unsigned SP register = memory location• SP register is unaffected• 8 bit offset is the byte immediately following opcode bytes
Example:
STA 5,SP
Memory
program space
ocl
ocl + 1
9 E
E 7
stack space
X X 00D0
ocl + 20 5
F F 00D5
•••
CPU
SP00 D0
FFA
Addressing Modes MTT48 3 - 13CPU08 CoreMotorola
Indexed Addressing- Using Stack pointer and 16-Bit Offset -
Unsigned 16 bit offset + unsigned SP register = memory location• SP register is unaffected• 16 bit offset is the two bytes immediately following opcode bytes
Example:
STA $100,SPCPU
SP00 D0
FFA
Memory
program space
ocl
ocl + 1
9 E
D 7
data space
X X 00D0
ocl + 20 1
F F 01D0
•••
0 0 ocl + 3
NOTE: If interrupts are disabled, SP can be
used as an additional index register
• Less efficient because of pre byte
Addressing Modes MTT48 3 - 14CPU08 CoreMotorola
Stack Pointer- 8 Bit Offsets -
High level language support
• Compilers often place parameters for procedures and temporary storage on the stack
Stack Pointer addressing is an efficient means to access this information
00C0 SPX X
temp 1
temp 2 msb
temp 2 lsb
param 3
param 2
param 1
temp 1 = 1,SP
temp 2 = 2,SP and 3,SP
param 3 = 4,SP
param 2 = 5,SP
param 1 = 6,SP
What happens if the stack pointer moves?
ie: more information is pushed onto the stack.
Where is -1,SP ?
Addressing Modes MTT48 3 - 15CPU08 CoreMotorola
PC
OFFSET
PC
OFFSET
OCL
BEQ LOOP
LOOP
OCL
• Only for branch instructions.
• PC is + 2 from OCL (due to prefetching) • 8 bit offset. Range is -128 +126 from PC • Effective Address (EA) = PC + displacement(8-bit Offset) • Assembler calculates displacement: disp. = EA - PC
OP CODE
SERVICE
OFFSET
OP CODE
OFFSET
BGT SERVICE
+2
+2
Relative Addressing
Addressing Modes MTT48 3 - 16CPU08 CoreMotorola
Relative Addressing Cont.
Used in all conditional branch instructions
If condition is TRUEProgram Counter = Program Counter + Signed 8 bit offset
elseProgram Counter is unaffected
Example:
BEQ $8100
CPU
PC81 52
Memory
program space
$8150
$8151
2 7
A E
$8152X X
81 00
if condition true
Addressing Modes MTT48 3 - 17CPU08 CoreMotorola
Indexed Addressing- No Offset with Post Increment -
Specifies H:X index register contains the address of the operand
• After address of operand is calculated, H:X is incremented by 1
Example:
Loop CBEQ X+,Out BRA LoopOut . . . .
Memory
program space
ocl
ocl + 1
7 1
0 2
data space
X X 0400
ocl + 2X X
5 5 0410
•••
CPU
H:X04 00
04 01
04 02
04 11
55A
Addressing Modes MTT48 3 - 18CPU08 CoreMotorola
Indexed Addressing- 8 bit Offset with Post Increment -
Just like indexed addressing with 8 bit offset, plus post increment
• After address of operand is calculated, H:X is incremented by 1
Example:
Loop CBEQ $50,X+,Out BRA LoopOut . . . .
ocl + 1
ocl + 2
Memory
program space
ocl7 1
5 0
data space
X X 0450
0 2
5 5 0460
•••
CPU
H:X04 00
04 01
04 02
04 11
55A
Addressing Modes MTT48 3 - 19CPU08 CoreMotorola
Memory to Memory Addressing
Used to move information from one location to another
• Does not use/affect CPU registers – Except when using indexed addressing with post increment
• More efficient than Load/Store combination
Can only be used with the MOV instruction
• MOV Source Address,Destination Address
Four variations:
• Immediate to Direct
• Direct to Direct
• Indexed to Direct with Post Increment
• Direct to Indexed with Post Increment
Addressing Modes MTT48 3 - 20CPU08 CoreMotorola
Source is one byte immediate value
Destination must be in first 256 bytes of memory
Example usage:
• Initialization of variables or registers
Memory to Memory Addressing - Immediate to Direct -
MOV #$AA,$F0
Memory
program space
ocl
ocl + 1
6 E
A A
ocl + 2F 0
data space
X X 00F0
A A 00F0
Addressing Modes MTT48 3 - 21CPU08 CoreMotorola
Source must be in first 256 bytes of memory
Destination must be in first 256 bytes of memory
Example usage:
• Moving data from one page zero location to another
Memory to Memory Addressing - Direct to Direct -
MOV $00,$F0
Memory
program space
ocl
ocl + 1
4 E
0 0
ocl + 2F 0
data space
X X 00F0
5 5 00F0
data space
5 5 0000
Addressing Modes MTT48 3 - 22CPU08 CoreMotorola
Memory to Memory Addressing - Indexed with Post Increment to Direct -
MOV X+,$18Memory
program space
ocl
ocl + 1
7 E
1 8
ocl + 2X X
data space
5 0 0400
Source may be any where in memory map
Destination must be in first 256 byte of memory
Example usage:
• Writing data to a communications device from a buffer
CPU
H:X04 00
04 01
X X 0018
5 0 0018
data space
Addressing Modes MTT48 3 - 23CPU08 CoreMotorola
Memory to Memory Addressing - Direct to Indexed with Post Increment -
MOV $18,X+Memory
program space
ocl
ocl + 1
5 E
1 8
ocl + 2X X
data space
5 0 0018
Source must be in first 256 byte of memory
Destination may be any where in memory map
Example usage: • Writing data from a communications device to a buffer
CPU
H:X04 00
04 01
X X 0400
5 0 0400
data space
Addressing Modes MTT48 3 - 24CPU08 CoreMotorola
MEMORY TO MEMORY- EXAMPLE -
SCI communication handling routines
ORG $50RCVPTR RMB 2XMTPTR RMB 2
ORG $100RCVB RMB 10XMTB RMB 10
Receive • • • LDHX RCVPTR • • • MOV $18,X+ • • • STHX RCVPTR • • • Transmit • • • LDHX XMTPTR • • • MOV X+,$18 • • • STHX XMTPTR • • •
RCVPTR0100
•••
XMTPTR010A
Addressing Modes MTT48 3 - 25CPU08 CoreMotorola
Addressing Modes Summary
MODE Example UsageInherent PULXImmediate ADD #$10Direct SUB $50Extended SUB $200Indexed
• no offset STA ,X• 8 or 16 bit offset LDX $200,X• post increment CBEQ X+,There• 8 bit offset w/ post inc CBEQ
$50,X+,ThereStack Pointer
• 8 or 16 bit offset CLR 5,SPRelative (PC) BEQ HereMemory to Memory
• Immediate to Direct MOV #$00,$A0• Direct to Direct MOV $18,$F0• Indexed post inc to Direct MOV X+,$12• Direct to Indexed post inc MOV $12,X+
Addressing Modes MTT48 3 - 26CPU08 CoreMotorola
Ad
dre
ss M
odes
Exe
rcis
es
For
eac
h op
erat
ion,
com
plet
e th
e in
stru
ctio
n us
ing
the
appr
opri
ate
addr
essi
ng m
ode.
A
lso
indi
cate
the
leng
th (
# of
byt
es)
of th
e in
stru
ctio
n an
d ex
ecut
ion
time
(# o
f cy
cles
).
1. L
oad
accu
mul
ator
A w
ith th
e he
x va
lue
55.
2. L
oad
the
X r
egis
ter
with
the
cont
ents
of
mem
ory
loca
tion
hex
C1.
3.
Loa
d th
e X
reg
iste
r w
ith th
e co
nten
ts o
f th
e m
emor
y lo
catio
n w
hose
add
ress
is th
e co
nten
ts o
f th
e X
reg
iste
r.
4. L
oad
accu
mul
ator
A w
ith th
e co
nten
ts o
f th
e m
emor
y lo
catio
n w
hose
add
ress
is th
e co
nten
ts o
f X
re
gist
er h
ighe
r th
an th
e m
emor
y ad
dres
s $2
20.
HC
08-a
ddrS
ol
Inst
ruct
ion:
Ope
rand
:
B
ytes
: C
ycle
s:
LDA
LDX
LDX
LDA
5. N
orm
al b
ranc
h in
stru
ctio
ns c
an c
hang
e th
e pr
ogra
m c
ount
er to
an
addr
ess
as f
ar a
s
by
tes
forw
ard
or
byte
s ba
ckw
ard
in p
rogr
am m
emor
y re
lativ
e to
the
addr
ess
of th
e br
anch
opc
ode.
6.
Ind
exed
add
ress
ing
gene
rate
s a
mem
ory
addr
ess
that
is th
e su
m o
f tw
o va
lues
: a r
egis
ter
and
an o
ffse
t. T
he r
egis
ter
valu
e is
a
(co
nsta
nt/v
aria
ble)
and
the
offs
et v
alue
is a
(con
stan
t/var
iabl
e).
7. D
irec
t and
Ext
ende
d ad
dres
s m
odes
gen
erat
e a
(con
stan
t/var
iabl
e) a
ddre
ss.
Dir
ect r
equi
res
a
(
one/
two)
byt
e ad
dres
s in
pro
gram
mem
ory
who
se v
alue
is f
rom
to
;
Ext
ende
d re
quir
es a
(
one/
two)
byt
e ad
dres
s in
pro
gram
mem
ory
who
se v
alue
is f
rom
to
.
8.
A c
omm
on w
ay to
use
the
16-b
it of
fset
with
inde
x ad
dres
s m
ode
is to
use
the
(
offs
et, X
reg
iste
r) a
s th
e st
artin
g ad
dres
s to
a ta
ble
of it
ems
and
the
(o
ffse
t, X
reg
iste
r) a
s th
e di
stan
ce to
sel
ect t
he it
em to
be
acce
ssed
.