A study of low jitter Phase Locked Loop for SPDIF

JiHoon Kim Soongsil University

School of Electronic Engineering Seoul, Korea

lixc1988@naver.com

Yong Moon Soongsil University

School of Electronic Engineering Seoul, Korea

moony@ssu.ac.kr

Abstract— CDR (Clock data recovery) circuit is an essential component for serial data communication. S/PDIF generates a lot of jitter from 2T and 3T. The PLL recognizes that the frequency changes in 2T and 3T portion. Change in frequency loses locking of the block. 3T detector reset Circuit is designed for reducing the jitter. Output jitter specifications of 9 frequencies are satisfied. 65nm CMOS process is used in this study.

Keywords— CMOS, CDR , SPDIF , PLL

I. INTRODUCTION

CDR (Clock data recovery) circuit is an essential component for serial data communication. The clock information is included in digital data. For this reason, CDR circuits are important to the clock and data restoration of digital data. Many CDR circuits use PLL. Therefore, the design of the PLL (Phase Locked Loop) circuit is important for data recovery. [1], [2]

This paper uses the S/PDIF signal which is one of digital data standard. S/PDIF is the acronym of Sony/Philips Digital Interface Format, which is data communication protocol for transmitting digital audio signals. SPDIF digital data stream is encoded using the BMC (Bi-phase Mark Code). S/PDIF signal has 192 frames in one block. One frame has two sub-frames. One sub-frame has 32 time slots. The preamble signal of 8bits exists in each sub-frame. The 4 time slots could be assigned to the preamble. When 3 bits occur in one slot, it is 3T. T is the period of S/PDIF data frequency. In addition, other S/PDIF features follow the standard of IEC-60958 [3].

Conventional PLL generate some jitter. Because the SPDIF signal is vulnerable to 2T (2x data period) and 3T (3x data period). The proposed PLL is designed for S/PDIF with low jitter by minimizing jitter in 2T and 3T portion of data.

II. BLOCK DESIGNE

Figure 1. PLL Block Diagram

Figure 1 is the block diagram of the proposed PLL. The operation of PLL is described in detail. S/PDIF is the input

signal. The PLL block recovers clock in SPDIF signal. The PLL block is locked to the recovered clock. When the sampling rate changes in S/PDIF, FD (Frequency Detector) are designed to detect the frequency change. When the change in frequency is detected, FD generates 3 bit signals. The 3bit signal changes the division ratio of the divider and generates the reset signal. 3T Detector & Reset circuit generates the signal from the 2T and 3T part. This signal drives the mux. So the PLL block finds the target frequency.

A. PLL (Phase Locked Loop )

The VCO (Voltage Controlled Oscillator) of the proposed PLL is composed of buffer and the ring oscillator, which has 5 stage inverter with feedback loop. The oscillation frequency of VCO is determined by the amount of current passing through the inverters. The VCO generates two frequencies of 24.576MHz and 22.5792MHz.

The input signal of S/PDIF is random data including 2T or 3T signal. The PFD (Phase frequency detector) of the conventional PLL could not be used, because the output value of PFD follows the PLL with random data including 2T or 3T signal, so PLL loses the lock condition. Therefore, the hogge PD is used in this design. [4].

The pumping current of charge pump circuit is 30μA.

The value of division ratio is 1, 2, 4, 6 and 8. The division ratio is decided by A, B and C. A, B and C are determined by the frequency detector. The program divider can be used for every frequency type of S/PDIF.

B. FD (Frequncy Detector)

Figure 2. Frequency Detector Block Diagram

Figure 2 is the block diagram of the FD circuit. The Frequency detector samples the S/PDIF signal according to 24MHz clock. If the frequency detector detects the preamble, it stores the count value in the memory block. The frequency detector can detect the frequency using the preamble. After the detection of the frequency from the preamble, the frequency detector outputs 3bit signals corresponding to the detected

frequency. [5] 3bit signal is used for the select signal of the program divider and the input signal of the reset circuit.

C. Loop Filter Reset circuit

1BIT Reset_CLK3BIT Edge

detector

Figure 3. The Loop Filter Reset Block Diagram

Fig 3 is the block diagram of Loop Filter Reset circuit .When the sampling rate changes, 3 bit signals shows the transition. 3 bit signal is detected by edge detector. The output signal is 1 bit. After passing the multivibrator, it generates the reset signal. The Reset_CLK signal duration is determined by monostable multivibrator circuit.

D. 3T Detector & Reset circuit

Figure 4. 3T Detector Reset circuit Diagram

Figure 4 is the block diagram of 3T Detector & Reset circuit. The 3T Detector & Reset circuit sampling is S/PDIF signal with 24MHz clock. When the frequency detector detects the preamble, the count value is sent to the selector block. The selector block receives the 4bit signal of A, B, C, and D. The selector block generates the desired clock. The output signal of multivibrator is the input signal of mux.

III. SIMULATION RESULT

Figure 5 shows the simulation of the proposed PLL block.

Figure 5. S/PDIF/ Phase Detecor output/ MUX input/ Modified PD output/

Charge pump output

Figure 6. (a) CP Output (b) PLL Frequency

Figure 7. (a) General PLL jitter (b) Proposed PLL jitter

TABLE I. OUTPUT FREQUNCY RANGE

NO.

����� ���� (�)

� �� � frequency (MHz)

General PLL � �� � frequency

(�)

Proposed PLL � �� � frequency

(�)

1 24.576 24.425~24.727 24.216~24.607 24.30~24.591

2 22.5792 22.452~22.707 22.274~22.605 22.471~22.681

3 12.288 12.250~12.325 12.187~12.356 12.212~12.314

4 11.264 11.232~11.295 11.185~11.328 11.192~11.315

5 6.144 6.134~6.153 6.123~6.165 6.145~6.155

6 5.6448 5.636~5.652 5.584~5.678 5.710~5.612

7 4.096 4.091~4.10 4.085~4.152 4.095~4.149

8 3.072 3.069~3.074 3.013~3.132 3.07~3.073

9 2.8224 2.820~2.824 2.817~2.827 2.821~2.823

When S/PDIF is input, output signal is PD_UP, DOWN. 3T detector reset circuit operates in 3T period of S/PDIF. MUX_UP, DOWN signals are output. MUX_UP, DOWN signals corrects PD_UP, DOWN signals. Output signal is UP, and DOWN.

Figure 6 (a) shows CP signal of Figure 5 according to time. Figure 6 (b) shows the PLL Frequency results. Figure 6 shows 24.576MHz. The simulation result is locked at 24.576MHz

Figure 7 (a) is the jitter of convention PLL and (b) is the jitter of the proposed PLL jitter. Output jitter range of S/PDIF frequency is ±500ps. General PLL exceeds the range of output jitter and its value is 656.2ps. But, the Proposed PLL satisfies the range of output jitter and its value is 487ps.

TableⅠ shows the output frequency. In TableⅠ, output frequency is in the satisfied range of 9 frequencies according to the specifications. The general PLL output jitter does not satisfy the output jitter of S/PDIF specification. The proposed PLL output jitter satisfies the output jitter of S/PDIF specification.

IV. CONCLUSION

We have designed the low jitter PLL for S/PDIF using 65nm CMOS technology. 3T Detector & Reset circuit can reduce jitter when 2T or 3T signals come in. The output of mux is corrected, so it can be locked to the required frequency. The proposed PLL satisfies 9 frequencies with satisfying the jitter specification of S/PDIF.

ACKNOWLEDGMENT

"This research was supported by the MSIP (Ministry of Science, ICT and Future Planning), Korea, under the ITRC(Information Technology Research Center) support program (IITP-2017-2012-0-00641) supervised by the IITP(Institute for Information & communications Technology Promotion)"

REFERENCES

[1] Hong Jun Park, CMOS Analog Integrated circuit Design, signal press

[2] Xuehui Chen, Yingmei Chen,” A 9.95-11.5Gb/s Full Rate CDR with Jitter Attenuation PLL in 65-nm CMOS Technology” 2011 International Symposium on Communication Technology, April 2011.

[3] IEC, IEC-6095- Digital audio interface.

[4] Behzad Razavi, “Challenges in the Design of High-Speed Clock and Data Recovery Circuits”, IEEE Communications Magazine,Augest 2002.

[5] JiHoon Kim, YoungJu Hwang and Yong Moon, “A study of the referenceless CDR based on PLL”, ISOCC 2016, November 2016