a cascade multilevel frequency changing converter for high-power applications

2118 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 6, JUNE 2013

A Cascade Multilevel Frequency ChangingConverter for High-Power Applications

Diego E. Soto-Sanchez, Member, IEEE, Rubén Peña, Member, IEEE, Roberto Cárdenas, Senior Member, IEEE,Jon Clare, Senior Member, IEEE, and Patrick Wheeler, Member, IEEE

Abstract—A novel frequency changing conversion scheme usingthree cascade multilevel converters in a Π topology is presented.The scheme resembles a direct frequency converter using thecascade converter in its simplest form (series strings of H-bridgemodules equipped with a dc link capacitor) as the building block ofthe overall converter. This yields a highly modular implementationapproach which may be attractive for large power applicationssuch as intertie connections and variable speed drives. Frequencyconversion takes place in a cascade converter which connects theinput and output ports. Two other converters are placed, respec-tively, in parallel to the input, to remove unwanted current com-ponents from the input, and the output to regulate output voltage.Operation of this topology is explained and a scheme to controlall the converters is developed, including control of convertercurrents, capacitor voltages, and output voltage. Experimentalresults, using a low-power prototype, confirm the foundations ofthe topology and verify its overall performance operating as apower supply at typical output frequencies (25 Hz, 162/3 Hz anddc) while being fed from a 50-Hz system. Additionally, PowerSIMsimulations demonstrate that the topology may be suitable for im-plementing high-performance, high-power ac drive systems usingvector control techniques.

Index Terms—Frequency conversion, multilevel converter,power conversion.

I. INTRODUCTION

B ECAUSE of the limitations of the current generationof power semiconductors devices (voltage and switching

frequency), large power converters typically use multimoduletopologies such as multipulse and the multilevel converters [1].In this context, the cascade multilevel converter, as comparedto other multimodule converters, is one of the most suitabletopologies for very high-power applications [1]–[8], particu-larly for static var compensators systems such as StatComs[5]–[8] and active power filters (APFs) [2], where floating ca-pacitors can implement the multiple isolated dc voltage sourcesneeded.

Manuscript received July 23, 2011; revised October 30, 2011; acceptedJanuary 27, 2012. Date of publication April 17, 2012; date of current versionFebruary 6, 2013. This work was supported by Fondecyt Chile under Contract1071136. The support of the Industrial Electronics and Mechatronics Millen-nium Nucleus is also acknowledged.

D. E. Soto-Sanchez is with the Department of Electrical Engineering,University of Magallanes, Punta Arenas 6210427, Chile (e-mail: [email protected]).

R. Peña is with the Department of Electrical Engineering, University ofConcepción, Concepción 4074580, Chile (e-mail: [email protected]).

R. Cárdenas is with the Department of Electrical Engineering, University ofChile, Santiago 8370451, Chile (e-mail: [email protected]).

J. Clare and P. Wheeler are with the Department of Electrical and ElectronicEngineering, University of Nottingham, Nottingham NG7 2RD, U.K. (e-mail:[email protected]; [email protected]).

Digital Object Identifier 10.1109/TIE.2012.2194971

On first sight, applications which require a cascade converterto process active power (as in the case of a unified powerflow controller (UPFC) [9] and a frequency changer converter[10]) may not seem as appealing as the case of a StatCom,if implemented as a back-to-back topology [1]. To maintainisolation among the multiple H-bridge modules, a back-to-backcascade-based topology needs either multiple standard isolationtransformers or a complex multiwinding isolation transformer[10]–[13].

Recently, a non-back-to-back implementation approach,resembling direct ac/ac converter topologies, has led to a newfamily of cascade-based converters which has become known asthe modular multilevel converter (MMC) topology [14]–[18].The main feature of an MMC topology is that it uses the cascadeconverter, or a similar modular converter, as the building blockof the main converter topology. In this approach, the cascadeconverter resembles a high-voltage valve in a standard convertertopology, e.g., a series string of H-bridge modules arranged in asingle-phase bridge, three-phase bridge or even in a full matrixconverter topology. Series strings of half-bridge modules areattractive for ac-dc conversion systems [14] and [17], and a fewinstallations of MMC-based HVDC systems have already beencommissioned [19], whereas full-bridge (FB)-based convertersseem more attractive for ac-ac conversion [14]–[16], e.g.,cycloconverters.

Generalization of this concept, and the realization of theenormous potential it may have in the area of large powerconverters, is attributed to [14]. However, there were also a fewpreliminary works that applied cascade converters in a modularfashion. These included a full matrix cascade-based converter[20] and a cascade-based UPFC [21] and [22]. In [21], thecascade converter is intended as the building block of a networkof series and parallel elements that could emulate a UPFC. Thesingle series-parallel arrangement proposed in [21] and [22] hasa limited operation area when compared to a standard UPFC,but the double series-parallel arrangement in [23] demonstratesfeasibility of a fully controllable cascade-based UPFC. In asimilar context, a matrix converter applying the flying capacitorconverter, and therefore not as modular as the cascade-basedmatrix converter, was reported in [24].

This paper proposes a novel MMC-based frequency chang-ing converter which, as shown in Fig. 1, uses three cascadeconverters arranged in a Π topology. The topology itself followsthe idea of implementing a converter as a network of seriesand parallel elements (in this case two parallel and one serieselement) and the MMC concept. An alternative interpretationof the Π topology would be that it corresponds to a special

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SOTO-SANCHEZ et al.: CASCADE MULTILEVEL FREQUENCY CHANGING CONVERTER FOR HIGH-POWER APPLICATIONS 2119

Fig. 1. Simplified schematic of the proposed frequency changer convertertopology. In this arrangement, each module is an H-bridge converter.

case of the FB ac-ac converter [15], where one of the arms hasbeen shorted. Like the FB-MMC converter, advantages of theΠ topology come mainly from its highly modular structure andthe use of one of the simplest converter modules to implement it(the H-bridge converter), which may have a significant impacton the final cost of a large power installation (manufactureof the Power Electronics Building Block and assembly of thetopology on the installation site).

Compared to the FB-MMC topology, the Π topology requiresa larger overall power rating in terms of power semiconductordevices and storage capacitors. However, it may require asmaller number of modules. An exhaustive comparison amongthe various potential MMC topologies for ac-ac conversion isbeyond the scope of this work.

This paper describes the principle of operation of the topol-ogy of Fig. 1 and develops suitable control strategies for thetopology to operate as a frequency changer. As recognized in[15] and [16], control of the capacitor voltages, in particular,the balance of capacitor voltages in each converter branch isone of the main issues with these topologies. A novel methodwhich uses a dedicated converter current component to balancecapacitor voltages, and which enables a systematic designapproach, is proposed.

Experimental results, from a low-power prototype, and sim-ulations of the proposed topology applied to the case of avector-controlled induction machine, validate operation of theproposed topology and its associated control strategies.

Because of the similarities with a UPFC, the cascade con-verter placed between the input and the output ports will bereferred to as the series converter, whereas the cascade convert-ers in parallel to the input and in parallel to the output will bereferred to as the shunt and output converters, respectively.

The remainder of this paper is organized as follows.Section II describes basic operation of the proposed topology,Section III develops a dynamic model of the series converter,with emphasis on capacitor voltages, and proposes a suitablecontrol scheme for regulation of the series bridge capacitorvoltages. By extension of the control strategy for the seriesconverter, Section III also describes control strategies for theshunt and output converters. Section IV presents both experi-mental and simulation results; and finally, Section V briefly dis-

cusses the requirements of semiconductor devices and storagecapacitors.

II. PRINCIPLE OF OPERATION

The basic operation of the proposed topology is describedin this section. The analysis which follows ignores switchingeffects. Fig. 1 shows the basis of the proposed new topology;where for simplicity of illustration, each cascade converteruses two H-bridge modules per branch. Clearly, the numberof modules can be increased, as required, to meet the voltagerating of a frequency changer in a high-power application.

In Fig. 1, the main conversion element is the series converter.This enables exchange of active power from the input, at theinput frequency, to the output, at the output frequency, andvice versa. The purpose of the output converter is to supportthe output voltage, i.e., maintain output voltage as externallydemanded, independent of operation conditions. The shuntconverter filters out current components which are not at theinput frequency and compensates for reactive current at thefundamental input frequency.

Note that each converter branch in Fig. 1 is a series stringof H-bridge modules equipped only with a capacitor on thedc link. The inductors in series with the shunt and the seriesconverters are interface reactors which, as a StatCom, areadded to reduce ripple current due to the switching. For thefrequency range of interest, the inductor voltage is small, incomparison with the overall converter voltage, and thereforeits effect can be neglected in analysis. Thus, as in a cascadeStatCom [5], [6], neglecting converter losses, each H-bridgemodule, and hence each cascade branch, is constrained to zeroactive power exchange with the rest of the system in order toavoid divergence of capacitor voltages.

The rate of change in the total stored energy in the capacitorsof each converter in Fig. 1 corresponds to the instantaneouspower exchanged by that particular converter with the rest ofthe system, as given in

dWsh

dt= vsish

dWse

dt= (vs − vo)ise

dWpo

dt= voipo (1)

where vs is the input voltage, assumed sinusoidal at frequencyωs; vo is the output voltage, assumed sinusoidal at frequencyωo; and ish, ise and ipo are, respectively, the shunt, the series,and the output converter current. Wsh, Wse, and Wpo are,respectively, the total stored energy in the capacitors of theshunt, the series, and the output converter.

For the case of Fig. 1, Wconv , with conv = {sh, se, po}, isgiven in

Wconv =c

2(v2

C1conv + v2C2conv

)(2)

where C is the capacitance of the dc storage capacitor ofthe H-bridge module (assumed the same for all the H-bridgemodules); and vc1conv and vc2conv are the capacitor voltage ofcapacitor C1conv and C2conv , respectively.


In general, the converter currents in (1) can be set to con-tain two components, one at frequency ωs, the s-component,and another at frequency ωo, the o-component. These compo-nents can be further resolved into an in-phase component anda quadrature component, α- and β-component, respectively.Thus, converter currents can be expressed as given in

ish = iαssh + iβs

sh + iαosh + iβo

sh

ise = iαsse + iβs

se + iαose + iβo

se

ipo = iαspo + iβs

po + iαopo + iβo

po (3)

where iαsconv and iβs

conv , with conv = {sh, se, po}, are, respec-tively, the component of iconv in-phase and in-quadrature to vs.Similarly, iαo

conv and iβoconv are, respectively, the component of

iconv in-phase and in-quadrature to vo. In steady state,

Wconv = W conv + W̃conv (4)

where W conv and W̃conv , with conv = {sh, se, po}, are, re-spectively, the dc component and the ripple component ofWconv . In general, W̃conv may contain components at frequen-cies 2ωs, (ωs − ωo), (ωs + ωo) and 2ωo.

For stable operation, W conv is kept at a constant andsufficiently high value, hence sufficiently high total capaci-tor voltage (vCTconv = vC1conv + vC2conv), to manipulate theconverter currents. The dynamics of the capacitor voltages, interms of W conv , can be written as

dW sh

dt= Psh

dW se

dt= Pse

dW po

dt= Ppo (5)

where Psh, Pse, and Ppo are, respectively, the active powerexchanged by the shunt, the series and the output converter.

Manipulation of W conv requires a net exchange of energy,hence active power, from/to the system to/from the capacitors.In steady state, dW conv/dt = Pconv = 0. Therefore, as antici-pated, for stable operation, each converter branch is constrainedto zero active power exchange. For the converter of Fig. 1, thefollowing equations apply:

Psh =VsIαssh = 0

Pse =VsIαsse − VoI

αose = 0

Ppo =VoIαopo = 0 (6)

where Vo and Vs are, respectively, the amplitude of vs and vo.Iαsconv is the amplitude of iαs

conv , and Iαoconv is the amplitude of

iαoconv , where conv = {sh, se, po}.

Note that in (6)Psh = Ppo = 0, therefore, the balance ofactive power in the series converter, second equation in (6), cor-responds to the balance between the input (supply) power, Ps,and the output (load) power, Po. For stable operation, the seriesconverter is therefore required to draw a current componentfrom the supply such as it balances the power demanded bythe load. This current component corresponds to iαs

se in (3),and its amplitude (Iαs

se ), as described in Section III, is set by

Fig. 2. Steady-state operation of the proposed topology; simulated voltageand current waveforms in the: (a) supply, (b) load, (c) series converter, (d) shuntconverter, and (e) output converter.

a dc capacitor voltage regulator system. In simple terms, thiscorresponds to the manipulation of Iαs

se so that, for a given Po,represented by VoI

αose in (6), Pse is kept to zero. Regulation

of capacitor voltages of the shunt and output converter areimplemented in a similar way to that of the series converter butby manipulating Iαs

sh and Iαopo , respectively.

To illustrate operation of the proposed converter, Fig. 2shows the voltage and current waveforms in all converterbranches for a given operation condition. For simplicity, theoutput voltage is set to the same amplitude as the supply voltage(Vo = Vs) while the frequency is set to half of the supplyfrequency (25 Hz considering the converter is supplied from a50-Hz supply). As shown in Fig. 2, the load current is assumedto be in phase with the output voltage.

The amplitude of the 50-Hz current component of the seriesconverter, hence supply current, that balances the load power(due to the 25-Hz output voltage and current) can be calculatedas given in (7), which follows from (6). In this particular case,(7) yields a supply current of the same amplitude as the loadcurrent (i.e., Is = Iαs

se = Iαose = Io), where Is is the amplitude

of the supply current

Iαsse =

Vo

VsIαose . (7)

The resulting series converter current, along with the seriesconverter voltage, is shown in Fig. 2(c). Note that both seriesvoltage and current are complex waveforms which, in thiscase, contain a 50-Hz component, due to the supply, and a


25-Hz component, due to the load. Because the shunt converterbypasses the 25-Hz current component, the line current inFig. 2(a) is sinusoidal and in phase with the supply voltage.Note that in Fig. 2(d), the shunt converter current is at 25 Hzwhereas its voltage is at 50 Hz. Thus, the shunt converterin Fig. 1 does not exchange active power with the system.Similarly, the output converter bypasses the 50-Hz currentcomponent while its voltage is at 25 Hz, Fig. 2(e).

III. MODELING AND CONTROL

This section develops suitable control strategies to regulatethe capacitor voltages in all three cascade converters, controlthe current through the series and shunt converters, and set theoutput voltage of the output converter.

In controlling the converter topology of Fig. 1, one of themain issues is regulation of capacitor voltages. Balance ofactive power between the supply and load power is an implicitrequirement for the controller. To derive a suitable controlscheme, the dynamics of the capacitor voltages must first beaddressed. To this end, a dynamic model of the series converteris developed next.

A. Model of the Series Converter

In analyzing the series converter dynamics, the followingassumptions are made.

– The voltage/current component x and y are consideredto be orthogonal if the mean, or average, value of itsdot product over a certain period of time, assumed muchsmaller than the time constants governing the dynamicsof the capacitor voltages, is zero.

– The instantaneous current ise closely follows its de-mand; therefore, dynamics of converter current can beneglected. Good tracking of the current is ensured by asuitable current control loop.

– The series inductor voltage is negligible.Assuming that deviations in capacitor voltages, from the

balanced condition, are small, i.e., vC1se = vC2se ≈ VC , thedynamics of the capacitor voltages can be represented by

dvC1se

dt=

v1seise

CVC

dvC2se

dt=

v2seise

CVC. (8)

In a cascade converter, regulation of the capacitor voltages istypically implemented as the regulation of the overall capacitorvoltage and equalization of all capacitor voltages in the string,as given in (9) for the case of Fig. 1

vCTse = vC1se + vC2se

ΔvCse = vC1se − vC2se. (9)

Capacitor voltages are regulated by manipulating the con-verter current, ise and converter voltages v1se and v2se usinga similar approach to that proposed in [25] for a cascadeStatCom. For the case of Fig. 1, as given in (3), ise can beset to contain four orthogonal components. Setting iβs

se = ibal

in (3) and noting that iose = iαose + iβo

se yields (10). Therefore,

ise can be resolved into the following three components: 1) iαsse ,

a component which is in phase with the input voltage; 2) iose, acomponent which is at the output frequency and it corresponds,in principle, to the load current; and 3) ibal, a component whichwill be referred to as the balance component and it is at theinput frequency, but in quadrature to vs

ise = iαsse + iose + ibal. (10)

The component iαsse is used to control overall capacitor

voltage; whereas ibal is needed to implement balancing of thecapacitor voltages.

Similar to the converter current ise, each H-bridge convertervoltage contains one component at the input frequency andanother at the output frequency (both set so that vs and vo

are equally shared among all converters in the branch). Inaddition, there is a component which is in phase with thebalance current component ibal. This voltage corresponds tothe balance component, vbal

se which is controlled according toa voltage equalization system. For the cascade series converterof Fig. 1, the H-bridge converter voltages are set as given in(11).The general case of a series converter having N modules,where N is the number of H-bridge modules, is explained inAppendix

v1se =12(vs − vo) + vbal

se

v2se =12(vs − vo) − vbal

se . (11)

Using (9), (10) and (11) in (8), and then taking the mean value,the capacitor voltage dynamics can be represented by

dVCTse

dt=

12CVC

(VsIαsse − VoI

αose )

dΔVCse

dt=

1CVC

IbalVbalse (12)

where V balse is the amplitude of voltage injected as a balance

component in (11) and Ibal is the amplitude of the balancecurrent component, set constant at a small fraction of thenominal input current, but sufficiently high to ensure properequalization of capacitor voltages. For example, as given in(13) (20% of nominal input current). Remaining voltages andcurrents in (12) are as in (6)

Ibal = 0.2√

2Inom_s (13)

where Inom_s = Pnom/Vnom_s and Vnom_s and Pnom are,respectively, the nominal input voltage (RMS amplitude), andthe nominal power of the converter.

B. Control of the Series Converter

From (12), considering that the load current is set by externalconditions, it follows that the overall capacitor voltage VCTse

can be regulated by adjusting Iαsse ; whereas voltage deviation

ΔVCse can be controlled by adjusting V balse . Adjustment of

Iαsse and V bal

se can be accomplished in a closed-loop fashionusing proportional integral (PI) controllers. Fig. 3 summarizes


Fig. 3. Simplified control system block diagram for the series converter.

Fig. 4. Simplified equivalent control system block diagram for the seriesconverter including the dynamic model of the capacitor voltages.

implementation of this strategy, including the overall capacitorvoltage controller, the current controller, and the subsystem forthe equalization of capacitor voltages.

Assuming load power, Po behaves as an external disturbance,design of the control system for capacitor voltages is straight-forward. Fig. 4 shows the block diagram of the equivalentsystem which represents the dynamics of the capacitor voltagesin (12) and the controller of Fig. 3. Controller gains can bechosen so that resulting system (i.e., PI controller plus first-order plant) behaves as a second-order system with a specifiednatural frequency, ωn and a damping factor ξ = 0.707.

Tracking of the reference current i∗se is accomplished bya dead-beat controller [26]. To minimize coupling with thecapacitor voltage control loops, the voltage needed to imposethe demanded current (voltage demand set by the dead-beatcurrent controller, vlse in Fig. 3) is equally shared among allconverter modules. To improve performance, load current iois measured and added as a feedforward term to the referenceinput of the series current controller.

In Fig. 3, us and ubal are sinusoidal signals of unity ampli-tude which are, respectively, in phase to vs and in phase to ibal.These signals shape the output from the PI controllers (Iαs

se

and V balse ) into the appropriate voltage reference and current

reference waveforms.

Fig. 5. Simplified control system block diagram for the output converter.

C. Control of the Output Converter

The main purpose of the output converter is to set theoutput voltage as demanded by external means, e.g., a mastercontroller. Providing that the capacitor voltages are kept at asufficiently high value, the output converter will be able to setits voltage demand independent from the output current, if keptwithin practical limits. Control of capacitor voltages vC1o andvC2o is accomplished in a similar way to that of the seriesconverter. However, the output converter current is not forcedby the output converter itself but by the series converter. Fig. 5shows the control scheme of the output converter.

To control the overall capacitor voltage of the output con-verter, a current component which is in phase with vo, denotedas iαo

po , is forced through the series converter, and by this meansthrough the output converter. Note in Fig. 3 that iαo∗

po is fedforward into the reference input of the series current controller.A PI controller, driven by voltage error in the overall capacitorvoltage, adjusts the magnitude of iαo

po . Equalization of vC1o andvC2o is achieved in a similar way to that shown in Fig. 3. Thebalance current ibal, which is forced by the series converter,


is in this case bypassed by the output converter, and it cantherefore be used, as in the case of the series converter, toequalize vC1o to vC2o.

D. Control of the Shunt Converter

Control of the shunt converter is similar to that of a parallelAPF which operates in the power factor correction mode [27].The main purpose of this converter is to compensate for theinput of the frequency changer so that it draws a current, notonly at the fundamental input frequency, but also in phasewith the input voltage. For this, all current components whichare forced by the series converter, with exception of that inphase with vs, must also be forced through the shunt converter,but in the opposite direction. Thus, ibal, iαo

po , and io are fedforward into the reference input of the shunt converter currentcontroller. Note that in this way, ibal is kept flowing insidethe loop provided by the Π topology, thus preventing it fromflowing into the input or into the output. In addition to ibal,iαopo , and io, a current component which is in phase with vs,

and whose amplitude is set by an overall capacitor voltagecontroller of the shunt converter, is forced through the shuntconverter. Equalization of the capacitor voltages in the shuntconverter is achieved in a similar way to that shown in Fig. 3.

IV. SIMULATION AND EXPERIMENTAL RESULTS

To validate the proposals, topology, and associated controlstrategies, a low-power single-phase experimental prototypesystem was built and tested. In addition, PowerSIM (PSIM)simulations of a vector-controlled induction machine drive sys-tem applying the proposed converter were conducted. Experi-ments are intended to demonstrate system performance underload impact for different conditions of output frequency. PSIMsimulations illustrate capability of the proposed frequencychanger to force fast dynamic currents on an induction motor(both in amplitude and phase, hence frequency), as is typicallyrequired during a fast reversal of speed in a vector-controlledinduction machine drive system.

The experimental prototype uses six H-bridge modules, asshown in Fig. 1, and is controlled using a DSK 6713 DSPsystem equipped with a daughter card that implements ananalog interface and PWM units. Switching frequency of theH-bridge modules is set to 1.0 kHz. The parameters and ratingsof the experimental prototype are listed in Table I. Note that theseries converter requires being rated at twice the nominal inputvoltage (assuming equal nominal input and output voltage).This is twice the voltage rating required by the shunt and outputconverter. Therefore, each module of the series converter, ascompared to one of the shunt and output converter, requirestwice as much dc voltage. Making a small allowance for theinductor voltage, the dc voltage of the H-bridge modules ofthe series, shunt, and output converter were chosen to be 50 V,30 V, and 30 V, respectively.

Parameters of all six PI-based capacitor voltage controllers(i.e., overall voltage and voltage balance controllers of theshunt, the series, and the output converters) are chosen so thatsimplified dynamic model of capacitor voltages plus PI con-troller has a response time of 200 ms. Forcing of the converter

TABLE IPROTOTYPE RATINGS

current, both in the series and shunt converters, is based on theuse of a dead-beat controller, as shown in Fig. 3.

A. Experimental Results for Load Impact Tests

This section presents the system response to load impactswhen the experimental prototype operates as a voltage sourceof a constant magnitude and frequency, i.e., as a power supply.Experiments were conducted for an output frequency of 25 Hz,162/3 Hz and dc, which are typical in locomotive systems,for example [28], [29]. In each test, a switched R-L load isused to apply load steps from zero to full load and back again.Results shown in Figs. 6–8 correspond to tests undertaken at25 Hz, 162/3 Hz and dc, respectively; showing: line voltageand current; reference output voltage and load current; shuntand series converter currents; and dc link capacitor voltage ofeach H-bridge module in the prototype system. These resultsare system voltages and currents as sampled, every 500 us,by the DSP-based control system. Therefore, Figs. 6–8 do notgenerally show switching effects such as ripple current. Exper-imental steady-state converter voltage and current waveforms,as captured by a digital scope, for the case of 25 Hz output areshown in Fig. 9.

Fig. 6 shows the system response for the case of 25-Hzoutput. As can be seen from Fig. 6, following the load impact,the capacitor voltages of both series H-bridge modules vC1se

and vC2se start dropping but, after approximately 50 ms, thevoltages begin to recover from the load impact, exhibitingonly a small voltage drop before stabilizing again to the ref-erence voltage. As expected from the design specifications,the recovery takes place within 200 ms. Concerning balanceof capacitor voltages, Fig. 6 reveals that the strategy for theequalization of capacitor voltages has such a good performancethat, even during transients, it is hard to distinguish between thetwo capacitor voltages in Fig. 6 (deviation between capacitorvoltages is less than 1 V).

In regard to capacitor voltage of the shunt and output con-verters shown in Fig. 6, following the load impact, with theexception of a small increase in voltage ripple, there is nonoticeable disturbance in the capacitor voltages. This confirmsthe benefit of feeding forward the measured load current into


Fig. 6. System response to a load impact when the frequency changer operates as a power supply at 25-Hz output.

Fig. 7. System response to a load impact when the frequency changer operates as a power supply at 162/3 Hz output.

the series and shunt current control loops and also indicates thatmost of the impact, because of a load disturbance, is absorbedby the capacitors of the series converter.

Fig. 6 also shows the supply voltage and current along withthe reference output voltage and load current. As expected, con-sistent with a relatively slow series capacitor voltage controller,following the load impact, the line current increases slowly, tocompensate for the loss of stored energy in the series capacitors,reaching a small overshoot, close to the current limit, beforestabilizing to a current which is well within rated current andthat balances the active power demanded by the load.

Note that soon after the load is switched on, the series andshunt converters start drawing larger currents. This is consistentwith the use of the load current as a feedforward term and there-fore confirms that the load current component is being rapidlyforced through the series and shunt converters. Note also thatthe supply current is nearly sinusoidal and in phase with the linevoltage, even during transients, thus confirming that the outputfrequency current component is effectively cancelled from theline current by the shunt converter.

Fig. 7 shows similar results to that of Fig. 6 but for operationat 162/3 Hz. As it can be seen from this figure, system response,


Fig. 8. System response to a load impact when the frequency changer operates as a dc power supply.

in terms of capacitor voltages and line current, is very similarto that of Fig. 6. As expected, because of the different outputfrequency, the main differences from Fig. 6, in addition to theoutput voltage and load current, are in the series converterand shunt converter currents, which now contain a 162/3 Hzcomponent. Notwithstanding the exact current waveform, theconverter currents in Fig. 7 show similar dynamic performanceto those in Fig. 6 (e.g., overshoot, rise and stabilization time),and they are all maintained well within normal operation values.

Fig. 8 shows the system response to a load impact whenthe proposed topology operates as a dc power supply. Notethat, in comparison to Fig. 6, the voltage magnitude in Fig. 8has been reduced to 75% of rated output voltage; otherwisethe R-L load would have demanded approximately twice asmuch power and hence 50-Hz current from the line than inFig. 6. As experimentally confirmed, but not shown here, theseries converter current hits the limit current, and after a shortperiod of operation at current limit, the system trips because itis unable to control the series capacitor voltages. Nevertheless,the results in Fig. 8 show that for a dc output, the system is alsoable to rapidly reject the load disturbance, keeping a stable andwell-regulated dc link voltage and all converter currents withinnormal operation conditions. One interesting feature in Fig. 8is that it clearly shows that both the series and shunt convertercurrents contain, as expected, a 50-Hz and dc component.

In general, the system performance when the R-L load isshed from the output, as seen in Figs. 6–8, is very similarto that when the load is switched on. In the main, followingdisconnection of the load, the capacitor voltages in the seriesconverter show a small increase before they start recovering tothe reference value within 200 ms. Capacitor voltages maintainbalance, even during the transient, and the supply current, asdictated by the series capacitor voltage controller, graduallydecreases to the no-load condition.

To further confirm operation of the proposed topology, Fig. 9shows steady-state converter voltage and current waveforms ofall three converters following the load impact of Fig. 6. As it canbe seen from Fig. 9(a), the supply current is nearly sinusoidaland in phase with the line voltage. Output voltage shown inFig. 9(b) is a five-level sinusoidal PWM voltage waveformwhich results in a nearly sinusoidal load current. Results inFig. 9(a), in terms of compensation for distortion and powerfactor in the supply, also confirm a good performance of shuntconverter and its control strategy.

Fig. 9(c) shows the overall series converter voltage andcurrent. Note that the PWM voltage in Fig. 9(c) is not as regularas that of Fig. 9(b); recall that the series converter must imposea voltage with a relatively large 50-Hz and 25-Hz component.Similarly, because of the load, the series converter current is acomplex waveform which, as expected, contains components at50 Hz and 25 Hz, Fig. 9(c).

Fig. 9 also shows the voltage across and the current boththrough the shunt converter [Fig. 9(d)] and the output converter[Fig. 9(e)]. Like the series converter current, the shunt convertercurrent contains components at 50 Hz and 25 Hz. The 50-Hzcomponent corresponds mainly to the quadrature balance cur-rent component (needed for balancing capacitor voltages),whereas the 25-Hz component corresponds to the load currentthat the shunt converter bypasses to prevent it from flowing intothe supply. For the case of Fig. 9(d), the quadrature balancecurrent component is small, compared to the 50-Hz seriesconverter current component that balances the load, thus theshunt converter current appears to be dominated by the 25-Hzcomponent. In contrast to Fig. 9(d), the output converter currentin Fig. 9(e) is clearly dominated by the 50-Hz component. Thisdemonstrates that the 25-Hz component needed to regulate theoutput capacitor voltages, because of the converter losses, isactually very small. In summary, results in Fig. 9(d) and (e)


Fig. 9. Steady-state results for 25-Hz output: (a) line voltage and current;(b) load voltage and current; (c) series converter voltage and current; (d) shuntconverter voltage and current, and (e) output converter voltage and current.Scales (1): 40 V/div, 5 A/div. Note (1): In the scope, the current is scaled sothat it has smaller amplitude than its corresponding voltage.

confirm that both the shunt and output converters are behavingvery effectively as bypass filters for the 25-Hz and 50-Hz com-ponent, respectively. Furthermore, the output converter is ableto impose a high quality sinusoidal PWM voltage, as demandedby the control system (constant amplitude and frequency in thiscase), on the load.

B. Simulation Results for a Drive System

To further verify potential applications for the proposed con-verter system and to illustrate expected performance, a simu-lation of vector-controlled induction machine drive, employingthe proposed converter configuration has been implemented inPSIM. To illustrate dynamic performance, the simulation hasbeen run to investigate speed reversal transients. The vectorcontrol scheme uses an indirect flux-oriented control technique,with d-axis aligned to an estimated-rotor flux position [30].

TABLE IIRATINGS OF SIMULATED CONVERTER

TABLE IIIPARAMETERS OF SIMULATED MOTOR

The machine is fed by a three-phase version of the frequencychanger in Fig. 1. This comprises three single-phase units, usingtwo H-bridge modules per branch, in a star connection. Thesimulated machine is a 4.5 kW/380 V, 50-Hz, four-pole induc-tion motor. Parameters and ratings of the motor and frequencychanger are listed in Tables II and III, respectively.

The d- and q-axis motor current control loops use PI con-trollers and cross compensation to improve decoupling [25].Parameters were chosen for a closed-loop frequency responseof 667 rad/s (rise time of 5 ms). The speed controller is basedon a PI controller and its parameters were chosen for a closed-loop frequency response of 33 rad/s. Current limitation wasset to twice rated motor current (2

√2 × 10 ≈ 30 A). In regard

to the control system of the frequency changer, d- and q-axisvoltage demands from motor current controller are transformedback into the phase coordinate system and used as referenceinputs to the control system of Fig. 3, one for each phase.Capacitor voltage controllers, both overall capacitor voltageand voltage balance, are designed to the same specification asthe experimental prototype, i.e., 200-ms response time. Seriesand shunt converter current control loops are the same as thoseof the experimental system.

Fig. 10 shows the simulated system response to a speedchange from −750 RPM to +750 RPM. For the speed reversalof Fig. 10, as in a typical vector-controlled motor drive system,the motor speed steadily rises to the reference speed whilethe motor currents limited to the maximum transient ratingto achieve as much braking and then acceleration torque aspossible. Therefore, in controlling an induction motor, Fig. 10demonstrates that the proposed frequency changer can achievethe same performance as a vector-controlled drive system thatemploys a standard PWM converter.

As far as operation of each converter is of concern, as inthe case of the load impact in Fig. 6, the series capacitorvoltages show only a small disturbance during reversal of speed


Fig. 10. Response to a speed reversal command from −750 rpm to 750 rpm.

(a small increase toward the end of acceleration), whereas theshunt and output capacitor voltages show only a small increasein voltage ripple. Furthermore, capacitor voltages in all theconverter branches maintain good balance. Note that the twoshunt capacitor voltages and the two output capacitor voltagesare all plotted together in Fig. 10. Close examination of Fig. 10reveals there is subtle difference in voltage ripple between theshunt and output capacitor voltages.

Note also that the series and shunt converter currents followa similar profile to the motor currents and that they keep wellwithin the transient converter ratings. As expected, the linecurrents are nearly sinusoidal and in phase with their respectiveline voltages. Following the speed reversal command, the linecurrents start decreasing from their pre-disturbance values,reversing phase, and hence direction of the power flow fora while, but reaching only a small amplitude. This contrastswith the line currents during acceleration, when the frequencyconverter draws relatively large currents, and hence power,from the line to rapidly deliver accelerating power to the motor.This difference can be explained by the type of load beingdriven by the motor (a frictional load in this case) which aidsbraking. From these results, it can be concluded that in this

particular case, during braking, most of the stored energy inthe inertia of the motor was actually dissipated by the frictionalload, and only a small fraction was delivered back to the line.

Results shown in Fig. 10 therefore confirm that the proposedfrequency changer can be used to replace a standard back-to-back-based frequency changer. The modularity of the systemalso lends itself to use at high powers.

V. VA RATING AND CAPACITOR REQUIREMENTS

This section briefly discusses the requirements of: 1) powersemiconductor devices; 2) dc capacitor filter on the H-bridgemodule; and 3) interface inductors of the PI topology.

The requirements of power semiconductor devices are typi-cally expressed in terms of the total VA rating of the devices(i.e., voltage rating × current rating of the devices) needed toimplement the converter. This measure is useful when com-paring to alternative converter topologies. In this case, the PItopology will be compared to the FB-MMC topology [15]. Forthis, it is sufficient to consider the converter voltage and cur-rent waveforms and to examine their maximum and minimumvalues (peak values). For the converter current, a more usefulmeasure of the current capability of the devices, instead of thepeak value or RMS value, is the average of the absolute valueof the current [15].

The comparison is made for the operation condition plottedin Fig. 2. This corresponds to nominal input and output voltage,at 50 Hz and 25 Hz, respectively, and nominal output currentand at unity power factor.

The voltage and current of each arm of the FB-MMC aregiven in (14)[15], where the subscript i = {1, 2, 3, 4} denotesthe i th arm of the topology

va1 = va4 =12(vs − vo)ia1 = ia4 =

12(is + io)

va2 = va3 =12(vs + vo)ia2 = ia3 =

12(is − io). (14)

For the case of Fig. 1, it can be shown that a good approxi-mation of each converter voltage and current is as given in

vsh = vs ish = −io

vse = (vs − vo) ise = (is + io)

vpo = vo iop = is. (15)

Calculation of the peak values of the voltages in (14) and in(15), as well as the average of the absolute value of the currents,shows that each arm of the FB-MMC, as compared to the seriesconverter, requires to be rated at half the current and half thevoltage. Therefore, the series converter alone requires the sameamount, in terms of VA rating, of semiconductor devices asthe FB-MMC. The shunt and output converter further increasethis requirement, when considering the average of the absolutevalue of the shunt and output converter current, to almost twiceas much.

Capacitor requirements, in terms of energy storage, can bedetermined by calculating the maximum amplitude of the ripple


on the stored energy over a period (T ) of the instantaneouspower, as given in

ΔW = maxti,tf

⎧⎨⎩

tf∫ti

vidt

⎫⎬⎭ (16)

where ti and tf are the instants at which the stored energyreaches its maximum and minimum values, respectively.

The capacitance of the storage capacitors is typically speci-fied so that they limit ΔW to a small fraction of the dc com-ponent of the stored energy. For the purpose of a comparison,the actual value of the capacitance and the voltage rating ofthe capacitor are not required. Given the allowed rW ,W canbe calculated using (17). The larger ΔW , the larger W , andtherefore, the larger capacitance that the H-bridge module willrequire (assuming a given dc-side voltage rating). Therefore,ΔW can be used as a measure of capacitor requirements

rW =ΔW

W. (17)

Calculation of (16) using the voltages and currents in (14)and (15) shows that the series converter alone has the samecapacitor requirements as the FB-MMC. Additional storagecapacitors in the shunt and series converter increase this re-quirement to five times as much. This significant increase islargely explained by the reduction in the frequency of the poweroscillation of the shunt and output converter (half the frequencyof the power oscillations in the series converter).

In general, selection of the capacitors is largely dictated bythe low frequency oscillation component of the instantaneouspower. The lower the frequency, the larger the capacitors re-quired to maintain the ripple on the stored energy low. Lowfrequency power oscillations occur when ωo is small or whenωo is close to ωs Unless a low frequency modulation of theinput current is allowed, to supply the low-power oscillationfrom the input, operation at low output frequency or close to theinput frequency should be avoided. This may not apply to thecase of a variable speed motor drive if its nominal frequencyis smaller than the input frequency. In this case, the powerdemand, hence the amplitude of the power oscillations, reduceswith reducing operation frequency, and therefore, power oscil-lations could be supplied from the capacitors, without incurringinto a significant ripple capacitor voltage. Compensation forthe power oscillations among the three phases of three-phaseconverter, for example by injecting zero sequence voltage andcurrent components, is currently being investigated.

The interface inductors in Fig. 1 are primarily intended tolimit the ripple current due to the switching. In a standardconverter which interfaces to the grid, operating at a switchingfrequency of a few kHz, the impedance of the inductor (at thefundamental frequency), as compared to the base impedance ofthe converter (Zbases_s = Vnom_s/Inom_s), is typically in theorder of 5%–15%. In a multilevel converter having a number ofH-bridge modules, each switching a few hundred Hz, becauseof the higher quality of the output voltage, the inductance ofthe inductor can be reduced. However, it may still be practicalto use an inductor in the order of 10% to help reducing the

rate of change of converter current under abnormal operationconditions (e.g., ac system disturbances). The current rating ofthe inductors is dictated by the total RMS current. In the caseof the series inductor, the current rating, considering the isse andiose components, is

(isse + iose)RMS =√

I2sRMS + I2

oRMS =√

2Inom_s (18)

where Is_nom is the amplitude of the nominal input current.Insulation voltage level, neglecting the switching nature ofconverter voltages (which is typically small in multilevel wave-forms), is set by the sinusoidal input voltage vs. Therefore, theinductor winding does not require reinforced insulation.

VI. CONCLUSION

A novel frequency changer topology using the multilevelcascade converter in its simplest form (a series string ofH-bridge modules equipped with a capacitor on each dc link)has been proposed. In this topology, the cascade converter,hence the H-bridge module is used as a building block. Thisenables a modular implementation approach in which voltagerating, hence power rating, can be readily extended to highervalues by adding as many H-bridge modules as needed to meetvoltage and power ratings of the application.

The proposed frequency changer can provide high qualityoutput voltage waveforms and can draw low distortion currentfrom the line, at close to unity power factor, thus facilitatinginterfacing to the load and the line.

The various control strategies needed to successfully operatethe proposed topology as a frequency changer have been devel-oped and presented. This includes schemes which are suitablefor: regulation of all capacitor voltages; tracking of the seriesand shunt converter currents; and setting of the output voltage.One of the main issues of the topology is regulation of capacitorvoltages. This is accomplished in the form of regulation ofoverall capacitor voltage of a branch and by balancing of theindividual capacitor voltages of each particular branch.

Operation of the proposed topology as a power supply with aspecified output voltage magnitude and frequency was success-fully demonstrated in a practical prototype. Experiments withload impacts, at various values of output frequency, demon-strate that the system (proposed topology and its associatedcontrol strategies) has an excellent performance in rejectingload disturbances. In terms of mitigation to a load impact, theproposed topology exhibits only a small impact in the series ca-pacitor voltages while keeping all the converter currents withinnormal operating conditions. Furthermore, it draws sinusoidalcurrent from the line, at close to unity power factor; and itprovides an adequate support to the output voltage during theimpact.

Preliminary results, from PSIM simulations of a vector-controlled induction machine, fed by the proposed frequencychanger, demonstrate such a drive can achieve similar perfor-mance to a vector-controlled drive equipped with a standardPWM converter. Therefore, the proposed converter may besuitable for high-performance induction machine drives in arange of high-power applications.


APPENDIX

This Appendix describes implementation of the voltage bal-ance scheme for a series converter having N H-bridge convertermodules. In this case, (N-1) capacitor voltage deviations, withrespect to the average capacitor voltage, are defined as givenin (19). Each voltage deviation, ΔvCise, is fed into a dedicatedPI controller. The output of each PI controller corresponds tothe amplitude of the voltage balance component, vbal

ise , which isinjected into the corresponding H-bridge converter module, asgiven in (20). Note that the voltage balance component of theNth H-bridge module is calculated so that all voltage balancecomponents sum to zero. This decouples regulation of the totalcapacitor voltage from the balancing of the N capacitor voltages

ΔvCise = vCise −1N

N∑i=1

vCise (19)

vise =1N

(vs − vo) + vbalisei = 1, 2, . . . , N

vbalise =

⎧⎨⎩

Vibalubal i = 1, 2, . . . (N − 1)

−N−1∑i=1

Vibalubal i = N.(20)

The control system of Fig. 3 requires two PI controllers forcontrolling the two capacitor voltages of the series converter,one to regulate the total capacitor voltage and the other tobalance the two capacitor voltages. An N H-bridge moduleseries converter, in addition to the PI controller which regulatesthe total capacitor voltage, requires (N-1) PI voltage balancingcontrollers, each one setting the corresponding voltage balancecomponent. A similar method, as that given in (19) and (20),applies to a shunt and output converters having N H-bridgemodules.

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Diego E. Soto-Sanchez (M’95) received theB.Sc. Electr. Eng. degree from the University ofMagallanes, Punta Arenas, Chile, in 1990, and thePh.D. degree from Imperial College, London, U.K.,in 1999.

Since 1990, he has been a Lecturer in powerelectronics and drives in the Department of ElectricalEngineering, University of Magallanes. His researchinterests include high-power converters for FACTSand HVDC systems.


Rubén Peña (S’95–M’97) was born in Coronel,Chile. He received the Electrical Engineering degreefrom the University of Concepcion, Concepcion,Chile, in 1984, and the M.Sc. and Ph.D. degrees fromthe University of Nottingham, Nottingham, U.K., in1992 and 1996, respectively.

From 1985 to 2008, he was a Lecturer in theUniversity of Magallanes, Punta Arenas, Chile. Heis currently with the Department of Electrical Engi-neering, University of Concepción. His main inter-ests are in control of power electronics converters, ac

drives, and renewable energy systems.Dr. Peña is a member of the Institute of Electrical and Electronic Engineers.

Roberto Cárdenas (S’95–M’97–SM’07) was bornin Punta Arenas, Chile. He received the B.S. degreefrom the University of Magallanes, Punta Arenas, in1988, and the M.Sc. and Ph.D degrees from the Uni-versity of Nottingham, Nottingham, U.K., in 1992and 1996, respectively.

From 1989 to 1991 and 1996 to 2008, he was aLecturer in the University of Magallanes. From 1991to 1996, he was with the Power Electronics Machinesand Control Group, University of Nottingham. Heis currently an Associate Professor in Power Elec-

tronics and Drives with the Department of Electrical Engineering, Universityof Chile, Santiago, Chile. His main interests include control of electricalmachines, variable speed drives, and renewable energy systems.

Dr. Cárdenas received the Best Paper Award from the IEEE TRANSACTIONS

ON INDUSTRIAL ELECTRONICS in 2004, and the “Ramon Salas Edward”Award for research excellence from the Chilean Institute of Engineers in 2009.

Jon Clare (M’90–SM’04) was born in Bristol,England. He received the B.Sc. and Ph.D. degreesin electrical engineering from The University ofBristol, Bristol, U.K.

From 1984 to 1990, he worked as a ResearchAssistant and Lecturer at The University of Bristolinvolved in teaching and research in power elec-tronic systems. Since 1990, he has been with thePower Electronics, Machines, and Control Groupat the University of Nottingham, Nottingham, U.K.and is currently Professor in Power Electronics. His

research interests are in power electronic converters and modulation strategies,variable speed drive systems, and electromagnetic compatibility.

Dr. Clare is a member of the Institution of Engineering Technology.

Patrick Wheeler (M’00) received the B.Eng. degreein electrical engineering, in 1990, and the Ph.D. de-gree for work on matrix converters at the Universityof Bristol, Bristol, U.K., in 1994.

In 1993, he moved to the University ofNottingham, Nottingham, U.K., and worked as a Re-search Assistant in the Department of Electrical andElectronic Engineering. In 1996, he was appointedLecturer (subsequently Senior Lecturer in 2002 andProfessor in Power Electronic Systems in 2007) withthe Power Electronics, Machines, and Control Group

at the University of Nottingham. His research interests are in variable speedac motor drives, particularly different circuit topologies, power converters forpower systems, and semiconductor switch use.

Dr. Wheeler is a member of the Institution of Engineering Technology.

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