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A 1 V Low Power CMOS Process

by

Luigi Di Pede

A thesis submitted in partial fulfillment of the requirernents for the Degree of Master of Applied Science

Department of Electrical and Computer Engineering University of Toronto

1998

Copyright O Luigi Di Pede 1998

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A IV Low Power CMOS Process

Master of Applied Science, 1998

Luigi Di Pede

Department of Electrical and Cornputer Engineering

University of Toronto

Abstract To reduce the size of portable telephones and other portable data comrnunicators,

and to increase the talk and use time, it is essential to reduce the power consumption of the

LSI circuits that are the main components of these devices. Because the power consump

tion of CMOS transistors is proportional to the square of the power supply voltage, the

power consumption can be dramaticdly reduced by cutting the power supply voltage. This

will only be true however, if the threshold voltage can be scaled down proportionately to

the supply voltage without increasing the standby current which otherwise increases due

to subthreshoId leakage.

This thesis deals with the optimization of the MOSFET device structure as a

means of providing 1V low power circuits in a submicron CMOS VLSI technology. Using

process and device simulations, a 300 mV threshold voltage, sub 80 mVldec subthreshold

swing 1 pm LVCMOS process was developed. Due to the fact that conventional process

simulations are not fully cdibrated to mode1 exact process conditions encountered experi-

mentally, process simulations were used only as a starting point from which experimental

results were used to refine the five most criticai fabrication steps.

High frequency and quasi-static C-V tests on n+ and p+ poly gates fabncated with

different gate oxide thicknesses were used to establish the fabrication conditions necessary

to prevent dopant penetration or polydepletion effect in 140 A gate oxide. Deep, low con-

centration (2x10'~ cm-3) n- and pwells with Bat profiles were implemented dong with

suitable threshold voltage adjust implants and shallow (0.2 pm) sourceldrain junctions to

achieve complementary long-channel devices with 300 mV threshold voltages and

< 80 mV/dec subthreshold swings.

A 12 mask 16 mm2 test chip was constnicted to fully characterize the process.

Acknowledgments

1 would like to express my sincere gratitude to Professor C. A. T. Salama for his

insightfd guidance and invaluable assistance during the course of this work.

My sincere thanks to Sebastian Magierowski for the countless hours of vaiuable

discussion both technically and personally. Also thanks to Dr. Zahir Parpia and Prof. Wai

Tung Ng for their insighdul advice.

Technical assistance from Dod Chettiar, Ralph Lisak, Dana Reem and Mr. Hou in

numerous timely occasions deserve very special acknowledgrnent. My appreciation is also

extended to al1 members of the Integrated Circuits Laboratory for creating a very friendly

and enjoyable working environment.

Thanks to Vito Mendolia, Paul Simak, Ramez Chehade. Ed Panyan, Dr. Nick

Dinadis and Takayuki Hayashi for intangibles.

Financial support provided by Gennum Corporation, MICRONET, Mitel. the Nat-

ural Sciences and Engineering Research Council of Canada and NORTEL is greatly

appreciated.

Last, and not least, 1 thank my family for having endured through it ail.

Chapter 1 page

Introduction ..................................................................................................... ..................... The Need for Low Power Electronics ........................... .. .................................. 1

Low Voltage Low Power C M O S ....................... .. ................................................. 4

Sources of Power Dissipation in CMOS ....................... .... ............................... -6

............................................................... Low Power Digital Design Methodology -9

Low Power Analog Circuits ........................ ..... ............................................... 9

Power Reduction through Rocess Technology .................... .... .................. 11

1.6.1 Threshold Voltage Optimization ................................................. 11

.............. 1.6.2 Subthreshold Current (Subthreshold Swing) Reduction 13

.......................................................... Low Voltage Low Power CMOS Processes 1 6

State of the Art Low Voltage Processes ...................... .. ..................................... 18

Thesis Objectives and Outline ............................................................................... 19

............................................................................................................. References -20

Chapter 2 Process and Device Design of a 1V Low Power CMOS Process .................rn............... 23

........................................................................................................... 2.1 Introduction 23

.............................................................................................. 2.2 CMOS Architecture -24

................................ 2.3 Design Considerations for a 1 V Low Power CMOS Process 26

............................... .........................*........ Short Channel Effects .. -26

.......................................................................... Thres hold Voltage 27

.......................................................................................... Latchup 30

...................................................................... MOSFET Isolation 3 1

......................................................................... Integration Issues -33

................................................................. ...................... 2.4 Process Description ... -34

............................................................................................... 2.5 Process Simulations 47

2.5.1 1D Simulations using SUPREM-3 ............................................... 47

2.6 Device Simulations ................................................................................................ 49

.................................... 2.6.1 1-V Characteristics and Threshold Voltage 50

....................................................................................................... 2.7 Device Scaling 53

......... 2.7.1 A 0.35 pm CMOS Process Optimized for 1 V Applications -54

............................................................................................................. 2.8 Summary 56

..................................................................... References -57

Chapter 3 ...................................... Experirnental Verification of a Low Voltage CMOS Proeess 62

......................................................................................... ....... Introduction ., ... ... -62

......................... Experimental Development of a 1 V Low Power CMOS Process 62

................................................ 3.2.1 Dual Polysilicon Gate Fabrication 63

............... 3.2.2 The Effect of a Nondegenerate Gate on MOS Device 64

Characteristics

............................................................ 3.2.3 N- and P- Weil Formation -68

............................. 3.2.4 P-Guard Implant/LOCOS Isolation Formation 69

........................................................... 3.2.5 Source/Drain Fabrication 69

.................................................... 3.2.6 Threshold Adjust Implants 7 1

......................................................................................... Test Chip Description 72

................................................................................................................ Summary 75

..................................................................................... .................... References ... -76

... Appendix A MOS Capacitor and PN Jonction Characterization ....O.................o 0.079 .............................................................................................. A . 1 C-V Measurements -79

................................................. A.2 FQW ard and Reverse Bias Diode Measurements -81

.................................................................. .................................. References ... 83

Appendix B Layout Design Rules ..., ............... ............................................................. W

List of Figures

Fig. 1.1

Fig. 1.2

Fig. 1 3

Fig. 1.4

Fig. 1.5

Fig. 1.6

Fig. 1.7

Fig. 1.8

Fig. 1.9

Fig. 1.10

Fig. 1.11

Fig. 2.1

Fig. 2.2

Fig. 2 3

Fig. 2.4

Fig. 2 5

Fig. 2.6

Fig. 2.7

Trends in Power Dissipation in Microprocessors and DSP.

Onset Temperatures of Various Failure Mechanism.

Process Technology Trends ( 1982-2000).

CMOS Scaling Guidelines (Late 80s-2004).

Dynarnic and Short-Circuit Power Dissipation in Digital CMOS Circuits.

Cross-Section of a CMOS Inverter with Parasitic Diodes Present.

Power Reduction Design Space.

Delay and Norrnalized Power vs. Supply Voltage for a CMOS 0.5 pm 2

Input NAND Gate with Fan-Out Equal to Three.

Weekly Inverted MOSFET - Bipolar Analogy.

Effect of V, Scaling on Subthreshold Leakage Current.

Key Technology Issues in a LVLP CMOS Process.

CMOS Active and Field Device Structure.

Average Minimum Feature Size F Versus Calendar Year Y.

Minimum Channel Len@ Versus xj*Lx(ws + wD12.

(a) QMS VS. NB for Poly and Al gates (b) NB vs. $F (c) IQB/ql vs. NB.

Buned Channel PMOS transistor (a) Cross-section (b) Depletion regions

(c) Doping profile (d) Equivalent circuit.

Source of Latchup in CMOS.

Parasitic Field Devices in CMOS.

Fig. 2.8

Fig. 2.9

Figm 2-10

Fig. 2.11

Fig. 2.12

Fig. 2.13

Fig. 2.14

Fig. 2.15

Fig. 2-16

Fig. 2.17

Fig. 2.18

Fig. 2.19

Fig. 2.20

Fig. 2.21

Fig. 3.1

Fig. 3.2

Fig. 3.3

A Dual-poly gate CMOS process is achieved by using a metai layer as part

of the gate stack (a) To strap the two discomected poly matenais so that

there is no interdiffusion path, @) To shunt the two connected poly materials

by carefully selecting the process conditions to control the inter-&sion.

LVCMOS Process Flow.

Kooi's Mode1 for Explaining Nitride Growth Under the Gate Oxide.

SALICIDE Integration Issues.

SUPREM-3 Simulation Regions.

Simulated Doping Profiles in (a) NMOS-Channel and Well. (b) NMOS-

Source/Drain. (c) PMOS-Channel and Well. (d) PMOS-SourcelDrain.

Simulated Doping Profile in the Field Region.

Simulated Transfer Characteristics with Lhm=l pm @ VDs = 50 mV.

Sirnulated Output Characteristics with LdraWI1= 1 p.

Simulated subthreshold characteristics for N- and PMOS transistors @

VDs= 0.05V & 1 V for Lhwn = 1 p.

(a) Threshold Voltage (b) Subthreshold Swing Roll-Off Characteristics.

0.35 pm CMOS Schematic Cross Section.

Simulated 0.35 pm CMOS Characteristics (a) Subthreshold 1-V. @) Output

N. (c) Threshold Voltage Roll-Off. (d) Subthreshold Slope Roll-Off.

Figure of Ment vs. LeR for Published Result.

(a) Extracted Vfi vs. Oxide Thickness from HFCV measurements (b) Typi-

cal HFCV profiles rneasured using Hewlett Packard's 4280A MHz C

Meter.

Typical Expenmental CQs-VG Characteristics.

Semi-Log Plot of the Measured (using SRA) Net Active Carrier Concentra-

tion in MOS Capacitor Gates (a) N+ (b) P+.

Fig. 3.4

Fig* 3.5

Fig. 3.6

Fig. 3.7

Fig. 3.8

Fig* 3.9

Fig. A.1

Fig. A.2

Fig. A.3

Fig. A.4

Fig. B.l

Semi-Log Plot of the Measured (using SRA) Net Active Carrier Rofile in

the (a) N-Weil and (b) P-Well Mer Drive-In.

Semi-Log Plot of the Measured (using SRA) P-Guard Carrier Concentration

vs. Depth from Surface Measured in the Field Region.

Semi-Log Plot of the Measured (using SRA) Net Active Carrier Concentra-

tion in the (a) nC S/D Region and @) p+ S/D Region.

PN Junction Forward Bias Log 0 - V Curve (a) n+ S / D and (b) p+ S/D.

Serni-Log Plot of the Measured (using SRA) Net Active Carrier Concentra-

tion in the Channel (a) PMOS @) NMOS.

Plot of the LVCMOS Test Chip.

Capacitance of a MOS Structure as a Function of Gate Voltage.

MOS Capaciior Test Chip.

Log O vs. V for a PN Diode with Series Resistance.

PN Junction Test Chip.

Layout Design Rules for a IV Low Power CMOS Process.

List of Tables

Table 1.1

Table 2.1

Table 2.2

Table 2 3

Table 2.4

Table 3.1

Table 3.2

Table 3 3

Table A.1

Table B.1

Sample of Presently Available Low Voltage Processes.

Low Voltage CMOS Device Parameters.

S imulated LVCMOS Process Parameters.

Sirnulated LVCMOS Device Parame ters.

A Cornparison of Key Device Parameters.

MOS Capacitor Thermal Budget.

Measured MOS Characteristics and Poly Gate Resistances.

PN Junction Characterization Data.

Dimensions of MO$ Capacitor Test Structures.

Layout Design Rules for a Low Voltage CMOS Process.

Introduction Page 1

Introduction

1.1 The Need for Low Power Electronics

Histoncally, Very Large Scale Integrated (VLSI) designs were characterized by

product performance (speed, accuracy, hnctionality, etc., in the case of processors and

similar products), or by silicon ana (especiaily in memory designs). Packaging and heat

transfer constraints were not sûingent and power dissipation was, in general, an after-

thought. Indeed, power considerations have been the main design cnterion only in special

portable applications such as wnst watches, pacemakers, and hearing aids, where saingent

requirements for small size, weight and long operating life were necessary [1,2]. Recently

though, low power has emerged as an increasingly important theme in the electronics

industry with power dissipation now given comparable consideration to speed and area

design specifications. This was prompted by a variety of factors listed below.

i) The growing popularity of battery powered portable electronic equipment such

as laptop PCs, Personal Digital Assistants (PDA's) and wireless telephones has

become a key driver of advanced semiconductor technologies. Because these

applications neccesitate portability and compactness, power consumption must

be kept to a minimum for a reasonable battery life at an acceptable battery

weight. Although the energy capacity of batteries has improved over the Iast two

decades, revolutionary improvements for very long-life compact power sources

does not seem imminent [2]. Conventional Nickel-Cadmium rechargeable bat-

teries only provide approximately 20 Watt-hours of energy per pound of weight.

With future muiti-media terminals expected to require 40 W, these terminals

would require 20 pounds of batteries for 10 hours of operation between

recharges. Even with the rapid progress in battery technology such as Ni-Metal

Hydride batteries offenng 40 W-hrAb, it is expected that only a 30% improve-

ment in battery performance will be achieved over the next five years [3].

A IV Low-Power CMOS Process University of Toronto

Introduction Page 2 -

ii) Enabled by advances in Integrated Circuit (IC) manufacturing, minimum fea-

ture sizes have decreased, chips have tended to get larger, integrating more tran-

sistors, thereby increasing power. As a result, the cost associated with cooling

and packaging high-end products is becoming prohibitive. Figure 1.1 illustrates

the trend in microprocessor and Digital Signal Processor @SP) power con-

sumption. Since power consumption is dissipated through the packages,

increasingly expensive packaging and cooling strategies are required as chip

power consumption increases [2,3].

t Ccramic Module with iiquid cooling

Cern-c package with air caoling

Piastic package

1980 1985 1990 1995 2000

Year of Publication

Fig. 1.1 Trends in Power Dissipation in Microprocessors and DSP [4-61.

Figure 1.1 shows that microprocessor power has nearly tripled every three years

since 1982. Two lirniting regimes are also indicated; in the portable Iimit, cool-

ing and energy storage issues make it difficult to carry systems that dissipate

over 5 W, in the package Iimit, it is difficult and expensive to package electron-

ics that dissipate over 30 W. These systerns typically require extemai cooling,

large heat sinks and specid packaging techniques [7].

- - -- - - - -


Introduction Page 3

iii) As transistors are scaled to sub-micron dimensions (< 0.8 pm), hotcarrier

effects, gate oxide integrity, and device breakdown require a reduction in power

via voltage reduction to maintain reliabiliiy. High power dissipation tends to

exacerbate silicon device failure mechanisms. For example, every 1 0 ' ~ increase

in operating temperature approximately doubles a component's failure rate [3].

Figure 1.2 illustrates the relationship between temperature and various silicon

IC failure mechanisrns.

Thermal runaway

Gate dielectric breakdown

Junction fatigue

Electromigration difision

Electrical-parameter shift

Package related failure

S ilicon-interconnec t fatigue

I I I 100 200 300

O C above normal operating temperature

Fig. 12 Onset Temperatures of Various Failure Mechanisms [3]

According to the Environmental Protection Agency (EPA), cornputer equipment

is responsible for between 5 and 10% of the electrical power consumed in the

United States [a]. The lower the power, the lower the electricity consurned and

therefore, the less the impact on the environment. Building more efficient com-

putes makes more sense than building new power plants to accommodate ineffi-

cient cornputea.


1.2 Low Voltage Low Power CMOS

CompIementary Metal Oxide Silicon (CMOS) is the most likely process technol-

ogy to be applied in Low Voltage Low Power (LVLP) applications. This a direct result of

the following advantages offered by CMOS processes [9].

i) Mature technology: CMOS processes are well established. The use of CMOS by

leading edge memory and microprocessor manufactures has led to continuous

improvement and scaling of CMOS processes.

ii) Design Resources: CMOS design is supported by vast design resources. Many design techniques and design libraries for analog and digital circuit design are

available.

iü) Availability: CMOS processes are readily available to prototype designs.

v) Mce: CMOS is the cheapest process available when compared to other technol-

ogies with comparable feature sizes.

Figure 1.3 illustrates the predicted process technology trends fiom 1982 to the year

2000. In 1982, CMOS accounted for 12% of the IC market with sales of $10.2 billion. It is

expected that by the year 2 0 , over 90% of ail system electronics will be implemented

using CMOS tec hnology.

Fig. 13 Process Technology Trends ( 1 982 -2000) [ 1 O]

A 1V Low-Power CMOS Process University of Toronto

Portable electronic systems are a key driver for CMOS technology. These products

use al1 of the features of deep subrnicron CMOS, namely high integration, performance

and low power to reduce cost/operation [Il]. Figure 1.4 illustrates the predicted scaling

guidelines for CMOS technology until the year 2004.

High Performance

-.-------*--------*- Law Power

O .O5 .l .2 S 1.0

Channel Length (L, p)

Fig. 1.4 CMOS Scaling Guidelines (Late 80s - 2004) [ 12,131

The upper curve in Figure 1.4 corresponds to a performance driven scenario. Even

with the reduced power supply voltage, the power density increases significantly due to a

large increase in the number of devices per unit area By the year 2004, it is projected that

for scaled CMOS, significant performance, density and powerffunction increases will be

achieved (4,8 and 12 times better than the present 0.35 Pm, 3.3V technology, respec-

tiveIy).

The lower curve in Figure 1.4 corresponds to the low power scenario. The low

power design curve has much bener power density due to the lower voltages and the lower

switching frequency. This scenario, is very attractive for applications where iow power is

the highest priority.


introduction Page 4

1.3 Sources of Power Dissipation in CMOS circuits

There are three principal components to power dissipation in digital

cuits as indicated in the following equation [14]

Consider the CMOS inverter shown in Figure L -5:

CMOS cir-

(a) Inverter Schematic showing @) Sources of Capacitance source of Dynamic and Short-Circuit Power Dissipation

Fig. 1.5 Djnamic and Short-Circuit Power Dissipation in Digital CMOS Circuits

In Figure 1.5, PdyMmic represents the switching component of power This compo-

nent arises when the output capacitance, CL, (made up of parasitic gate, ciiffision and

interconnect capacitances) is charged through the power supply or is discharged to ground.

This power can be expressed as:

where fck is the clock frequency and %+, is the node transition activity factor (i.e., the

probability a node makes a power consuming transition within a clock period) at a supply

voltage of VDD. Since the dynarnic switching power is usuaily the major cornponent of

overall power dissipation, a low-power design methodology usually concentrates on mini-

mizing total capacitance, supply voltage, and frequency of transitions [15].

PsbH,kua is due to the direct-path short circuit current, 1, which arises when

both the p-channel MOS (PMOS) and n-channel MOS (NMOS) transistors are simulta-

. . -

A 1V Law-Power CMOS Rocess University of Toronto

Introduction Page 7

neously on. Shortcircuit currents occur when the rise/fall time at the input of a gate is

larger than the output rise/fall time. While the condition V, < Fn < Vm - IV,,& holds for

the input voltage, where V' and V p are the threshold voltages of the n- and p-channel

devices respectively, there will be a conductive path open between the power supply and

ground because both devices are on. This power is usually expressed as:

For most ICs, the short-circuit power dissipated is approximately 5-10% of the

total dynamic power [14]. If the supply voltage is lowered below the sum of the thresholds

of the transistors, VDD < V' + IV$, short-circuit currents will be eliminated because both

devices cannot be on at the same time for al1 values of input voltage.

Fig. 1.6 Cross-Section of a CMOS Inverter with Parasitic Diodes Present

Pleakage, is due to the leakage current, IIeaka,, arising from reverse-bias diode cur-

rent and subthreshold leakage through the channel of "off' devices. Ileakage is set predorni-

nately by the processing technology. The diode leakage occurs when the transistor is off,

and another active transistor charges up/down the drain with respect to the former's bulk

potentiai. In the case of the inverter shown in Figure 1.5, with a high input voltage, the out-

put voltage will be low because the NMOS transistor is on. The PMOS transistor will be

turned off, but its drain-to-bulk voltage will be equal to the supply voltage, -VDD. The

resulting diode leakage current will be approximately IIeakage=Ads, where AD is the area

of the drain difision, and Js is leakage current density, set by the technology. For the

MOSIS 1.2 pm technology, Js is approximately 1-5 p~/pm2 (2S°C) [15]. For a one mil-


lion transistor chip there is an equal amount of source and drain diffusions, but only one

out of two has leakage. Assuming the average area of a drain is 10 ~ r n ~ , then the average

total leakage current is 25 pA. Thus power dissipated is below LOO pW. For chips with a

power dissipation greater than lûmW, the leakage contributes less than 1%. However, for

low-power ICs in the ImW range, this component can becorne a significant fraction.

Subthreshold leakage occurs under sirnilar conditions as the diode leakage. The

magnitude of the subthreshold current is both a function of process, device sizing, and

supply voltage. The process parameter that predorninately affects the current value is V' Reducing V, exponentiaily increases the subthreshold current. For a typical process with

V, of 0.7 V - 0.9V, the subthreshold current magnitude ranges from SM) fA - 10 PA, which

is similar in magnitude to the diode leakage current. Subthreshoid current is dso propor-

tional to transistor device size, and an exponential function of the supply voltage. Thus,

the current can be minirnized by reducing W/L, and by reducing the supply voltage.

Pleakage, which can be major under stand-by conditions, is expressed as:

Since the dynamic power generally consumes the largest share of the system's

power budget and because PdyllLUniC is proportional to vm2, reducing the supply voltage is

clearly the easiest and most efficient way to reduce the dynamic power dissipation. Mini-

mizing is of the utmost concem in battery operated portable electronic equipment

with long down-times such as laptop PCs and cellular phones and is best minimized by

reducing the diode and subthreshold leakage current as well as the supply voltage.


1.4 Low Power Digital Design Methodology

To optimize the power dissipation of digital systerns, a low power design method-

ology should be applied throughout the entire design process. The basics of this prwess

are shown in Figure 1.7. wthin each design level, energy and power c m be reduced in a

number of ways [2,18]: device physics (lowering the supply voltage, reducing device

thresholds), logic design style (fully static or pass transistor logic), circuit design style

(back gate forward bias, self-adjusting threshold voltage [19,20]), circuit optirnization

techniques (sizing transistors to minimize capacitance and short circuit current [2 l]),

architecture (powering down sections not being used, slowing the clock down during peri-

ods of low activity), aigorithm (minimizing the number of operations required to perform

a specific function), and system (multichip modules to reduce connection lengths).

Fig. 1.7 Power Reduction Design Space [2]

1.5 Low Power Analog Circuits

Technology feature size scaling and the need to reduce the power consumption in

large digital systems both push in the direction of using lower supply voltages. From a

fundamental viewpoint, in analog systems, operating at reduced power supply does not

necessarily result in lower power dissipation. As the supply voltage is scaled, the noise

must be scaled correspondingly to maintain the sarne dynarnic range. Since the fundamen-

ta1 noise power is proportional to kT/C, this requires scaling up the capacitance, C, with

the square of the supply voltage, precisely canceling any advantage that would accure in

A 1V Low-Power CMOS Rocess University of Toronto

Introduction Page 10

power dissipation assurning that the power consumption was dominated by dynamic

power (as for digital circuits) [22,23].

Power is needed in analog circuits to maintain the energy of the signal much larger

than the thermal noise energy to achieve the required signal-to-noise ratio (S/N). The

power necessary to create a sinusoidal signal of peak-to-peak amplitude Vpp and fre-

quency f across a capacitor C from a voltage source V' can be expressed as:

whereas the S/N ratio is given by:

Combining Eq. ( 1 -5) and Eq. ( 1.6) to elirninate C

which is a minimum when the amplitude of Vpp equals the supply voltage V,:

This absolute requires approximately a 10 fold increase in power for every 10 dB

increase of SM. As a result, performance-critical analog circuits will typically require

higher supply voltages than their digital VSLI counterparts. For this reason, purely analog

systerns are not expected to follow digital ones in the scaling of the supply voltage. In

mixed-signal VLSI circuits used for portable communication devices, however, anaiog

power supplies are likely to be set by digital ones since these devices are usually powered

by a single-cell battery [24,25].

A IV Low-Power CMOS Pmcess University of Toronto

htroduction page 11

1.6 Power Reduction through Process Technology

Although supply voltage reduction is an effective way of reducing the switching

component of power dissipation, it can lead to a severe penalty in circuit speed. For any

given technology, with both the capacitance and the threshold voltage king constant,

circuit delays increase as the voltage level is reduced. A simple first-order equation which

~redicts this dependance is as follows; A

where p is

channel)

the carrier mobility, C,, is the gate capacitance, Vt is the absolute threshold

voltage, I' is the average of the n- and p-channel transistor's saturation currents, and W

and L, the gate width and length respectively. If VDD is much greater than V, then the

delay is inversely proportional to the supply voltage and the latter term can be ignored.

The V, term however, causes the delay to increase rapidly for supply voltages near the

threshold voltage. A change from a 5V supply to a 1.W supply gives a 90% reduction in

power dissipation. However, the trade-off is increased circuit delay; a factor of 9 over the

SV case,

Since the objective is to reduce power consumption while keeping the throughput

of the overall system fixed, compensating for these increased delays at low supply volt-

ages is required.

1.6.1 Threshold Voltage Op timization

Correctly scaling the threshold voltage with the voltage supply is one of key steps

in the development of a Iow voltage CMOS process. Until recently, the threshold voltage

in most CMOS processes had been fixed at a fairly high potential -- 0.7V to 1.OV. For 5V

circuit operation, this has little effect on circuit delay, which is inversely proportional to

(Vm - vJ2. The main benefit of a high threshold voltage over a low threshold voltage is

that the subthreshold leakage current is reduced exponentially. While the total leakage cur-

rent in an IC is still well below the average supply current under operation, the reduced

subthreshold current prolongs the duration of stored charge in dynamic circuits, providing

more robust operation (due to longer leakage times). Thus there has been little reason to


Introduction page 12

reduce the threshold voltages until recently, with the decrease of supply voltages to 3.3V,

and the emphasis on low power design [ 151.

Reducing the threshold voltage allows the supply voltage to be dropped thereby

reducing the power dissipation without a loss in speed. For exarnple, using Eq. (1.9), a cir-

cuit operating at a supply voltage of 0.9V with V, = 0.25V will have approximately the

same performance as a circuit operathg at a supply voltage of 1.5 V and V, = 0.65V but

with dynamic power reduced by a factor of 2.8. Figure 1.8 demonstrates this trend with a

plot of propagation delay and normalized power vs. supply voltage for a 0.5 p m CMOS

two input NAND gate with fan-out of three.

i To 1:s io 2

Supply Voltage (V)

Fig. 1.8 Delay and Normalized Power vs. Supply Voltage for a CMOS 0.5 2 Input NAND Gate with Fan-Out Equd to Three [3]

Since a signifiant power improvement can be gained through the use of low

threshold MOS devices, how low the threshold voltages can be reduced must be

addressed. The energy-delay product, which describes the trade-off between energy and

operation speed, is a comrnonly used metric for comparing designs based on their energy

efficiency. The energy, E, required to charge a load capacitance, CL, in a CMOS gate is;



Assuming that the transistor operates mainiy in the saturation region, then the delay rd, (assuming long-channel transistors) for the sarne gate is given by Eq. (1.9). By differenti-

ating the product of Eqs. (1.9) and (1.10) with respect to Vm it follows that the minimum

energy delay product (E.tdmin) is achieved when VD&3Vr [26]. Thus for a 1V supply, the

optimum value for the threshold voltage is approximately BO0 mV when considering

both energy and delay.

1.6.2 Subthreshold Current (Subthreshold Swing) Reduction

The lower bound of the threshold voltage is set by the maximum acceptable leak-

age current at VGS = Ov For a fixed operating voltage, the optimum threshold voltage is

&en a compromise between an improvement in the dnvecurrent (which is proportional

to VDD - V,) and control of subthreshold leakage. Fundamental MOS theory assumes that

no drain current flows when the gate to source voltage is less than the threshold voltage of

the device. In a real device, the drain current decreases exponentially to zero as the gate to

source voltage falls below the threshold voltage. This subthreshold current IL, is expressed

as:

where n is the slope factor defined as:

C,, is the gate oxide capacitance and Cdepletion, the channel depletion capacitance. For

VDs larger than O. 1 V, the subthreshold leakage current is independent of Vm At gate volt-

ages below the MOS threshold voltage, the device ceases MOSFET-like behavior, and

begins acting more like a bipolar transistor. The channel is not strongly inverted and no

low conductance path exists between the drain and the source, thus minority carriers and

difision currents are dominant as in a bipolar device 1271. This concept is illustrated in

Fig. 1.9.

A 1 V Low-Power CMOS Process University of Toronto


Inversion

Fig. 19 Weakly inverted MOSFET - Bipolar Analogy

The weakly inverted channel of the MOS device in the subthreshold region acts as

the base of a bipolar transistor, while the source and drain act as the emitter and collecter

respectively. A capacitive voltage divider is formed by the gate oxide and the depletion

capacitances, and only a portion of the gate voltage is seen by the base region. This is the

origin of the ( 1 + CdepcltioJCox) term in Eq. (1.1 1).

Subthreshold behavior is characterized by the subthreshold swing denoted by S.

defined as the amount of gate voltage necessary to effect a decade drop in drain current.

The subthreshold swing can be expressed as:

A small value for S is desirable because this means that the device can mm off

quickly without undesirable leakage current. A low subthreshold swing equates to a rela-

tively large difference in the drain current just above and just below the threshold voltage,

tantamount to a sharp transition from ''ofl' to "on". Sharp transitions are important, espe-

cially for low supply voltages where the dynamic range is limited and noise margins are of

great concern. A typical value of swing for transistors in a modem CMOS process is

between 80-90mV/dec. The subthreshold swing of the MOS device varies directly with



the channel depletion capacitance and inversely with the oxide capacitance For this rea-

son, the swing decreases (i.e., improved) with a decrease in channel doping, as well as a

decrease in oxide thickness. The fundamental hmit for the subthreshold swing is approxi-

- O at 3ûûK. mately 2.3(kT/q) or oOmVldecade for CdcpletioJCOX =

This result has serious implications for scaling practices, since threshold voltages

which are scaled excessively yield very poor quaiity switches [27]. With the supply volt-

age reduced to IV, a symmetric 300 mV threshold voltage will ensure that the transistor

performance remains as high as possible at the reduced power supply. However, as illus-

trated below in Figure 1. 10, reducing the threshold voltage from V, to V,' increases the off-

state leakage current (IL to IL').

1 Low Threshold Deq

Fig. 1.10 Effect of V, Scaling on Subthreshold Leakage Current

Consequently, in addition to reducing the threshold voltage to maintain high per-

formance as the supply voltage is reduced, the subthreshold swing S must be kept to a

minimum to reduce the off-state leakage current.

A IV Low-Power CMOS Rocess University of Toronto


1.7 Low Voltage Low Power CMOS Processes

Development and implementation of a 1 pm CMOS process with a threshold volt-

age of 1: 300 mV and subthreshold swing of less than 80 mV/dec is the subject of this the-

sis. The key technological elements in this process are depicted Figure 1.1 1.

Gate Stack Gate Dielectric - Dual Worldunction Pdy - Thin Gate Oxide b lrnprove SC€ - Low Sheet Resistance and Current Drive - No Boron Penetmtion

LOCOS

L Sourcelürain Device Wells - Shdlow/Abnipt for - Low Ooped Weil to:

improved SCE - Minimire Subthreshold Swing - Low Sheet Resistance - Prevent Vertical Punchthrough

Fig. 1.11 Key Technology Issues in a LVLP CMOS Process

To obtain syrnmetric low threshold voltages as well as good 1 0 ~ O ~ c o n t r o l , optimi-

zation of the gate work function and channel doping profiles is a primary requirement. To

optimize the gate work function. the NMOS and PMOS transistors must be individudly

doped to fom n+ and p+ polysilicon gates. In conventional n-type polysilicon CMOS tech-

nology, both nchannel and p-channel MOSFET's require a ptype channel implant to pro-

duce the proper threshold voltage for Iow-voltage applications. Such implants convert the

pchannel transistors into buried channel devices. Even though buried-channel devices

benefit from improved mobility, surfacechamel devices are more resistant to threshold

voltage lowering, show better subthreshold cut-off characterïstics. and thus are better

suited for low threshold voltage operation [28].

Several processing issues are associated with dual-gate CMOS technology. These

include:



i) Lateral dopant diffusion between the n+ and the pC gate area The work hinction

of the gate is changed due to counter-doping from nearby opposite type gates.

This is promoted by the strapping silicide layer during thermal annealing, and

causes the threshold voltage of the devices to change accordingly [29].

ii) Boron penetration from the p-type polysilicon gate may diffuse through the gate

dielectric and into the channel region during dopant activation and annealing.

This penetration results in interface degradation, threshold voltage shifts and

reduced process control [30]. Boron penetration into the Si substrate is not only

a problem as gate oxide thickness is reduced, but aiso as Source-Drain (S/D)

junctions become shallower and require BF2 as an implant species. Boron diffu-

sion is enhanced by increasing the anneal temperature, annealing in a hydrogen

atrnosphere, or by fluorine incorporation into the gate oxide. Consequently, it is

very difficult to utilize CO-implantation of BF2 with low thermal annealing, to

achieve shallow source/drain junctions and degenerately-doped work functions.

To achieve degenerately-doped work functions, dopants implanted into polysili-

con must be unifomily distributed after source-drain drive-in so that the concen-

tration at the polysilicon/oxide interface is greater than 5x 10 A non-

degenerately-doped gate suffers from reduced current dnve as a result of an

effective increase in oxide thickness caused by depleted charge at the polysili-

codoxide interface. This phenornenon is referred to as the polydepletion effect

[30-351. As a result, a revision to the practice of simultaneously implanting the

polysilicon gate and source-drain junctions is necessary [26].

iii) Some key features of a dual-gate CMOS process are performance driven. Exarn-

ples are: 1) shallower source-drain junctions with more abrupt profiles to reduce

Short Channel Effects (SCE) and lower senes resistances; 2) The use of thin

gate oxides to increase dnve current and reduce SCE. The thickness of the gate

dielectric, however, will have to be a trade-off between the requirernent for

increased reliability against boron penetration and the desire to increase perfor-

mance; 3) The use of silicided S/D and gate regions with Tisi2 to reduce the

number of contacts required and the RC delay of wide devices.



1.8 State of the Art Low Voltage Processes

A sample of presently available state of the art low voltage processes is shown in

Table 1.2.

Table 1.1 Sample of Presently Available Low Voltage CMOS Processes

Texas Instruments (TI) and International Business Machines (IBM) were prompted

to reduce their power supply voltages from 5V to 3.3V and 2 . N respectively to increase

the reliability of their devices (see section 1.1). Reliability problems caused by hot carrier

effects, oxide breakdown, and gate induced leakage currents as MOS geometries were

scaled down to 0.5 pm or less, necessitated a reduction in the power supply voltage.

American Telephone and Telegraph (ATBrT), the Inter-University MicroElectronics Cen-

tre (IMEC)' , Stanford, and the Massachusetts Institute of Technology (MIT) al1 provide

IV low power processes. AT&T's process offers the highest level of integration and is

designed to be operated up to 3.3V. Stanford's process is the most aggressive in that it

incorporates a very thin, (49 A) gate oxide, dong with 0.25 Pm channel lengths and back-

forward biasing to adjust the threshold voltage. From the stand-point of an optimized

energy-delay product and low subthreshold swing (70 mVIdec), IMEC presently offers the

best low voltage CMOS process. MIT has recently developed a 1V low power process

with Silicon-on-Insulator (SOI) technology [IO].


vt CV)

0.8

0.4

0.2

L (m)

0.5

0.25

0.25

Company/ University

[ l u IBM [36]

AT&T 1371

Supply Voltage O 3 -3

2.5

I

x, S f

(A) (mvldec)

120

70 90

80

80

80


1.9 Thesis Objectives and Outline

The objective of this thesis is to design a low power 1 Fm CMOS process with a

threshold voltage of 300 mV and subthreshold swing of less than 80 mVldec for use in

battery-powered devices such as personal cornputers and mobile phones. The proces is to

be manufactured at the University of Toronto's Microelectronics Research Lab. Conse-

quently, the critical issues involved in the design of LVCMOS process are verified experi-

mentally. In Chapter 2, a 1 V low power CMOS process is presented. The L W CMOS

process specifications are given, technology issues are discussed, the processing steps are

described and the process and device simulations are presented. Chapter 3 presents the

experimental results obtained from measurements. Finally, conclusions dong with sugges-

tions for future work are presented in Chapter 4.

-- --- -- -



References

P. Verhofstadt, "The Emerging Discipline: Challenges and Oppominities in Low- Power Microelectronics Design", IEEE Symp. Low Power Electronics., p. 7, 1994.

A. Bellaouar and M. 1. Elrnasry, 'Zow-power Digitai W I Design", Kluwer Aca- demic Publishers, Boston, 1995.

J-M. Rabaey and M. Pedram "Low Power Design Methodologies," Kluwer Aca- demic Publishers, Boston, 1995.

A. Matsuzawa, "Low-Power Baseband Electronics", Technologies for Portable Systems, IEEE International Electron Device Meeting (IEDM), Short Course, 1995.

J. Montanaro, et al. "A 160 MHz 32b 0.m CMOS RISC Microprocessor," IEEE International Solid-St. Circuits Conference (ISSCC), Dig. Tech. Papers, pp. 2 14- 215, 1996-

C. F. Webb, et al., "A 400MHz SB0 Microprocessor," IEEE International Solid-St. Circuits Conference (ISSCC), Dig. Tech Papers, pp. 168- 169, 1997.

2. J. Lemnios, "Manufacturing Technology Challenges for Low Power Electron- ics". R&D Programs, Electronics Technology Office, DARPA, http://molo- thnis.sysplan.com/esto/Articles/LPEArticIe2.html1997.

J. S. Denker, "A Review of Adiabatic Computing", IEEE Symp. Law Power Elec- tronics, pp. 94-97. 1994.

A. Moini, "Vision Chips or Seeing Silicon", Center for GaAs VLSI Technology, The University of Adelaide, Australia, http://www.eleceng.adeiaide.edu.au/ Groups/GAAS/Bugeyelvisionchips/vision~chips/vision~chips.h~, 1996.

C. A. T. Salama, "LVLP Limitations, Impact on Device and Process Design", Course Notes for Low Voltage Low Power Integrated Circuit Design, MICRO- NET, Short Course, 1996.

J. M. C. Stork, 'Technology Leverage for Ultra-Low Power Information Systerns", IEEE Symp. Law Power Electronics, pp. 52-55, 1994.

B. Davari, RH. Dennard and G.G. Shahidi, "CMOS Scaling for High Performance and Low Power-The Next Ten Years", froc. IEEE - Special Issue on Law-Power Electronics, pp. 595-606, 1995.

R. H. Dennard, "Future CMOS Scaling: Approaching the Lirnits?', Future Fab International, FF-2, pp. 39-4 1, 1997.


Introduction page 2 1

A. P. Chandrakasan and R. W. Brodersen, "Low Power Digital M O S Design", KIuwer Academic Publishers, Boston, 1995,

T. Burd, "Low-Power CMOS Library Design Methodology", http://info- pad.eecs.berkely.eddinfopad-ftp/these// abstract.O.htm1, 1993.

H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wes- ley, Menlo Park, CA, 1990.

E. S. Yang, "Microelectronic Devices," McGraw-Hill Book Company, Toronto, pp. 287-290, 1988.

J. B. Bun; "Energy, Capacity, and Technology Scaling in Digital VLSI Neural Net- works", Stanford University, Interal Report, 199 1.

M. J. Chen et. al, "Back Gate Forward Bias Method for Low Voltage CMOS Digi- tal Circuits", IEEE Trans. E l e c ~ Devices, vol. ED-43, pp. 904-910, 1996.

T. Kobayashi and T. Sakurai, "Self Adjusting Threshold Voltage Scheme (SATS) for Low Voltage High Speed Operation", Custom Integrated Circuits Conference (CICC), Dig. Tech. Papers, pp. 274, 1994.

A. P. Chandrakasan, A. Burstein and R. W. Brodersen, "Low-Power Digital CMOS Design", IEEE J. of Solid-St. Circuits, vol. SC-27, pp. 473-484, 1992.

R. Castello, "Analog Supply Scaling. it Follow Digital?", IEEE International Solid-St. Circuits Conference (ISSCC), Dig. Tech. Papers, pp. 1 06- 107, 1 996.

T. B. Cho, D. W. C h e . C. S. G. Conroy and P.R. Gray, "Design Considerations for High-Speed Low-Power Low-Voltage CMOS Analog-to-Digital Converters", Analog Circuit Design, Kluwer Academic Publishers, Boston, pp. 49-7 1, 1995.

E. A. Vittoz, "Low-Power Low-Voltage Limitations and Prospects in Analog Design", Analog Circuit Design, Kluwer Acadernic Publishers, Boston, pp. 3-47, 1995.

T. Hayashi, "Low Voltage Low Power Floating Point Analog-to-Digital Con- verter", M.A.Sc. Thesis, University of Toronto, 1997.

S. C. Magierowski, "A PMOS Transistor for a L V CMOS Process", M.A.Sc. The- sis, University of Toronto, 1997.

J. C. Czilli, "BiCMOS Technology And Some Applications In High Performance Anthmetic Structures", M.A.Sc Thesis, University of Windsor, pp. 41-42, 1994.

G. J. Hu and R.H. Bruce, "Design Trade-offs Between Surface and Buried-Chan- ne1 FET's", IEEE Tram Electron Devices, vol. ED-32, pp. 584-1985.

- -


Introduction Page 22

D. C.H Yu, K.H. Lee et al, 'Wew Robust n+/p+ Duai-Gate CMOS Technology ûptimized for Low Power Operation", International J. of High Speed Electmnics and System, BS-5, pp. 135- 143, 1994.

D. C. H. Yu, H. D. Lin, C. McAndrew and K.H. Lee. "Low threshold Voltage CMOS Devices with Smooth Topography for 1 V applications", Interanational Electron Device Meeting (IEDM), Dig. Tech. Papers, pp. 489-492, 1994.

K. S. Krisch. M. L. Green et. ai, 'Thickness Dependance of Boron Penetration Through O*- and N20-Grown Gate Oxides and its Impact on Threshold Voltage Viuïation", IEEE Trans. Electron Devices, ED-43, pp. 982-989, 1996.

R. B. Fair, "Oxide Thickness Effect on Boron Diffusion in Thin Oxide p+ Si Gate Technology", ZEEE Electron Device Le#., EDL-17, pp. 242-243, 1996.

J. R. Pfiester, L. C. Parillo, and F. K. Baker, "A Physical Mode1 for Boron Penetra- tion Through Thin Gate Oxides from p+ Polysilicon Gates", IEEE E1ectr.m Device Lett., EDL-11, pp. 247-249, 1990.

C. Y. Wong, J. Y. -C. Sun. et al, "Doping of N+ and P+ Polysilicon in a Dual-Gate CMOS Process", IEEE International Electron Devices Meeting (IEDM), Dig. Tech. Papers, pp. 238-24 1, 1998.

N. D. Arora, R. Rios and C. -L. Huang, "Modelling the Polysilicon Depletion Effect and Its Impact on Submicrometer CMOS Circuit Performance", IEEE Tms. Electron Devices, vol. ED-42, pp. 935-942, 1995.

R. A. Chapman, C. C. Wei, et al, "0.5 Micron CMOS for High Performance at 3.3V', IEEE International Electrun Device Meeting (IEDM), Dig. Tech. Papers. pp. 52-55. 1988.

R. Davari et al, "A High Performance 0.25 um CMOS Technology", IEEE Interna- tional Electron Device Meeting (IEDM), Dig. Tech. Papers. , pp. 56-59, 1988.

2. Chen, I. Burr, J. Shott and I. D. Plummer, "Optirnization of Quarter Micron MOSFETs for Low VoltageLow Power Application", lEEE International Elec- tmn Device Meeting (IEDM), Dig. Tech. Papers, pp. 63-66. 1995.


Cbapter 2 - Rocess and Device Design of a 1V Low Power CMOS frocess Page 23 -

CHAPTER 2

Process and Device Design of a 1 V Low Power CMOS Process

2.1 Introduction

Device fabrication is a lengthy and expensive process. Therefore, it is not efficient

or economical to try and optirnize the device structure by repeated fabrications. Fomi-

nately, there are cornputer ai& that yield process data and device characteristics in houn

rather than months as is the case for fabrication [l]. SUPREM-3 for exarnple can numeri-

cally estimate the diffusion, segregation, and implantation of dopant impurities as well as

the growth rate and deposition of oxide and nitride layers on several different semiconduc-

tor materials [2]. However, since the default models are not universaily applicable, it is

necessary to calibrate these with experimental data to get accurate results. Tuning the sim-

ulator rnay involve matching simulated doping profiles to SRP (Spreading Resistance Pro-

files) or SIMS (Secondaiy Ion Mass Spectrometry) measurements and bird's beak

geometry to SEM (Scanning Electron Microscope) pictures. Even without this calibration,

the simulator still provides more accurate information than would be obtained from simple

analytical formulae. So while the simulator may not be entirely accurate, it is very useful

for gaining insight into the dominant variables in the process flow.

To obtain device characteristics, a sirnulator such as MEDICI is required. It uses as

input device cross-sections with appropriate doping profiles and solves for terminal volt-

ages and currents. It also performs small signal analysis so that AC device parameters such

as transconductance and cut-off frequency c m be determined. Device simulations are very

useful for gaining insight into certain device characteristics (e.g.. threshold voltage roll-off

at deep submicron channel lengths) and for investigating trends (e.g., effect of changing

substrate doping on threshold voltage) [ 1 1.

In this chapter. the process specifications are given, the design issues are discussed,

the processing steps are described and the process and device simulations are presented.

' TSUPREM-3 and MEDICI are trademarks of Technology Modeling Associates, Inc. (T'MA)


Chapter 2 - Process and Device Design of a IV Low Power CMOS Process page 24

2.2 CMOS Architecture

A cross-section of the low voltage CMOS device structure is s h o w in Fig. 2.1.

Figure 2.1 will serve to define the main elements of the CMOS active and field devices as

weil as to describe the major device properties of the 1 prn technology under discussion.

The 1 pm mentioned here represents the physical gate length on a finished wafer (Lse).

Source

1 p m CMOS Technology

Gate Drain Drain Gate Source

1 N - WELL p-chanhel stop

P-type Substrate

Fig. 2.1 CMOS Active and Field Device Structure

A CMOS process architecture has to provide both n- and p-channel transistors on a

Si wafer. Unlike a p-well or a n-well CMOS technology in which case only one of the

device types is optimized, a twin-well CMOS technology provides the basis for the sepa-

rate optirnization of n- and p-devices [3,4]. Furthemore, twin-well CMOS technology

allows for the close placement of complementary devices, the need for only a single litho-

graphie mask step to form both well types, and the choice of either substrate type for dif-

ferent circuit applications with essentially no change in process Row.

An 18-20 Q-cm ( - 5 . 5 ~ 1 0 ' ~ cm3) p-type (100) wafer was chosen as the starting

substrate. The low background concentration allows for the fabrication of low doped

(-2x1 016) n- and p-wells. The low doped wells are necessary to achieve a 300 mV thresh-

old voltage and minirnize the subthreshold swing (< 80 mV/dec). The light well doping is

also used to achieve low junction capacitance and low body effect y, which are also essen-

tial for low voltage operation. The n-well depth (2 pm) is designed to be deep enough to

avoid vertical punchthrough between the n-well and the p+ (drain) depletion layers below -


Chapter 2 - Process and Device Design of a IV Low Power CMOS Fn>cess Page 25

3 V. The gate work function (p+ polysilicon) for the PMOS transistor is optimized. The

thickness of the polysilicon gate layer is selected to be 0.3 pm, out of consideration for

surface topology and poly wire resistance. To reduce the spacing between devices and pro-

vide better isolation, LOCOS isolation with a p-channel stopper (p-guard) is used. This

process features shallow source/drains (0.2 pm) junctions as weli as 140 A gate oxide

(T,,) to lirnit short-channel effects and low gate and source sheet resistances (Tisi9 to

minimize the delay and increase the current drive of the devices. Enabled by the low volt-

age environment, no Lightly Doped Drains (LDDs)' are incorporated. Aluminum is used

for metallization. Titanium-Tungstem (TiW) is sputtered before aluminum deposition to

prevent the penetration of aluminum through the shallow source/drain junctions. The pro-

cess specifications are summarized in Table 2.1.

Table 2.1 Low Voltage CMOS Device Parameters

1 Field Threshold Voltage 1 v~ 1 - 6 1 V 1

Parame ter

Threshold Voltage

1 SubthreshoId Swing 1 S 1 < 80 1 mV/dec 1

Symbol

vt O

L

P-Wef l Surface Concentration I NPweii I

Gate Oxide Thickness

N-WeIl Depth

N-WeII Surface Concentration

1 Poly Gate Thickness 1 TG 1 0.3 1 P 1

Vaiue

300

1 Poly Gate Sheet Resistance (with Tisi9 1 % I c 3 O 1 ~ I

Units

mV

TOX

X n w e ~ ~

N n w e ~ ~

'LDDS arr low resistivity regions adjacent to the source and drain to =duce the electric field in the channel

140

- 2

2 . 3 ~ 1 0 ' ~

- - -p --

Source/Drain Junction Depth

S/D Sheet Resistance (with Tisi2)


A W

cm-3

-- -- - - -

Crm ! X I

xj

%d

- - -

0.2

< 10

-ter 2 - Rocess and Device Design of a IV Low Power CMOS Rocess page 26

2.3 Design Considerations for a 1V Low Power CMOS Process

23.1 Short Channel Effects

The evolution of average minimum feature size F for state-of-the art microchips

vernis calendar year Y is illustrated in Fig. 2.2. In 1960, F was about 25 Pm. By 1980, it

had scaled down to 2.5 p. If the historical rate of evolution continues throughout the

1990's, the average minimum feature size F will be about 0.25 pm in the year 2000.

0.001 1960 1970 1- 1- 2ûûû #no 2030

Calendar Yeer, (Y)

Fig. 2.2 Average Minimum Feature Size F Versus Calendar Year Y [5 ]

As the channel length in a MOSFET is reduced, departures from long channel

behavior may occur. These departures, the shortthannel effects, arise as a result of a two-

dimensional potential distribution and high electric fields in the channel region. Because

short-channel effects complicate device operation and degrade device performance, these

effects need to be eiiminated or minimized so that a physical short-channel device can pre-

serve the "electrical" long channel behavior.

The minimum channel length Lmin for which long-channel subthreshold behaviour

can be observed is found to follow a simple empirical relation [6]:


Chapter 2 - Process and Device Design of a 1V Low Power CMOS Pmcess Page 27

where xi is the junction depth in p, t,, is the oxide thickness in A, and (wS + wD) is the

sum of source and drain depletion widths in a one-dimensional abrupt junction formula-

tion. Figure 2.3 shows a plot of Eq. (2.1) compared to expenmental results and two-

dimensional cornputer simulations.

< LONG CHANNEL REGION>

- io E 4. Y

e - E

J

Fig. 2 3 Minimum Channel Length Versus xj*bx(ws + wD)2 [6]

Al1 devices with channel lengths that lie below the line are effectively shonchan-

nel devices, and al1 devices with channel lengths above the line are longchannel devices.

Based on Eq. (2. 1). a 1 pm MOSFET should have approximately a 200 A gate oxide. 0.2-

0.25 pm junctions. and 2-3x10'~ cmJ substrate doping density to be long channel.

2.3.2 Threshold Voltage

The key in implementing low threshold voltage transistors in a low voltage CMOS

processes is the optimization of the gate work function and channel doping profiles for

both n- and p-type devices. The need for a p-type (n-type) gate for the PMOS (NMOS)

transistor can be explained by examining the equation for the threshold voltage defined as

where

A 1V Low-P,ower CMOS Rocess University of Toronto

Chapter 2 - Rocess and Device Design of a 1V Low Power CMOS Process page 28

OMS is the metal-semiconductor work-function difference, OF is the fermi potential, Qg

is the effective oxide charge, QB is the semiconductor bulk charge, Di is the dose of the

channel threshold adjust implant and Co, is the gatr oxide capacitance.

By refemng to Eq. (2.1) and the using values for QMS, OF and Q$il shown in

Fig. 2.4, it can be shown that a PMOS(NM0S) transistor with a p+(n+) polysilicon gate

requises an n(p) -type threshold voltage adjust implant to attain a -(+) 300 mV threshold

voltage, while a PMOS transistor controlled by an n+ polysilicon gate needs a counter dop

ing ptype threshold adjust implant to achieve the same threshold voltage.

(a) This work: PMOS I NMOS 0

LOw Voltage PMOS: N+ Poly Gate@

10Y

leU

le"

10- 10" 10' loY IO" 10- 10"

Substratt Doping Concentration, NB (cm'?

(4

Figo 2.4 (a) 45,,,s VS. NB for Poly and Al gates (b) NB vs. bF (c) IQg/ql vs. NB

P-type threshold adjust implants move the channel of the PMOS device away from

the surface (i.e., away frorn the control of the gate) and into the bulk of the semiconductor.

A "buned channel" device of this sort, as shown in Fig. 2.5, exhibits a higher rninority car-

- - - - - - - - - - . . -


Chapter 2 - Rocess and Device Design of a IV Low Power CMOS Process page 29

ner low-field mobility (since there is less surface scattering of mobile charge carries with

the Si-SiO2 interface), and it seems that they show advantages over surface-channel

devices in terms of reliability issues as well [7]. However, because the current path is

moved away €tom the interface, device transconductance is reduced; essentially cancelling

any benefit of a higher minority carrier mobility and making two-dimensional effects like

drain-induced barrier lowenng, the threshold voltage roll-off with decreasing channel

Iength and source/drain punchthrough more pronounced.

Fig. 2.5 Buried Channel PMOS transistor (a) Cross-section (b) Depletion regions (c) Doping profile (d) Equivalent circuit

The subthreshold swing for a buned channel device is given by tke capacitance

divider ratio formed by the gate oxide and the depletion capacitances (Fig. 2.5(c)) [6]

. .


Chapter 2 - Rocess and Device Design of a IV Low Power CMOS Process page 30

Consequently, buried channel devices suffer from a much degraded subthreshold

swing as compared to surface channel devices rnaking them unsuitable for Iow power

applications [8].

A challenging problem in designing CMOS circuits is to avoid a condition known

as latchup, in which parasitic bipolar action causes a low-resistance path between the

power supply and ground. The source of the latchup effect is depicted in Fig. 2.6.

a) Schematic of parasitic resistors and transistors in a CMOS circuit

v, b) Equivalent circuit

Fig. 2.6 Source of Latchup in CMOS

The CMOS structure has inherent pnp and npn parasitic bipolar transistors fomed

by the p-well-p-substrate, the n-well and an active source/drain junction in each well.

They are different from active bipolar devices in a BiCMOS structure. The collecter of

either parasitic transistor is connected to the base of the other, forming a pnpn parasitic

SCR (Semiconductor Controlled Rectifier). Under certain conditions such as terminal

overvoltage stress, transient displacernent currents or ionizing radiation, lateral currents in

the wells can cause sufficient ohmic drop to forward bias the ernitter-base junction and

activate both bipolar devices. When the current gain product (B npnpp,) of the two bipo-

lar transistors is sufficient to cause regeneration, the pnpn SCR can be switched to a low

impedance, high current state. This condition is defined as latchup. Latchup, can result in

momentary or permanent loss of circuit function [9].


Chapter 2 - Rocess and Device Design of a IV Low Power CMOS h e s s page 3 1

By examining the physicai structure of the parasitic devices, the necessary and suf-

ficient conditions for latchup to occur are that:

-The lateral pnp and vertical npn base emitter junction be forward biased

-The supply current be sufficient to sustain latch-up

Lmtchup in a IV CMOS Process

Ractical techniques cornmonly used to avoid latchup include the use of retrograde

wells, guard rings, butted contacts, thin epitaxial layer structures on heavily doped sub-

strates, trench isolation and increased n+-to-p+ spacing [I l] . These techniques however

require that certain design rules be followed to guarantee the avoidance of laichup, mles

that enlarge the design and may make it slower. Latch-up c m , however, only be sustained

at a voltage larger than

where V , is the collector-emitter voltage of the pnp-transistor (> 0. IV), V , is the base-

emitter voltage of the bipolar npn transistor (-0.7V) and the R's are parasitic resistors

according to Fig. 2.6. Using reasonable values far these parameters, we find that

Vhold>L.SV This means that we can expect no latch-up below 1.5V making latch-up at a

1 V supply, relatively unlikely [IO].

2.3.4 MOSFET Isolation

In MOS technology, isolation is commonly fonned using a thick oxide and/or

heavily doped Si layer in the field region arnong active MOSFETs (Fig. 2.1). The thick

oxide is often called the field oxide and the heavily-doped region is often referred to as the

channel stop. Field oxide with a possible polysilicon/alurninum interconnect creates para-

sitic MOSFET structures as illustrated in Fig. 2.7. Here the source/drain of the parasitic

transistors are existing source/drains and the gate is a metal or polysilicon interconnect

overlapping the two sourceldrain regions. This field isolation works well for active MOS-

FETs only if the Si surface in the active channel region is not allowed to invert. If the bias



on the polysilicon~aluminum interconnect induces the channel under the field oxide then

isolation is lost. Obviously such a situation must be prevented by proper process design.

p+ to paibstrate

* Field Oxide

- - 1 I I l 1

-- p-weu

n-well

p-substrate

Fig. 2.7 Parasitic Field Devices in CMOS

Field Threshold Voltage

The threshold voltage of the parasitic filed oxide transistor VtF is given by the same expression as the active MOSFET

where t o x ~ is the thickness of the field oxide and Vm, the flatband voltage is

The field threshold voltage increases with an increase in oxide thickness or substrate doping concentration according to Eq. (2.5). Consequently, the threshold voltage of this transistor is much higher than that of the regular transistor. For a 1V process, a prop- erly designed field device threshold voltage, VrF. should be about 6V, at least an order of magnitude higher than the threshold voltage [1 I l .

Ion Implantation of the Fielii Area

An additional p-type implant is being used over the p-well (i.e., p-channel stopper) to increase VtF because dunng field oxidation, boron experiences both segregation and oxidation enhanced difision in such a way that the surface concentration decreases. Depletion of boron at the surface decreases VrF This implies that the peak of the boron

- --

A 1V Low-Power CMOS Procas University of Toronto

Chapter 2 - Process and Device Design of a 1V Low Power CMOS Process page 33

implant must be deep enough that it is not absorbed by the growing field oxide interface. Thus relatively high boron doses are needed (mid 1012 to l0I3 atorns/cm2) to achieve acceptable field threshold voltages. The opposite effect is observed for phosphorus, used to dope the n-well. Dunng LOCOS oxidation, phosphorus tends to pile-up increasing the surface concentration and the absolute value of VtF [12- 131.

23.5 Integration Issues

By using a silicide layer not only over the polysilicon and source/drains, but also

for the interconnections, an undesired interaction between neighboring gates of different

type c m occur in dual-gate CMOS circuits. During annealing the dopants segregate at the

silicide layer and can travel easily through it towards a neighboring gate of opposite type.

After the out-difision ftom the siIicide into the second gate they can compensate the

desired impurities, thus making the second gate low-doped. The worst cases are when

small-area gates lie close to large area gates. This inter-diffusion can be quite pronounced

and cm posses a serious limitation to the temperature budget allowed in this and subse-

quent processing steps [14].

Figure 2.8 ilIusvates two comrnon structures that have been demonstrated to work

effectively in suppressing the potentiai poly-diodes when two different poly materials are

connected togethec

(a) Gate Strap ,TiN

. -

FOX

(b) Gate Shunt ,TiN (or WSi,)

Fig. 2.8 A Dual-poly gate CMOS process is achieved by using a metal layer as part of the gate stack (a) to strap the two discomected poly matenais so that there is no interdiffusion path (b) to shunt the two connected poly materials by carefully selecting the process conditions to control the inter-diffusion [15].


Chapter 2 - Process and Device Design of a 1V Low Power CMOS Rocess Page 34

Rather than increase the complexity of the process by incorporating a gate strap or

gate shunt material, aluminum is used to ohmicdy connect the two types of gates

together.

2.4 Process Description

The process steps for fabricating the LVLP CMOS process are illustrated in

Fig. 2.9. Twelve masks are used in this process. The process was arrived at through item-

tive simulations to achieve the desired specifications.

The process starts with a 18-20 R c m (-5x loi4 cm") (100) oriented boron-doped

wafer. In general, p-type substrates are preferred to n-type because they are less sensitive

to process induced material defects [3]. The twin-wells are fomed in a self-aligned man-

ner by first defining an oxide-nitride sandwich (MASK #1) as shown in Fig. 2.9(a). A thin

pad oxide (400 A) is grown. Silicon nitride (Si3N4) (1200 A) and a thin (500 A) oxide

layer are then deposited and annealed (lOOO°C, 10 minutes). The pad oxide or buffer

oxide is used to cushion the transition of stresses between the silicon substrate and the

deposited nitride during oxidation. This stress is due to the mismatch of thermal expansion

coefficients of the Si substrate and the nitride and due to the volumetric increase of the

growing oxide. Silicon nitride acts as a barrier to the diffision of the oxidant, preventing

oxidation in selected regions of the silicon. This technique is called LOCal Oxidation of

Silicon (LOCOS) .

Photoresist is pattemed using the first mask: the NWELL mask. Openings in the

oxide are dry etched using RIE with Cm3 and C2F6 gas ( 1 : I ), hereafter referred to as

freon plasma. Photoresist is removed and the silicon nitride is wet etched with hot phos-

phoric acid (1 6 0 ' ~ ) . To ensure a surface concentration of -2x 1016 and - 2 pm deep

n-well, a low energy phosphorus (3.5x1012 cmJ, 25 keV) implant and an initial 7 hou

drive-in ( 1 LOOOC) in a nitrogen arnbient is performed.



(a) MASK #I NWELL

PHOSPHORUS

(b) SELF ALIGNED PWELL

BORON

I + + + ,, P - WELL 1 - p

I P-type Substrate I

(c) MASK #2 ACTIVE

N - WELL I \

P-type Substrate

(d) MASK #3 PGAURD

BORON

I P - WELL

N - WELL P-type Substrate u

(e) MASK #4 NMOS -VT ADJUST IMPLANT

Gate Oxide

FOX 1 I P - WELL

N - WELL I b P-hm Substrate I

(f) MASK #S PMOS -VT ADJUST IMPLANT

ARSENIC - 1 1 1 1 1 FOX I

P - WELL N - WELL P-type Substrate

(g) MASK #6 N+ POLY IMPLANT

PHOSPHORUS

FOX

P - WELL N - WELL , P-tspe Substrate

(h) MASK #7 P+ POLY IMPLANT

BORON

-- -



(i) MASK #8 GATE DELINEATION

N - WELL

(j) MAsK #9 N+ S/D IMPLANT ARSENIC

b!! N - WELL 1 P-type Substrate

(k) ACTIVATION OF N+ S/D AND GATE IMPLANTS


O) MASK #10 P+ S/D IMPLANT

BORON

P - WELL N-WELL

1 P-tMe Substrate 1

(m) SWS FORMATION AND P+ S/D ACTIVATION

POWELL N - WELL 1 P-type Snbstrate 1

(n) SALICIDE

I \

P-type Substrate

(O) MASK #Il CONTACT OPENINGS

O 1 1 !' FOX \3

P - WELL N - WELL

(p) MASK #12 METALIZATION

-


Fig. 2.9 LVCMOS Process Flow



Self-Aligned O d e + P W E U Implant

M e r drive-in, the n-well is selectively oxidized: dry ( 1 100°C, 10 minutes), wet

(1 100°C, 22 minutes), dry ( 1 100°C, 10 minutes), which results in a thick (-3500 A) align-

ment oxide everywhere except where there is nitride. This oxide serves to act as a screen

to the pwell implant and as drive-in on the n-well. The 500 A of deposited oxide and the

remaining nitride is then stx-ipped off leaving - 3000 A over then n-well regions and 400 A over the p-well regions. This differential thickness is then used to "self-align" the p-well-

implant by selecting an energy low enough to be screened by 3000 A of oxide (blocked

out of the n-weil areas) yet high enough to penetrate the 400 A of oxide (to doped the p-

wells). The pwell is implanted using boron (6x1012, 15 keV) self-aligned to the oxide

masked n-well as shown in Fig. 2.9(b). The n- and pwells are then driven-in (3 hours,

1 100°C) in an nitrogen ambient to a final depth of 2 pm and 1.5 pm respectively. Follow-

ing drive-in, the remaining oxide is completely removed by wet etching in hydroduoric

acid.

A thin pad oxide (400 A) is grown at 900°C. Silicon nitride (1200 A) is then

deposited and annealed (10OO0C, 10 minutes). Photoresist is pattemed using the second

mask: the ACTIVE mask to define the active device areas. This leaves the field region

exposed as shown Fig. 2.9(c).

The purpose of the p-guard mask is to block the p-guard implant from the n-well

areas. Constraints on the p-guard implant are as follows: 1) The implant energy may not

be so high that it penetrates the unmasked device wells; 2) The implant energy should be

as high as possible to move the p-guard implant fwther into the silicon so that only a small

amount of boron is segregated into the oxide during field oxidation; 3) The channel stop

doping cannot be too heavy or it will cause high source/drain-to-substrate capacitances

and reduce source/drain-to-substrate pn junction breakdown voltages.

The nitride is dry etched with fieon and the photoresist is removed. The field

region is implanted with boron (8x10'~ cm-2, 30 keV) as shown in Fig. 2.9(d). The g

guard implant sets the threshold voltage undemeath the field region. A three step oxidation


Chapter 2 - Process and Device Design of a 1V Low Power CMOS fmcess page 38

is perforrned: dry (950°C, 10 minutes), wet (9w0c, 250 minutes), and diy (g()O0C, 10

minutes), which results in a thick oxide (7000 A) everywhere except where there is

nitride. This long oxidation step also drives-in the boron implant in the field region. The

remaining oxide and nitride are then removed by wet etching.

GATE OXIDATION

During the growth of the field oxide, Kooi et al. 1161 discovered that a thin layer of

silicon nitride can form on the silicon surface (i.e., at the pad oxide/silicon interface) at the

edges of the active regions as a result of the reaction of NH3 and silicon at that interface.

NH3 is generated from the reaction of H20 and the masking nitride layer during the field

oxidation step. It diffuses through the pad oxide and reacts with the silicon to form silicon

nitride spots or ribbon (sometimes called white ribbon).

Fig. 2.10 Kooi's Mode1 for Explaining Nitride Growth Under the Gate Oxide

Gate oxide growth is impeded at locations where nitride has formed. One way to

eliminate this problem is to grow a 'csacrificial" gate oxide after stripping the masking

niû-ide and pad oxide. and then remove the sacrificial oxide before growing the final gate

oxide [Il]. A sacrificial oxide (500 A) is grown at 9 0 0 ~ ~ prior to gate oxidation to remove

this white nbbon caused as a result of the previous LOCOS step.

The gate oxidation is a very critical part of the process for CMOS transistors. The

target oxide thickness is 140 A. The gate oxide is grown (900°C. 34 minutes) in dry O2

with 2% HCI. The HCl is used to eliminate mobile charges, Q, localized in the S i 4 . The -- - -

A 1V Low-Power CTMOS Process University of Toronto

Chapter 2 - h e s s and Device Design of a 1V Low Power C ' O S Rocess Page 39

origin of this charge is related to the presence of positive alkali metai ions such as potas-

sium (K+) and sodium (Na+). The name "mobile" implies that these charges can move

within the S i 4 , although typicaliy, an elevated temperature and an elecaic field is

required for this movement This is immediately followed by a ~ 0 5 0 ~ ~ . 30 minute anneal

in a nitrogen ambient to reduce both the fixed oxide charge, Qf and interface trapped

charge, Q, [17]. Qfis aiways positive and its value depends on the details of the fabnca-

tion process (for example, temperature and ambient during oxidation) and on the crystallo-

graphic orientation of the substrate. The name "fixed" implies that Qfdoes not depend on

voltage.

To set the threshold voltage of each device, separate threshold adjust implants for

each device are perfomed. Photoresist is pattemed using the fourth mask: the NMOS - Vt

Adjust rnask. A low-energy, low dose (25 keV, 2 . 5 ~ 1 0 ' ~ ) BF2 implant is performed (Fig.

2.9(e)) to raise the surface concentration to (- 5 . 6 ~ 1 0 ' ~ cm"). BF2 is used because of its

low projected range. Photoresist is then removed.

MASK #5 PMOS- Vt @ust

Photoresist is pattemed using the fifth mask: the PMOS - Vt Adjust rnask. A low

energy, very low dose (25 keV, 3.8~10") As implant is performed (Fig. 2.9(f)) to set the

surface concentration to the required value (- 2.3~10 '~) . As was the case for BF2, Arsenic

is used becacse of its low implant range. The photoresist is then removed.

AMORPHOUS GATE FOIpIiMATION

The following summaruRs the options available to provide a process within which

degenerately doped polysilicon gates can be formed without any penetration of dopants

through the gate oxide.

1) Low Pressure Chernical Vapor Deposition at temperatures below 600°C can be

used to deposit arnorphous silicon (as opposed to polycrystalline silicon nor-

mally associated with the gate material) [18]. Amorphous silicon, without the

colurnnar microstructures, pinholes and small grain size of polycrystalline sili-

con, has been shown to retard the diffusion and channeling of dopants while

A IV Low-Power CMOS Rocess University of Toronto

Chapter 2 - Process and Device Design of a IV Low Power CMOS Process Page 40

improving the gate oxide integrity and activation efficiency of boron dopants

innoduced into it via ion implantation 1191. As a result, high temperature

anneals cm be applied to the gate to activate the dopants without causing the

dopants to penetrate through the gate oxide. Above 600°C, amorphous siiicon

recrystallizes to form a polycrystalline silicon [20].

2) Employing a nitrogen-doped-poly buffer between the p+ polysilicon gate and

the gate oxide has been shown to be an effective method of stopping boron pen-

etration through the gate oxide [21]. This process requires the deposition of a

very thin (- 50 A) highly doped (- ld') nitrogen doped poly layer before

depositing the polysilicon gate. The advantage of this approach is that boron

penetration is not dependent on the oxide thickness or processing conditions but

solely on the ability of the nitrogen-doped polysilicon buffer to stop the difi-

sion of impurities into the channel. This allows the gate oxide thickness to be

downscaled without fear of boron penetration and without altering the gate dop-

ing and fabrication conditions. Aside from the processing difficulties of repro-

ducibily depositing a very thin nitrogen-doped layer, a drawback of this

approach is the uncertainty in the efficiency of boron difision into the nitro-

gen-doped Iayer which can cause variations in the gaie work-function and lead

to inaccurate predictions in the threshold voltage 181.

3) An increasingly popular method of preventing boron penetration involves the

incorporation of nitrogen into the gate oxide. These nitrided oxide layers

involve first, a standard oxidation in an 4 ambient followed by rapid thermal

nitridation in a NO [22], N20 [23], or MI3 [24] ambient. The nitridation

changes the gate oxide into an oxynitride, SiOxNy with mole fractions x and y

dependent on the nitridation temperature and nitrogen concentration [25].

Although the nitridation of the gate oxide has been shown to improve the toler-

ance to hotcarrier injection, it usually results in an increase in the fixed oxide

charge density, degrades mobility, and requires a high thermal budget unless

special steps are taken [24,26,27].

In this work, the first option was used because it offered the simplest fabrication

requirements. As a result, 2900 A of amorphous silicon was deposited by LPCVD at

560°C for 75 min. at 300 mïorr.



Photoresist is patterned using the sixth mask: the N+ gate implantation mask. A

low energy, high dose phosphorus (30 keV, 5x 10") implant is performed (Fig. 2.9(g)).

The photoresist is then removed.

MASK 7- P+ Gaîe Imphntation

Photoresist is pattemed using the seventh mask: the P+ gate imphntation mask. A

low energy, high dose boron (30 keV, 5x10'~) implant is performed (Fig. 2.9(h)). Boron

was used as the implant species rather than BF2 because it has k e n shown that fluorine

actually enhances the difision of boron in silicon dioxide. This is significant since fluo-

rine-doped gate oxides have been shown to provide improved radiation hardness and hot-

carrier immunity, and a variety of techniques have acnially been developed to introduce

fluorine into the gate oxide. These include a pre-oxidation HF dip, oxidation in a fluorine

containing arnbient and F implantation (usuaily with BFd into the gate followed by a fluo-

rine difision. The problern with fluorine enhancing the diffusion of boron through the

gate oxide is that the boron collects below the gate oxide and can change the threshold

voltage of the device, as well as degrade the oxide quality. When F is present in the gate

oxide fiom etching residues or BF2 implants, the role of F is to break the Si-O bonds so

that reactions with O are possible and additional defects called peroxy linkage defecfs

(PLDs) are forrned. This in tum enhances the diffusion coefficient of boron in S i 4 with a

F2JIR dependence [28,29]. So, while Ruonne cm boost the performance of the gate

oxide, the boron difision is a very nasty side-effect.

MASK #8 - Gate Delineafian

Before photoresist is deposited and patterned, a thick layer of silicon nitride is

deposited (3000 A) on top of the amorphous silicon gate to protect it from sourceldrain

boron (PMOS) and arsenic (NMOS) implants. Photoresist is patterned using the eighth

mask: the Gate-Etch mask. The n' and p+ polysilicon gates are defined simultaneously in

a two step procedure: 1) Silicon nitride in the exposed areas is dry etched by RIE using

freon in 30s intervals to prevent photoresist bum-out; 2) After the Si3N4 is etched, the

remaining resist is rernoved with acetone. The wafers are then dipped in buffered hydrof-

lounc acid for 30s and dried before retuming them to the etch chamber for polysilicon

etching. Once within the evacuated chamber, wafers are subjected to a short 15s oxide etch -



with freon to remove native oxide and the chamber is cryopurnped to decontaminate it pri-

rnarily of atmospheric water vapor. Al1 the polysiIicon and some of the Si3N4 masking

material is then etched with a CI2 and BC13 plasma (1 : 1.5) as show in Fig. 2.9(i). This is

necessary because the selectivity (the ratio of the vertical etch-rate into the material to be

etched to the rate of erosion of mask materid [30]) of this plasma to both Si3N4 and SiO2

(i.e., gate oxide) etching is dramatically improved as compared to a freon one. Using a

freon plasma to etch the polysilicon would create considerable damage to the Si substrate

directly beneath the gate oxide over source/&ain areas.

One of the limitations of reactive ion etching is residual damage left in the sub-

strate after etching. Both substrate damage and chemicd contamination are senous issues

1301. It is aIso impossible to prevent some of the gate oxide underneath the polysilicon

gates from k ing etched and most often results in damaged gate oxide (at least at the

edges). To remove this darnage, the Si substrate and gate oxide are reoxidized using Rapid

Thermal Activation (RTA) in a ~ e a t ~ u l s e ~ ~ 410 at 90°C for 2 min. in an O2 ambient.

UASK #9 - N+ Source/Druin Implantation

Two hundred angstroms of Si3N4 are deposited. Photoresist is patterned using the

ninth mask: N+ SourceIDrain Implantation mask. A high energy, high dose (1 10 keV,

4x10'~) arsenic implant is performed to fonn the N+(NMOS) source/drains (Fig. 2.9(j)).

The photoresist is then removed.

GATE, Vt-adjust and N+ Source/Druin Activation

Since RTA has been show to be very effective in reducing boron ion penetration

[3 11, a very high temperature RTA ( 1 1 OO°C) for 20 sec. is applied to simultaneously acti-

vate al1 the dopants in the nf and p+ polysilicon gates, the threshold voltage adjusmient

implant and the n+ sourceldrain arsenic implant (Fig. 2.9B)). A high temperature RTA

was used in order to adequately activate al1 these implants without allowing the dopants

sufficient time to diffuse throughout the device [3 1,321. This high temperature. short-time

anneal is intended to strike a balance between avoiding the poIydepletion effect in the

gates and preventing boron penetration into the channel.

A 1V Low-Power CMOS Rocess U~versity of Toronto

Chapter 2 - Rocess and Device Design of a 1 V Low Power CMOS Rocess page 43

Four hundred angstroms of Si3N4 are deposited. Photoresist is pattemed using the

tenth mask: the P+ Source/Drain Implantation mask. A low energy, moderate dose (25

keV, 8x10'~) boron implant is performed to form P+ (PMOS) source/drains (Fig. 2.9(1)).

Photoresist is thern removed and al1 the silicon nitride is selectively wet etched.

Even though BF2 has a smaller projected range than elemental boron which makes

shallow junctions easier to create, boron was used to create the 0.2 pm junctions for the

following reasons:

1. Because BF2 is larger than elemental boron, activation of the sourceldrain

implant and removal of implantation-induced crystallographic defects would

require that it be subjected to the gate activation anneal ( 1 lûû°C, 20 sec.).

2. Because at the University of Toronto Microelectronics Research Lab (UTMRL)

their exists a standard recipe to form oxide sidewall spacers (SWS) and no rec-

ipe to form nitride ones (which have k e n shown to prevent up-diffusion of

boron from BF2 S/D implantation) their exists the possibility for this high dose

implant to completely d i f i se out (caused by the fluotine in BF2) dunng the high

temperanire RTA step preventing the formation of an ohmic contact with the

metallization.

3. The up-difision of the high dose boron implant into the oxide c m lead to the

formation of a boron-silicate glass. This g l a s is very dificult to remove. There-

fore, it may become difficult to manufacture SWS.

P+ Source/Drain Activafrafron and Side Wall Spacer (SWS) FonnafLnnafLon

A thick LPCVD oxide is deposited (4200 A). The boron S/D implant is activated

and the oxide densified for 1 min. at 900°C in an N2 ambient by RTA. Using RIE, the

oxide is isotropically etched to form SWS (Fig. 2.9(m)). The width of the SWS is approx-

imately 60% of the thickness of the oxide deposited (- .25 pm).


Chapter 2 - Process and Device Design of a t V Low Power CMOS Pmcess Page 44

Self-Aligned Silicide (SALICIDE) processes are used in advanced CMOS technol-

ogies to lower the resistance of gate and S/D regions, contact resistance and S/D series

resistance increasing device performance and allowing higher operation speeds by reduc-

ing RC delays [33-361. The integration of a SALICIDE process into a CMOS technology

requires the understanding of the many interactions between process variables. silicide

physical characteristics, device parameters and ultimately device performance.

(transformation to

isolation leakage

I I

Contact resistivity, S/D series resistance

Fig. 2.11 SALICIDE Integration Issues [3 11

Some of the device parameters that are affected by silicide processing (Fig. 2.1 1)

are the sheet resistance of the gate and S / D areas (which affect delay per stage and device

speed), junction leakage, leakage due to bndging by silicide later growth over isolation or

gate sidewall spacer, silicide to S/D specific contact resistivity( p C) and contact resistance

(Rc) which contributes to SID series resistance (RsD) affecting drive current (Idrive).

Titanium silicide (Tisi9 is by far the most commonly used refractory metal sili-

cide.TiSi2 has the lowest resistivity (13-16 pohm-cm) arnong the refractory metal silicides

(MoSi2, WSi, TaSi& It cm dissolve the native oxide fonning a clean interface with the Si.

However, its reaction with Si02 is among the worst of al1 the candidates. Reaction temper-

atures should be Iimited to 70°C dunng silicide formation. Tisi*, after formation has its

-- - -


Chapter 2 - Process and Device Design of a 1 V Low Power CMOS h e s s page 45

high temperature limitations as well. At 900°C or above. both junction integrity and gate

integrity degrade [33].

There is a maximum silicide thickness compatible with a given junction depth, that

maintains low diode leakage and low RsD. As the junction depth is scaled for each new

technology generation, the silicide thickness needs to be scaled down accordingly. The cri-

teria for maintaining Iow leakage currents (< 1 0 ' ~ ~crn-*) was found to be [37-381: less

than 75% of dopant loss from the junction; and a remaining junction depth of at least 140

nrn under the Tisi2 layer. A blanket Ti film (300 A) is deposited in the first step by sputter-

ing using a Virian-Mode1 3 140 sputter. In the second step (silicide formation), the depos-

ited Ti is themally reacted using the Heatpulse 410TM thermal processor at 690°C for 60

sec. in an N2 ambient to fonn Tisi2 (this Tisiz film is a high resistivity 60-90 pohm-cm

layer with a C49 crystal structure 1331) films on the gates and S/D areas. Since the silicide

forms by the reaction between Ti and Si (Si has ken shown to be the moving species) no

silicide is formed on top of the isolation or gate sidewail spacer. The use of a nitrogen

environment during Tisi2 formation is essentid to the SALICIDE process because the

nitrogen reacts with titanium to provide a surface layer of Ti which inhibits the laterai

growth of the silicide. The titanium-nitrogen reaction, however, is a competing reaction

and reduces the amount of titanium available for Tisi2 formation. Therefore the ideal

TiSi2/Si structure is not realized in practice and TiN/Si2/Si is expected [38]. In the third

step, Ti and unreacted Ti films are removed using a selective wet etch (H202:NH40H).

Finally, a higher temperature anneal (850°C, 30 sec.) is used to convea the high resistivity

silicide from the C49 to the CS4 phase and reduce the sheet resistance by a factor of five

[33] as shown in Fig. 2.9(n).

A 8000 A oxide layer is deposited. The oxide should be thick enough to reduce the

parasitic capacitance between the metal pads and the substrate. The thickness of the oxide

is limited by the need to etch contact openings. The oxide is densified in an nitrogen ambi-

ent using RTA (800°C, 2 min). The temperature is limited to 8 0 0 ~ ~ so that the silicide

sheet resistance and metal to silicide contact resistance are not degraded [39]. Photoresist

is pattemed using the eleventh mask: the Contact Opening mask as shown in Fig. 2.1 L(o).

Contact openings are wet etched to ensure good step coverage. Photoresist is then

removed.


Chapter 2 - k e s s and Device Design of a IV Low Power CMOS M e s s Page 46

Using TiW to Prevent Aluminum Spiking through Shallow S/D jurtctions

Silicide Iayers provide litde barrier in preventing the interaction between dumi-

num metallization and the silicon substrate. The best solution to this problem is to incor-

ponte a diffusion barrier between the aluminum and the silicide [33]. The refractory metal

d o y TiW is one of the most popular contact barrïer layers. Consequently, a blanket layer

of 1 0 A of Ti. Weg is deposited first by sputtering.

A 1 pm layer of aluminum is sputtered on the wafer. Photoresist is pattemed using

the twelfth and final mask: the Metal mask. Aluminum is wet etched and the photoresist is

then rernoved. TiW is wet etched using hydrogen peroxide with the aiuminum serving as

the mask for the underlying TiW. Photoresist cannot be used as a mask because H202

reacts with photoresist to crack it. M e r TiW is etched, the wafer is anneaied in forming

gas (5% hydrogen, 951 nitrogen) for 25 minutes at 435OC to reduce the contact resistance

and Qit (interface-trapped charge) as shown in Fig. 2.9(p).


-ter 2 - Process and Device Design of a 1 V Low Power CMOS A.ocess page 47

2.5 Process Simulations

Two simulators, SUPREM-3 and SUPREM-4, were used to investigate the L W

CMOS fabrication process. SUPREM-3 is a 1D simulator and is used to obtain accurate

doping profiles versus depth from the surface of the wafer. SSUPRM-4 is a 2D simulator

that can determine oxide thickness, impurity concentrations, etc., in d l regions of the

device simultaneously. SUPREM-4 is usefd for investigating 2D effects such as laterai

diffusion of impurities. However, because profiles are determined in two dimensions, sim-

ulations take much longer to complete and doping profiles in the vertical direction are less

accurate (i.e., fewer available mesh points).

2.5.1 ID Simulations using SUPREM-3

Doping profiles were detemùned in the active regions, the field region, and the S/D

contact regions dong the cross-sections defined in Fig. 2.12.

Fig. 2.12 SUPREM-3 Simulation Regions

The TSUPREM-3 process simulations were performed first on the device wells

and threshold adjust implants. The simulated well and channel profiles were then used (as

the background concentration) for simulating the S/D contact regions. Figure 2.13 illus-

trates the simulation results on the various regions of the device.

A 1 V Low-Power CMOS Rocess University of Toronto

Chapter 2 - Rocess md Device Design of a 1V Low Power C ' O S Rocess Page 48

.- .1 la r0 Y

Depth from Surface (pm)

.- U ln U J.0

Depth from Surface (pm)

(cl

Fig. 2.13 Simulated Doping Profiles in (a) NMOS-Channel and Weil (b) NMOS- Source/Drain (c) PMOS-Channel and Weli (d) PMOS-Source/Drain

The simulated doping profiles in the channel and well and sourcefdrain regions is

shown Fig. 2.13. The doping concentration at the surface, initidly 2x10'~ for both

wells, is raised by ion implantation using As (nFET) and BF2 (pFET) to 2 . 3 ~ 1016 cm-3 and

5.6~ 1 016 cm" as shown in Fig. 2.13(a) and Fig. 2.1 3(c) respectively. The sirnulated dop-

ing profile in the source/drain region for these same devices is show Fig. 2.13(b) and Fig.

2.13(d) respectively, for 0.2 pm junction depths. Table 2.2 below surnmarizes the process

parameters extracted from 1 D SUPREM-3 simulations.

Table 2.2 Sirnulated LVCMOS Process Parameters

- -


Chapter 2 - Process and Device Design of a 1V Low Power CMOS Rocess page 49

The simulated doping profile in the field region (over the p-well) after boron

implantation and field oxidationl is shown in Fig. 2.14.

Depth from surface of SiOz (pm)

Fig. 2.14 Simulated Doping Profile in the Field Region

The concentration of boron at the Si/SiO2 interface is 1 . 8 ~ 1 0 ' ~ while the p-

guard extension into the p-well is - 2.5 Pm. Using 1D simulations, the field threshold volt-

age was determined to be 6 V.

2.6 Device Simulations

Device simulations were performed using the 2D device simulator MEDICI with

vertical doping profiles (Le. source/drain and channel) input from TSUPREM-3. A doping

and field dependent mobility mode1 were included. The device simulations were an itera-

tive process with the n- and p-channel devices re-tested until the threshold voltage specifi-

cation was met and the subthreshold swing S reduced as far as possible. As well, to

ascertain the future potential of low voltage MOSFETs, a 1 V 0.35 pm low power CMOS

process was also simulated.

' ~ s s u m i n ~ that - 3000 A ( f m the initial 7000 A) of SiOi grown is lost through subscquent processing


Chapter 2 - Rocess and Device Design of a 1V Low Power CMOS Process page 5 1

Using this technique, a threshold voltage of 300 mV was extracted for both devices

satisfj4ng the V, specification. As expected, the drain current of the n-channel MOSFET

is larger than that of the p-channel one (approximately 3.5 times larger than the p-channel

MOSFET).

The simulated subthreshold swing is extracted by measuring the inverse subthresh-

old slope in the weak inversion regime on a Log (IDS)-VGS curve. The off-state leakage

current Iop is defined as the device current with OV applied to the gate and 1V applied

between drain and source terminais. Figure 2.17 illustrates the simulated subthreshold

characteristics (normalized on a per channel width) for 1 prn Ldrawn n- and p-channel

devices-

IO"

1.0 4.5 0.0 0.5 1.0

Gate Voltage (V)

Fig. 2.17 Simulated subthreshold characteristics for N- and PMOS transistors @ VDs= 0.05V & 1V for LhW = 1 Pm-

The values of S and Iof extracted from Fig. 2.17 are 74 mV/dec and 17 pAlpm

respectively for the p-channel device and 79 mV/dec and 114 pA/pm respectively for n-

channel device. The higher subthreshold swing and off-state leakage current exhibited by

n-channel MOSFET is directly a result of a higher substrate doping concentration and

smaller effective channel length (see Table 2.3).

--


Chapter 2 - Process and Device Design of a IV Low Power CMOS Roces page 52

Medici simulations of V, and S as a function of Ld,, are shown in Fig. 2.18. The

results indicate the devices begin to exhibit short-channel effects at Ldmn < 1 pm for both

transistors after which it can be seen that V' and S begin to rapidly roll-off.

Table 2.3 surnrnarizes the simulated 1

Fig. 2.18 (a) Threshold Voltage and (b) Subdireshold Swing Roll-Off Characteristics

Table 2.3 Simulated LVCMOS Device Parameters

pm LVCMOS device characteristics.

)LI

h

U P)

=- E V

M f .I s

m . 0 O a 3 51 75.0-


-

0 NMOS

Parameter

Ldmm

vto

S

CA - PMOS

NMOS

1

0.3

79

PMOS

1

-0.3

74

Units

P V

mV/dec


2.7 Process Scaling

Given the increasing demands of portable applications, device dimensions as well

as supply voltages, continue to be scaled down to achieve higher packing density, faster

circuit speed and lower power dissipation [41]. The performance of the baseline 1 pm

CMOS process can be improved dramaticaily through device scaiing - shrinking the gate

length to a state-of-the-art 0.35 pm (Lg=0.25 pm) process from 1 Pm.

Reduction of the SCE constinites a major part of the technology optirnization and

development for a scaled CMOS technology. In the ideal case, a MOSFET should behave

like a switch, Le., the device current should be high when the device is on, and there

should be minimal leakage when the device is off. As device dimensions are reduced, it

becomes very difficult to maintain this ideal switching behavior of CMOS. The prlliiary

impact of short-channel effects is to increase the leakage current when the devices are in

the off-state. To scale transistors into the deep submicron regime and at the same time sup-

press short channel effects, very thin gate oxide thicknesses, very shallow source/drains

junctions as well as the aggressive design of dopant profiles within the device are neces-

sary. However, one major challenge is boron penetration through the thin gate oxide in

surface channel PMOSFETs since boron diffusion through Si02 becomes exponentially

dependent on oxide thickness below 80 A [42]. Other difficulties include low breakdown

voltage, thickness variation control, and device reliabilities [43].

The 0.35 pm device simulation structure is the same as the one used for the 1 pm

case with obvious changes to the gate length and source/drain doping profiles. The doping

profile in the channel however is vertica1ly engineered to minirnize the doping level at the

surface and beneath the junctions, while maintaining good tum-off characteristics. It is

assumed that their is no boron penetration through a thin 60 A gate oxide (with very high

interface quality, Qf- 10'' /cm2) [44] and this achieved through the incorporation of nitro-

gen directly into the polysilicon gate via ion implantation or through a separate- heavily

doped nitrogen cap layer between the polysilicon gate and gate oxide [45-471. The S/D

junctions are 500 A deep to lirnit SCE and no LDD are incorporated to reduce parasitic

source/drain series resistance.

'~aiwan Semiconductor Manufachuing Company (TSMC) is an extemal foundry offering CMOS processes with 0.35 j.un design mles for large volume production through the Canadian Microelectronic Corporation (CMC).

A 1V Low-Power CMOS m e s s University of Toronto

Chapter 2 - Process and Device Design of a IV Low Power CMOS h e s s Page 54

2.7.1 A 0.35 p.m CMOS Process Optimized for 1V Applications

A schematic cross section of the 0.35 pm CMOS device structure is shown in Fig.

2.19. Key device parameters are shown in Table 1 S. Figures 2.20(a) and 2.20(b) show the

1-V curves of 0.35 pm nFET and pFET devices. High transconductance with steep sub-

threshold swing and low Ieakage are demonstrated Simulated threshold and subthreshold

roll-off characteristics are plotted in Figs. 2.20(c) and 2.20(d) as a function of channel

length respectively. Excellent short-channel characteristics are obtained for both FETs.

n+ Poiy ,7LL

Fig. 2.19 0.35 pm CMOS Schematic Cross Section

1 I .U U U .I W

Gate Volîage (V)

PMOS JII

VG swcpt from OV to (-1 1 V with ( -p.2~ rteps VD swcpt from OV ro (4 1 V with (-N.2V ucps '

Gate Voltage CV)

Fig. 2.20 Simulated 0.35 pm CMOS Charactenstics (a) Subthreshold I-V (b) Output IV (c) Threshold Voltage Roll-Off (d) Subthreshold Slope Roll-Off



Table 2.4 A Cornparison of Key Device Parameters

Parameter

Using a figure of merit of I&~(/(Cox*VDD), the performance of the transistors in

this work is compared to published results [48-541 in Fig. 2.2 1 .

PMOS

Lefl Olm) Leff ( ~ m )

Fig. 231 Figure of Merit vs. LeRfor Published Results

Although the supply voltage (thus the switching power) of this work is much less

than most references cited, the devices in this work deliver comparable performance.

- - - - - - - - - - -

A IV Low-Power CMOS h.ocess University of Toronto

Chapter 2 - Pmcess and Device Design of a 1V Low Power CMOS Process page 56

This chapter presented device fabrication and performance issues dong with pro-

cess and device simulation results. SpecificalIy, design issues including: short-channel

effects, the implementation of low threshold voltages, the elimination of latch-up, MOS-

FET isolation and polysilicon gate strapping during silicidation, al1 issues critical in the

design of a 1 pm low power CMOS process were presented. The low voltage CMOS pro-

cess fiow was also descnbed. Using ID process simulations and 2D device simulations,

the electrical performance of these devices was examined. These simulations showed that

complementary long-channel devices with 300 mV threshold voltages and subthreshold

swings of c 80 mVldec with low off-state leakage currents could be fabricated.

The portability of this process to deep subrnicron gate lengths was also investi-

gated using 2D device simulations. These devices are highly suitable for high performance

1 V applications.

Using ~at/(Cox*VDD) as a figure of merit, the low voltage devices in this work

were compared to other high performance bulk CMOS technologies. The performance of

these devices was shown to be comparable even at the reduced power supply.


Chapter 2 - Rocess and Device Design of a 1V Low Power CMOS Process page 57

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S. J. Kwon, Y. H. Kim, K. J. Chum, and J. D. Lee, "As Rearnorphization of the Predeposited Amorphous Si Layer for the Formation of the Silicided Ultra Shallow p+-n Junction," Jpn. J. Applied Phys., vol. 33, pp. 664-667, 1994.

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L. K. Han, D. Wristers, J. Yan, M. Bhat and D. L Kwong, "Highly Suppressed Boron Penetration in NO-Nitrided S i 4 for p+-~olysilicon Gate MOS Device Applications," IEEE Elecrron Device Lett., vol. EDL-14, pp. 3 19-32 1, 1995.

K. S. Krisch, M. L. Green, F. H. Baumann, D. Brasen, L. C. Feldman and L. Man- chanda, "Thickness Dependence of Boron Penetration Through O*- and N20- Grown Gate Oxides and Its Impact on Threshold voltage variation," IEEE Tram. Electron Devices, vol. ED-43, pp. 982-990, 1996.

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H. S. Momose, T. Morimoto, Y. Ozawa, K. Yamabe, and H. Iwai, "Electrical Char- acteristics of Rapid Thermal Nitrided-Oxide Gate n- and p-MOSFETTs with less than 1 Atom% Nitrogen Concentration," IEEE Trans. Electron Devices, vol. ED- 41, pp. 546-552, 1994.

H. G. Pomp, et al., "Lightly N20 Rapid Thermal Niuided-Oxide Gate n- and p- MOSFET's with less than l Atom % Nitrogen Concentration," IEEE Trans. Ekc- tron. Devices, vol. ED-41, pp. 546-552, 1994.


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J. C. Hsieh, Y. K. Fang, C. W. Chen, N. S. Tsai, M. S. Lin. and F. C. Tseng, "The Ongins of the Performance Degradation of Implanted P+ Polysilicon Gated P- Channel MOSFET WithlWithout Rapid Thermal Anneaiing,.' IEEE Trans. Elec- tmn Daices, vol. ED-41, pp. 160- 162, 1994.

W. Zagozdzon-Wosik. P. B. Grabiec, and G. Lux, "Fabrication of Submicron Junc- tions-Proximity Rapid Thermal Diffusion of Phosphorus, Boron, and Arsenic,.' IEEE Trans. Electmn Devices, vol. ED-41, pp. 228 1-2290, 1994.

C. Y. Ting, "Silicide For Contacts and Interconnects," IEEE International Electron Device Meeting (IEDM), Dig. Tech. Papers, pp. 1 10- 1 13, 1984.

J. A. Kittal, D. A. Prinslow, and Q. Hong, "Evolution of Ti SALICIDE processing: From 0.5 pm to 0.1 pm Length CMOS Technologies," Future Fab, vol. 1, pp. 19 1 - 197, 1997.

T. Mogami, H. Wakabayashi, Y. Saito, T. Tatsumi, T. Matsuki, and T. Kunio, 'cLow-Resistance Self-Aligned Ti-Silicide Technology for Sub-Quarter Micron CMOS Devices," IEEE Trans. Electron Devices, vol. ED-43, pp. 932-939, 1996.

C. K. Lau, Y. C. See, D. B. Scot, J. M. Bridges, S. M Perna, and R. D. Davies, 'Titanium Disilicide Self-Aligned Source/Drain + Gate Technology," IEEE Inter- national Elecrron Device Meeting (IEDM), Dig. Tech. Papers, pp. 7 14-7 17, 1982.

J. Amano, K. Nauka, M. P. Scott, J. E Turner, and R. Tsai, "Junction Leakage in titanium self-aligned silicide devices," Applied Phys. Lefi. vol. 49, pp. 737-739, 1986.

R. G. Taylor, "Arsenic Redistribution During Titanium Silicide Formation," M.A.Sc. Thesis, University of Toronto, 1988.

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Application Note 3 15, Practical Applications of the 4 I45B Semiconductor Parm- eter Analyzer, Hewleît-Packard Co., 1992.

M. Rodder, et al., 'A Sub-û. 18 p.m Gate Length CMOS Technology for High Per- formance (1.W) and Low Power (l.OV)," IEEE International Electron Device Meeting (IEDM), Dig. Tech. Papers, pp. 563-566, 1996.

R. B. Fair, "Oxide thickness Effect on Boron Difision in Thin Oxide p+Si Gate Technology," IEEE EIectmn Device Lm. , vol. EDL-17, pp. 242-243, 1996.

M. T. Takagi, et al., "A novel0.15 pm CMOS Technology using W/WNX/Polysili- con Gate Electrode and Ti Silicided Source/Drain Diffusions," IEEE International Electron Device Meeting (IEDM), Dig. Tech Papers, pp. 455458, 1 996.

L. Manchanda, et al., "A Boron-Retarding and High Interface Quality Thin Gate Dielectric for Deep-Subrnicron Devices," IEEE International Electron Device Meeting (IEDM), Dig. Tech. Papers, pp. 459-462, 1993.

T. Kuroi, et ai., "The Effects of Nitrogen Implantation Into P+ Polysilicon Gate on Gate Oxide Properties," Symp. VLSl Technology, pp. 107- 108, 1994.

S. C. Sun, L. S. Wang, F. L. Yeh, and C. H. Chen, "Rapid Thermal Chernical Vapor Deposition of In-Situ Nitrogen-Doped Polysilicon for Dual Gate CMOS," Symp. KSI Technology, pp. 12 1 - 122, 1995.

S. Nakayama, and T. Sakai, "The Effect of Nitrogen in P+ Polysilicon Gates on Boron Penetration into Silicon Substrate Through Gate Oxide," Symp. VLTI Tech- nology, pp. 228-229, 1996.

R. Chapman, J. W. Kuehne, et al., "High Performance sub half micron CMOS Using Rapid Thermal Processing," IEEE International Electmn Device Meeting (IEDM), Dig. Tech. Papers, pp. 10 1 - 104, 199 1.

Z. Chen, J. Burr, J. Shott and I. D. Plurnrner, "Optimization of Quarter Micron MOSFETs for Low VoltageLow Power Applications," IEEE International Elec- hon Device Meeting (IEDM), Dig. Tech. Papers, pp. 63-66, 1995.

R. Chapman, R. A Haken, D. A. Bell, "A High Performance CMOS technology for High Performance Logic Applications," IEEE Intenuztional Electron Device Meet- ing (IEDM), Dig. Tech. Papers, pp. 363-365, 1987.

B. Davari, et al., "A High Performance 0.25 pm CMOS Technology," ZEEE Inter- national Electron Device Meeting (IEDM), Dig. Tech. Papers, pp. 56-59, 1988.

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Chapter 2 - Process and Device Design of a IV Low Power CMOS Process page 6 1

[53] K. Fujii, et al., " A Thermally stable Ti-W Salicide for DeepSubmicron Logic with Embedded DRAM," IEEE International Electron Device Meeting (ZEDM), Dig. Tech. Papers, pp. 45 1454, 1996.

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Chapter 3 - Experimentai Venfication of a Low Valtage CMOS Process page 62

CHAPTER 3

Experimental Veripcation of a Luw Voltage CMOS Process

3.1 Introduction

This chapter deals with the experimental verification of the LVLP CMOS process

simulations presented in Chapter 2. In Section 3.2, a full description of the experimental

work done to verify the process steps is presented. The test chip is documented in Section

3.3. Finaily, Section 3.4 surnrnarizes the conclusions regarding the experimental results.

3.2 Experimental Development of a 1V Low Power CMOS Process

Due to the fact that conventional off the shelf process simulations are not hilly cal-

ibrated to mode1 exact process conditions encountered experimentally, the process simula-

tions presented in Chapter 2 were used only as a starting point from which experimental

results were used to refine the fabncation steps [Il.

There are five important technological steps involved in the design of the LVLP

CMOS process. The first is the fabrication of a 0.3 pm n+(phosphorus)/p+(boron) polysili-

con gate without any dopant penetration through the gate oxide into the Si substrate or

polydepletion effect. The second issue is the realization of low doped (-2x10'~ cm") n-

and p-wells. The n-well being approximately 2 Fm deep to prevent vertical punchthrough

below -3 V. The third issue is the formation of a p-guard with sufficiently high concentra-

tion to set the field device threshold voltage to at least 6V. The fourth issue is the imple-

mentation of the threshold adjust implant needed to attain the low 1300 mV threshold

voltage. And the fifth issue is the fabncation of very shallow 0.2 pm source/drain junc-

tions to minimize shortchamel effects. These steps were verified experimentally and are

dealt with individually in the following sections.


Chapter 3 - Experimental Verification of a Low Voltage CMOS Process Page 63

3.2.1 Dual PolysiIicon Gate Fabrication

Using the MOS capacitor structures illustrated in Fig. A.2 (See Appendix A) both

high frequency (HF) and quasi-static (QS) capacitance-voltage measurements were per-

formed. The HFCV measurements were used to determine whether boron(phosphorus)

penetration from the p+(n+) polysilicon gate through the 140 A gate oxide occurred. The

QSCV measurements were used to investigate polydepletion effects in the inversion

regime.

Dopant penetration is assessed by noting positive(negative) shifts in the flat-band

voltage, Vfb (from expected V' values) extracted from HFCV measurements. An

increase(decrease) in Vib is expected if boron(phospho~s) dopants penetrate through the

gate oxide and form a sheet of positive(negative) charge localized a the gate oxide/Si inter-

face. Taking dopant penetration into effect, the flatband voltage can be expressed as 121:

where qMS is the gate-to-serniconductor work function difference, N* is the effective den-

sity of dopant that penetrated through gate oxide, NF is the fixed oxide charge density and

Cm is the gaie-oxide capacitance.

MOS capacitors were fabncated on ( 100) 8.5- 1 1 R-cm n-type (phosphorus doped)

wafers for the case of the P+ poly capacitors (PCAP) and (100) 2-4 !&cm p-type (boron

doped) wafers for the N+ poly capacitors (NCAP). Four different thicknesses of gate

oxides, 100, 140,290, and 390 A, were therrnally grown in dry O2 + 2% HCL at 9ûû°C for

the purpose of establishing a Vfi reference. The gaie oxidation is followed by a 30 min.

anneal at 1050°C after which arnorphous poly is deposited by LPCVD at 560aC. The

thickness of the polysilicon film was 2850 A. The PCAP wafers were implanted with

boron (30 keV, 5x10'~ cm-') while the NCAP wafers were implanted with phosphorus

(30 keV, 5x10'~ cm"). The poly-Si gates areas were defined photolithographically and

patterned by wet etching. The annealing step to activate the implanted dopants as well as

to distribute dopant across the gaie and thereby take into account the thermal budget of the

entire process after n+ and p+ gate implantation (e-g., gate oxide reoxidation, gate and nf

S/D activation, p+ S/D activation and C49-CS4 Tisi2 conversion) was perfonned by RTA

in an N2 environment as illustrated in Table 3.1.


Chapter 3 - Experimental Venfication of a Low Voltage CMOS Process Page 64

Table 3.1 MOS Capacitor Thermal Budget

Thermal Step l Temperature (OC) 1 Orne (r) 1 - - - - - --

Gate Dopant and N+ S I D Activation 1 I l00 20 1

Re-oxidation of Gate Oxide after Gate Definition by RIE

P+ S / D Activation l 900 1 60 1 1 C49-CS4 Tisi2 Conversion 1 850 1 30 1

s

To establish whether any boron or phosphoms difhsed through the gate oxide, it is

important to establish a V+' reference above which boron and phosphorus penetration is

assumed to not have occurred. To establish this reference, fabricated MOS capacitor struc-

tures with gate oxide thicknesses larger than 140 A were used. Penetration of dopants is

not expected to occur at these gate oxide thicknesses [l]. Since the Bat-band voltage varies

linearly with gate oxide thickness as a result of the effect of qNdCox (See Eq. (3.1)), the

measured Rat-band voltages for the thick oxides can be extrapolated to lower oxide thick-

ness and used as a Vfb reference to asses whether boron or phosphorus penetration through

the gate oxide occurred. If no dopant penetration occurred then the extracted Ratband volt-

age measurements as a function of gate-oxide thickness should lie dong a straight line as

is illustrated in Fig .3.1.

900

Based upon the results shown Fig. 3.1, and for the experimental sequence envi-

sioned in the present CMOS process, there is no evidence that either boron or phosphorus

penetration through the thin 140 A gate oxide occurred. In fact, the results show that by

using the present implant conditions for both boron and phosphorus and rapid thermal

annealing at 1 lW°C for as long as 20s, the gate oxide thickness can be reduced to even

100 A without dopant penetration.

120


Chapter 3 - Experimental Verification of a Low Voltage CMOS h e s s page 65

NCAP P

t

Fig. 3.1 (a) Extracted Vfi vs. Oxide Thickness from HFCV measurements (b) Typical HFCV profiles measured using Hewlett Packard's 4280A lMHz C Meter

3.22 The Effect of a Nondegenerate Gate on MOS Device Characteristics

Unlike conventional gates, implanted polysilicon gates, as typically used in mod-

em processes, may be nondegenerately doped, depending on the process conditions. If the

implanted gate is not doped to degeneracy, it cm no longer be assumed to be an equipoten-

tial surface in the analysis of the electncal properties of MOS devices. Nondegenerately

doped gates produce several effects on MOS device characteristics: distortion of high fre-

quency and quasi-static C-V characteristics (including shift of the fiatband and the thresh-

old voltage) and a reduction in the inversion-Iayer charge and therefore, the drain current

[3-51. The gate depletion effect is a parasitic effect and the pnmary aim of this experimen-

tai work is to suppress it. The main parameter which determines the electrical characteris-

- - --- -- - - - -

A 1V Low-Power CMOS kocess University of Toronto

Chapter 3 - Experimental Verification of a Low Voltage CMOS Frocess Page 66

tics of the gate is the activated net impurity concentration near the gate/oxide interface.

This concentration ought to be sufficiently high, which is one of the key issues in process-

ing implanted gates [3].

To evaluate the extent of any polydepletion effect, QSCV rneasurements were per-

formed on the 140 A n+- and p+-type capacitors using a Hewlen Packard 4 140B pA Meter.

The measured quasi-static C-V rneasurements are shown in Fig. 3.2.

-3.0 -10 -la en ta t0 3.0

Voltage (V)

Fig. 32 Typical Experimental CQs-VG Characteristics

The QSCV rneasurements indicate that the inversion capacitance is within 6-7% of

the oxide capacitance in the inversion region for both types of capacitors. This suggest that

the polydepletion effect is very minimal in these devices. Figure 3.3 shows the active car-

rier concentration of phosphorus and boron in the polysilicon gate MOS capacitors

obtained from SRA.

From SRA, the measured carrier concentrations at the Polysilicon/Si02 interface

were 1 . 5 ~ 10" cm-3 and 1x10'~ cm-3 for the n' and p+ capacitors respectively. Complete

elimination of the polydepletion effect in these MOSFETs [4] requires that the concentra-

tion of dopants at the polysilicon/Si02 interface be increased to atleast 5x 10" cm-3.


Chapter 3 - ExperimentaI Verification of a Low Voltage CMOS Process page 67

1 1 1 gate oxide

WprCr ID: NCAP-14

b S W a = Pnasphonis Dase = 5*10U En- = 30 keV

Fig. 3 3 Semi-Log Plot of the Measured (using SRA) Net Active Carrier Concentration in MOS Capacitor Gates (a) N+ (b) P+

Table 3.2 summarizes typical results of MOS capacitor and gate sheet resistance

measurement extracted from high frequency and Transmission Line Method (TLM) mea-

suremen ts respective1 y.

Table 3.2 Measured MOS Characteristics and Poly Gate Resistances


Chapter 3 - Experimental Verification of a Low Voltage CMOS Rocess page 68

3.23 N- and P-Weil Fabrication

Numerous implant and anneal conditions were tested to fabricate n- and pwells

with a surface concentration of approximateiy 2 x 1 0 ~ ~ cm-3. The depth of the n-well k i n g

around 2 pm to avoid vertical punchthrough. These objectives were met by using a phos-

phorus implant with a dose of 3 . 5 ~ 1 0 ' ~ at 25 keV and a boron implant with a dose of

6x10'~ cni2 at 15 keV (thmugh 400 A of screening oxide) for the n- and pwells respec-

tively. The n-well implant was driven-in for a total of 10 hours (initial 7 hour drive-in)

while the boron implant was driven-in for 3 hours (p-well and final n-well drive-in) at

1100°C. The final well doping profiles measured after drive-in by SRA are illustrated in

Fig. 3.4.

R n

10" N-W~N ~m~iant: E y Species = Phosphorus g ,op .ri C) DOW = 3 5 x 1 0 ~ cmœ2 E Y IO" r Energy = 25 keV E

R h

P-Weii Implant:

Energy = 15 keV

- - - - - -

Depth €mm Surface (pm) (b)

Fig. 3.4 Semi-Log Plot of the Measured (using SRA) Net Active Carrier Profile in the (a) N-Well and (b) P-Well After Drive-In.


Chapter 3 - Experimentai Verification of a Low Voltage CMOS Process page 69

3.2.4 P-Guard ImplantLOCOS Isolation Formation

To set the field device threshold voltage Vfto approxirnately 6V (see Chapter 2,

Section 2.5), a boron implant with a dose of 8x10'~ cm" at 30 keV (through a 400 A screening oxide) was used. After implantation, LOCOS oxidation is performed at 950°C

for 250 min. in which 7000 A of field oxide is grown and the boron implant driven-in. The

resulting p-channel stopper implant profile measured by SRA is shown in Fig. 3.6.

P-Guard Implant: 1 Species = Bomn Dose = S X I O ~ cm-2 Energy = 30 keV Field Oxide = 4000 A

Li

Li

Depth h m Surface (p)

Fig. 3.5 Semi-Log Plot of the Measured (using SRA) P-Guard Carrier Concentration vs. Depth from Surface Measured in the Field Region

The boron concentration at Si/S i 0 2 interface was 1 SX 1 016 c m 3 while the p-guard

extension into the p-well was determined to be 1.7 Pm (using SRA). Using 1D simulation

with the measured p-guard carrier concentration profile above as input, the field threshold

voltage was deterrnined to be 5.4 V.

3.2.5 Source/Drain Fabrication

The source and drains were designed for a junction depth of 0.2 Fm. To achieve

this for the case of the n+ Sm, arsenic with a dose of 4x10'~ at 110 keV was

implanted through 200 A of Si3N4 and subjected to the thermal budget shown in Table 3.1.

For the case of the p' S/D, boron with a dose of 8x10'~ cme2 at 25 keV was implanted

through 600 A (after subsequent deposition of 400 A) of Si3N4 and activated by RTA at

900°C for 1 min. followed by 850°C for 30 sec. (to account for C49-CS4 Tisi2 conver-

sion). The doping profile in the S/D junctions depths is illustrated in Fig. 3.6 and indicates


Chapter 3 - Experimentai Verification of a Low Voltage CMOS Process Page 70

junction depths of 0.175 pm and 0.185 pm with peak doping concentrations of

lx1 do and 3x 10'' cm3 for the n and p junctions respectively.

- - 5 la= N+ Sm Implant: E V ioW

n+ SiD S ~ e c i e s = Arsenic DOW = 4x10'~ cm3 Energy = 110 keV

P+ S/D Implant: V

c Species = Boron p le- s Li w

!i Ion 1 \ Energy = 25 keV 1

Depth from Surface (jm) (b)

Fig. 3.6 Semi-Log Plot of the Measured (using SRA) Net Active Carrier Concentration in the (a) nf S/D Region and (b) p+ S/D Region

Using the pn junction test structures illustrated in Fig. A4 (See Appendix A) dong

with the HP 4155A Semiconductor Parameter Analyzer and the Tektronix K213 Povrer

Curve Tracer, the forward-bias and reverse bias 1-V characteristics of these junctions were

measured. Typical forward bias 1-V characteristics obtained from measurements on

n+- and p+- SID junctions are presented in Fig. 3.7 together with the cdculated parameters

in Table 3.1.


Chapter 3 - Experimental Venfication of a Low Voltage CMOS Process page 71

Voltage (V)

Fig. 3.7 PN Junction Forward Bias Log (1)-V Curve (a) n+ S I D and (b) pf S / D

Table 3.3 PN Junction Characterization Data

1 Parame ter 1 P+ Diode 1 N+ Diode 1 I

Ideality Factor 1 1 .O9 1 f -08 1

1 Specific Contact Resistance (&m2) 1 5.20~10;' 1 1.50~10~~ 1 I I

Saturation Current (fA)

S heet Resistance (WCl)

Senes Resistance (Q)

1 Breakdown Voltage (V) 1 30 1 27.5 1

3.2.6 Threshold Adjust Implants

41-1

44

30.5

Experimental threshold voltage implant tests were performed in an effort to

achieve a surface concentration (as predicted from MEDICI simulations) which would

provide n- and p-MOSFET's with a 300 mV threshold voltage. The implant conditions

used were a 2 . 5 ~ 1 0 ' ~ cmm2 dose BF2 implant and a 3 .8~10 '~ dose As implant both at

25 keV (through 140 A of gate oxide) for the n- and p-channel devices respectively. These

implants were then activated by RTA with the thermal budget shown in Table 3.1

23.4

10

29.4


Chapter 3 - Experimental Verification of a Low Voltage CMOS Rocess Page 72

Species = Arsenic j 10- 0 , ,, DOW = 3.tix101' cmo2

Depth fmm Surface ( p j

(a)

Species = BF2 Dose = 2.5~10~ cm4

Y psu bstrate

3.0

~ e & from ~di&'(pm)

Fig. 3.8 Semi-Log Plot of the Measured (using SRA) Net Active Carrier Concentration in the Channel (a) PMOS (b) NMOS.

Using two dimensional computer simulations with experimental chunnel, well and

S D doping profiles as input, threshold voltages of 308 mV and -294 mV with subthresh-

old swings of 80 mVldec and 74 mVldec for n- and p-MOSFETs were predicted.

3.3 Test Chip Description

A photornicrograph of the LVCMOS test chip is shown in Fig. 3.4. The test chip

was laid out using 1 pm design rules (see Appendix B for a complete set of design rules)

and contains process test inserts, MOSFETs as well as ring oscillators, EX-OR, NAND and INV gates. The process inserts include on-wafer standards for deembedding of the

transistor S parameten, MOS capacitors for process and device characterization, TLM


Cbapter 3 - ExperÏmental Verification of a Low Voltage CMOS h e s s page 73

(Transfer Line Method) for sheet resistivity measurements of poly gate and diffusion

regions and Kelvin cross stnictures for extraction of contact resistance.

Fig. 3.9 Plot of the LVCMOS Test Chip

The following is a description of the transistors included on the test chip:

(a) Fourteen interdigitated gate (7 n-channel and 7 p-channel) 180 pm wide MOS-

FETs with gate lengths of 0.8 pm, lpm, 1 . 2 ~ ~ 1.4 Pm, 2 Pm, 3 pm and 5 pm

respectively with 1 12x 1 12 pm inputloutput pads for dc measurements.

(b) Fourteen single gate (7 n-channel and 7 p-channel) 180 pm wide MOSFETs

with gate lengths of 0.8 p, lpm, 12p, 1.4 Pm, 2 p, 3 pm and 5

respectively with 1 12x1 12 pm input/output pads for dc rneasurements.


Chapter 3 - Experimental Venfication of a Low Voltage CMOS Rocess page 74

(c) Eight interdigitated gates (4 n-channel and 4 p-channel), 3 pm long with 30,80,

130 and 180 jm wide gate widths. These devices have 1 12x1 12 input and out-

put pads. They are intended for the extraction of the effective gate length from

dc measurements.

(d) Six (3 n-channel and 3 pchannel) Z-shaped gates, 180 pn wide wi& 1 p,

2 pm and 3 pm gate lengths. These devices have 50x50 pm input and output

pads laid-out for S parameter probing using the ground-signal (GSG) coplanar

probes.

(e) Two long and wide n- and p-channel MOSFETs (FATEET) lOOxlOO pn

intended for C-V and mobility profiling.

Circuits implemented on the test chip include:

(0 Two 180 pm wide interdigitated gate (inverters, 2-input NAND and 2-input

NOR gates) with gate lengths of 1.2 prn and 3 p n respectively.

(g) Two ring oscillators (one 21-stage inverter and one 21 stage 2-input NAND

with output buffers) to characterize circuit speed and circuit power. Both of

these ring oscillators incorporate 1.2 Pm gate lengths and 12 pm gate widths.

(h) Four current &ors (2 n-channel and 2 pchannel), 12 pm and 24 pm wide

with 1.2 pm drawn gate lengths.

Inserts included to Characterize the process:

(i) Four TLM and four Kelvin structures for the extraction of sheet and contact

resistances n+- and p+- poly gate and n+- and p+- S/D layen respectively.

(j) Two MOS capcitors (area = 6 . 2 5 ~ 1 0 ~ cm2), one n-type and one p-type for

C-V profiling.

(k) 'Mo Gate-Controlled Diodes (GCD), one p+n and one nCp for leakage current

characterization (area = 6.92 ~ 1 0 ~ cm2).

(1) Two pn diodes (axa = 1 x 1 0 ~ cm2), one p+n and one nfp for source/drain char-

acterization.

A 1V Low-Power C ' O S Process University of Toronto

Chapter 3 - Experhental Verification of a Low Voltage CMOS Pn>cess page 75

The five critical issues involved in the fabrication of a 1 pm LVCMOS process

were verified in order to establish the feasibility of t le process proposed in Chapter 2.

Separate n- and p-MOS capacitor studies indicate that an amorphous silicon layer

deposited at 560°C with high dose, low energy boron and phosphorus implants followed

by activation anneals of 1 10û°C for as long as 20s, are suitable for effectively doping the

gate with minimal polydepletion effect and avoiding dopant penetration through 140 A of

gate oxide.

Deep, low concentration (2x10'~ cmJ) n- and pwells with Rat profiles were

implemented dong with suitable threshold voltage adjust implants and shaliow (0.2 pm)

source/drain junctions. From the experimental results obtained, complementary devices

with 300 mV threshold voltages and low subthreshold swings are definitely feasible.

Using a moderate dose boron implant prior to field oxidation, the parasitic field

threshold voltage can be set to approximately 6 V.

A 12 mask 16 mm2 test chip using 1 pm design rules was laid out incorporating

process inserts, MOSFETs as well as ring oscillators INV, NAND and NOR gates.


Cbapter 3 - Experimentai Verification of a Low VoItage CMOS Process page 76

References

S. C. Magierowski, "A PMOS Transistor for a Low Power 1V CMOS Process," M. A. Sc. Thesis, University of Toronto, 1997.

K. S. Krisch, M. L. Green, F. H. Baumann, D. Brasen, L. C. Feldman, and L. Man- chanda, 'Thickness Dependence of Boron Penetration Through 02- and N20- Grown Gate Oxides and Its Impact on Threshold Voltage Viuiation," IEEE Tram. Electrun Devices, vol. ED-43, pp. 982-990, 1 996.

P. Habas. "'Anaiysis of Physicd Effects in Smaü Silicon MOS Devices," Ph. D. Dissertation, 1993.

C. Y. Wong, J. Y. -C. Sun, Y. Taur, C. S. Oh. R Angelucci, and B. Davari, "Doping of N+ and P+ Polysilicon in a Dual Gate CMOS Process," ZEEE Electron Device Meeting (IEDM), Tech. Papers. pp. 238-24 1, 1998.

H. Hayashida, Y. Toyoshima, Y. Suim, K. Mitsuhashi, H. Iwai, and K. Maeguchi, "Dopant Redistribution in Dual-Gate W-Polysicide CMOS and Its Improvement by RTA," MSI Techology. Symp., pp. 29-30, 1989.


Chapter 4 - ConcIusions and Suggestions for Future Work Page 77

CHAPTER 4

Conclusions

The goal of this thesis has been the development and experimentd verification of

the critical processing steps required to fabricate a CMOS process suitable for 1 V supply

applications. To ensure that the transistor performance remains as high as possible at the

reduced power supply, it is necessary that devices provide symmetric 300 mV threshold

voltages with good control. These two requirements are simultaneously satisfied

with the use of nC- and p+-poly gates for the n- and pchannel devices respectively. Due to

the low voltage environment, the devices do not include low doped drains, and titanium

silicide is incorporated to rninirnize the RC delay and increase the current drive of the

devices. The complete process involves 12 masks.

Due to process mode1 inaccuracy in predicting the exact process conditions, the

five cnticd technological steps involved in the design of the LVLP CMOS process were

verified experimentally. The first issue is the fabrication of a 0.3 Fm n+(phosphorus)/

p+(boron) polysilicon gate without any dopant penetration through the gate oxide into the

Si substrate or polydepletion effect. MOS capacitor studies indicate that implanting phos-

phoms and boron with a dose of 5x10 '~ at 30 keV followed by activation anneals of

L lO0C for as long as 20s are suitable for effectively doping the gates with minimal poly-

depletion effect. The second issue is the realization of low doped ( -2x10~~ cm-3) n- and p-

wells. The n-well being approximately 2 pn deep to prevent vertical punchthrough below

-3 V. This is done using a low dose phosphorus implant and a 1100°C anneal in N2 arnbi-

ent. The third issue is the formation of a p-guard with sufficiently high concentration to set

the field device threshold voltage to approximately 6V. This is done using a moderate dose

boron implant prior to field oxidation. The fourth issue is the implementation of the

threshold adjust implant needed to attain the low fl00 mV threshold voltage. Using sepa-

rate As and BF2 implants into the PMOS and NMOS devices respectively, the threshold

voltage of each transistor is tailored individually. And the fifth issue is the fabrication of

A 1V Low-Power îMOS Process University of Toronto

Chapter 4 - Conclusions and Suggestions for Future Work page 78

very shallow (0.2 pm) sourceldrain junctions to rninirnize short-channel effects. These

junctions are formed by using arsenic and boron implants respectively.

From the experimental results obtained, complementary devices with 300 mV

threshold voltages and less than 80 mV/dec subthreshold swings are definitely feasible. A

16 mm2 12 mask test chip to characterize the 1 pn CMOS process has been completed.

Future work should include the experimental characterization of working devices

and test structures using the LVCMOS process documented in Chapter 2. A worthwhile

effort would be to focus on systematically caiibrating various implant, difision and segre-

gation models for BF2, arsenic, boron and phosphorus in silicon and polysilicon to

enhance the capability of the process simulation software.


Appendix A- MOS Capacitor and PN Junction Characterizaton Page 79

Appendix A

MOS Cupucitor and PN Junction Characten'mtion

A.l C-V Measurements

HF-CV (high frequency) as well as QS-CV (low frequency) measurements are one

of the most cornmon process monitoring diagnostics employed in device manufachiring.

The MOS CV curve is charactenzed by three distinct regions: accumulation, depletion,

and inversion. In accumulation and inversion, capacitance is independent of applied volt-

age. The accumulation capacitance Ca and the inversion capacitance Cim are used in

computing device parameters such as substrate doping, Ratband voltage, and oxide charge

[l-21. The C-V curve is measured from a minimum to a maximum capacitance (from

strong inversion to accumulation) and, for an n-type substrate that means changing the d.c.

applied voltage from negative to positive values. The MOS capacitor and its typical HF-

CV curve are shown in Fig. A. 1.

Fig. A.l Capacitance of a MOS Structure as Function of Gate Voltage

If one measures the small signal capacitance between the gate metal and the silicon

substrate as a function of the gate to substrate voltage, a curve sirnilar to Fig. A.l is

obtained. For an n-type substrate, when the gate voltage is positive, the silicon surface is


Appendix A- MOS Capacitor and PN Junction Characterizaton page 80

accumulated and acts as a conductor, with the result that the capacitance (per unit area) is

just that of a parallel plate capacitor with the oxide as dielectric:

where C is the total measured capacitance; Cm is the oxide capacitance, e, is the permit-

tivity of the oxide and T, is the oxide thickness.

When the gate voltage is sufficiently negative to form a depletion region in the sil-

icon, the capacitance is that due to the senes combination of the oxide and the depletion

region capacitances:

As the depletion layer becomes wider, the capacitance associated with this region

decreases causing the total capacitance C, to decrease. For a sufficiently negative gate

voltage, an inversion layer forms, the depletion layer is at its maximum width, and the

total capacitance no longer decreases.

At low frequencies (between 5 and 100 Hz [3]), the generation of rninority carriers

(in our example, holes) is fast enough to keep up with small-signal variation of the mea-

surement signal. Therefore, the ac. measurement samples smail variations in the inversion

region rather than in the depletion region. Because of this effect, for measurements at very

low frequency the MOS capacitor in inversion resembles the parallel plate capacitor C,,

High frequency and QS capcitance-voltage measurements were performed on

MOS capacitors shown in Fig. A.2. Dimensions of MOS capacitor test structures are listed

in Table A. 1

AIso shown in Fig. A. I is the TLM structure used to measure the sheet resistance

of the polysilicon layer [4].

--


Appendix A- MOS Capacitor and PN Junction Cbaraçterizaton page 8 1

Fig. A 3 MOS Capacitor Test Chip

Table A.l Dimensions of MOS Capacitor Test Structures

A.2 Forward and Reverse Bias Diode Measurements

MOS Capacitor

a

The fonvard diode current of a pn junction taking into account series resistance rs

c m be written as:

Area ~1 ~ ~ ( r n ' )

4.49

where Io is the saturation current, n is the ideality factor and V the measured voltage across

the entire diode. A plot of Log (1) vs. V gives a straight line only over that portion of the

curve where kT/q cc V and Irs « il The measured current deviates from the straight Iine

at low currents due to the -1 in the bracket and deviates fkom the straight line at high cur-

rents due to the series resistance. The straight-line portion of the plot yields 2, by extrapo-

lation to V a , and it gives n from the slope as shown in Fig. A.3.


Appendix A- MOS Capacitor and PN Junction Characterizaton page 82

Fig. A 3 Log (I) vs. V for a PN Diode with Senes Resistance

The reverse -bias voltage across a diode may not increase without limit; at some

particular voltage, the reverse current will increase rapidly. The applied voltage at this

point is caiied the breakdown voltage. The breakdown voltage is a function of the geome-

try of the junction and is inversely proportionai to the impurity concentration on the lightly

doped side [SI

Forward and reverse bias 1-V measurements were performed on the pn junction

test chip shown in Fig. A.4. Also show in Fig. A.4 is TLM and six temiinal Kelvin stmc-

hue used to measure the sheet and contact resistance of the pn diodes respectively.

Fig. A.4 PN Junction Test Chip


Appendix A- MOS Capacitor and PN Junction Characterizaton Page 83

References

B. J. Gordon, "C-V Plotting: Myths and Methods", Solid-St. Tech., pp. 57-61, 1993.

HP4280A 1 MHz C Meter User's Manual, Analysis of the Serniconductor Capaci- tance Churacteristics, Hew let. Packard, 1 995.

S. M. Sze, Physics of Semiconductors Devices 2nd Edition, Wiley-Interscience, Chapter 7, 198 1.

D. K. Schroder, Semiconductor Materiai and Device Characterization, Wiley- Interscience, 1990.

L. Di Pede and D. Gradinam, "Clean Room Training Report", University of Tor- onto, 1994.


Appendix B- Layout Design Rules Page 84

Appendix B

LAYOUT DESIGN RULES

The layout design rules are based on very conservative assumptions to leave suffi-

cient margin for mask misalignment and greater than expected laterd diffusion of impur&

ties. This should result in working devices but not necessarily devices that occupy

minimum area. The design rules are based on the minimum feature size of 1 prn which is

imposed by the Karl Suss MA4 mask aligner. A subset of the layout design d e s are illus-

trated in Fig. B. 1. A complete set of design d e s are presented in Table B. 1.

NWELL ACTIVE P-GUARD n-Vt/PDEV PPOLY Gate-Etch CON METAL

Fig. B.l Layout Design Rules for a 1 V Low Power CMOS Process


Appendix B- Layout Design Rules page 85

Table B.1 Layout Design Rules for a Low Voltage CMOS Rocess

Layer Description Dimensions (pm)

NWELL 1 1.2 1 Minimum spacing

PGUARD 1 3.1 1 Minimum width 1 24

1.1

6

ACTIVE

1 3.2 1 Minimum overlap of NWELL 1 PDEV 1 4.1 1 Minimum overlap of ACTIVE 1 4

Minimum width

1.3

2.1

20

1 5.3 1 Minimum spacing to PDEV 1 4

Minimum overlap of ACTIVE

Minimum width

NDEV

MOLY 1 6.1 1 Minimum width 1 8

6

12

1 6.2 1 Minimum overlap of GATE ETCH 1 4

4.2

5.1

1 7.2 1 Minimum Overlap of Gate Etch 1 4

Minimum spacing to NDEV Minimum width

PPOLY

1 7.3 1 Minimum Spacing to NPOLY 1 4

4

12

GATEETCH 1 8.1 1 Minimum width 1 16

6.3 1 Minimum spacing to PPOLY 7.1 1 Minimum Width

4

8

1 9.2 1 Minimum spacing 1 4

CONTACT

1 9.3 1 Minimum overlap of ACTIVE 1 4

1

4

6

4x4

8.2 1 Minimum length

8.3 1 Minimum extension beyond ACTIVE

METAL

- - -

I -- 1 10.4 1 Minimum Overlap of Poly 4

8.4

9.1

10.2

10.3


Minimum spacing

Excat size

9.4

9 -5

10.1

Minimum spacing

Minimum overlap of ACTIVE contact

Minimum spacing to GATE ETCH Minimum overlap of GATE ETCH Minimum width

6

4

5

4

8

IMAGE NALUATlON TEST TARGET (QA-3)

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