6. design and evaluation of a low-cost

8/12/2019 6. Design and Evaluation of a Low-Cost

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 5, MAY 2014 2601

Design and Evaluation of a Low-CostHigh-Performance ADC for Embedded Control

Systems in Induction Heating AppliancesOscar Jimenez, Student Member, IEEE , Oscar Lucia, Member, IEEE , Isidro Urriza,

Luis A. Barragan, and Denis Navarro

Abstract The advantages of resonant power converters, suchas high efciency and high power density, make them a suitablesolution for domestic applications such as induction heating (IH)cookers. The control systems of these appliances require perform-ing accurate and smooth power control while assuring the safetyof the power devices. In order to accomplish these tasks, it is nec-essary to have information about the target output power, whichis selected by the user, and the specic parameters of the out-put current. In this paper, a single-bit second-order sigmadelta( ) analog-to-digital converter (ADC) is proposed to measurethe magnitude of interest in resonant power converters. An opti-mized digital low-pass lter architecture is proposed to extract theoutput current from the digitized bit stream. This lter improvesthe accuracy while having low logic-resource consumption. Theproposed ADC has been veried using a resonant inverter appliedto the IH cooktop application. The inverter switching frequencyis in the range of 4080 kHz. A statistical analysis of the nalmeasurement system has been performed to assess the systemaccuracy. The proposed system achieves good accuracy in theinverter operating range.

Index Terms Analog-to-digital converter (ADC), digital con-trol, induction heating (IH), resonant power conversion.

I. INTRODUCTION

T HE DOMESTIC induction heating (IH) market has ex-perienced in recent years a signicant growth due to itsadvantages such as safety, cleanliness, and higher efciency [1],in comparison with its other classical counterparts. Fig. 1(a)shows the block diagram of an IH system. The IH system iscomposed of four main subsystems: a user interface, a powerconverter, a digital control system, and a sigmadelta ( )analog-to-digital converter (ADC).

The user interface allows users to select the power deliveredto the vessel. The power converter transfers mains power to the

Manuscript received December 27, 2012; revised April 4, 2013 andJune 19, 2013; accepted August 4, 2013. Date of publication August 15, 2013;date of current version October 18, 2013. This work was supported in partby the Spanish Ministry of Science and Innovation under Project TEC2010-19207, Project CSD2009-00046, Project IPT-2011-1158-920000, and FPUGrant AP2010-5267, in part by the Diputacin General de Aragn-FondoSocial Europeo (DGA-FSE), and in part by the Bosch and Siemens HomeAppliances Group.

The authors are with the Department of Electronic Engineering andCommunications, University of Zaragoza, 50018 Zaragoza, Spain (e-mail:[email protected]).

Color versions of one or more of the gures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identier 10.1109/TIE.2013.2278524

load. Manufacturers usually choose resonant power convertersdue to their high efciency and high power density implemen-tation. The most used topologies in domestic IH are half-bridge[2], [3], full-bridge [4], single-switch [5], and multiinvertertopologies [6], [7]. In this paper, the power converter featuresa half-bridge resonant converter operating with switching fre-

quency f sw between 40 and 80 kHz. In order to reduce thecommutation losses, the half-bridge converter operates underzero-voltage-switching conditions. The resonant load of thepower converter consists of a planar inductor situated below avessel and a series resonant capacitor C r . Usually, the couplingbetween the inductor coil and the pan is modeled as a equivalentseries resistor Req and inductor Leq [8]. Fig. 1(b) shows themain waveforms of the power inverter.

The digital control system controls the power transferred tothe pan by adjusting the modulation parameters of the rstpower stage [7], [9], [10]; then, it performs the other requiredtasks, such as verifying the proper switching conditions [11].In order to assure that the power devices of the inverter arekept inside the safe operational area, the control system re-quires the values of the following parameters of output currentio [see Fig. 1(b)]: peak value io, peak , mean of the absolutevalue io, mean , and rms value io, rms . These measurements arecomputed at each half period of the mains T B . Then, thecontrol system can be divided into two blocks: the control unitand the measurement block. The control unit block generatesthe gating signals of the power devices (S1 and S2), takinginto account user input and output current measurements. Themeasurement block measures the required current parametersfrom the reconstructed output current ir provided by the ADC. Despite that the nal system will be implemented in

an application-specic integrated circuit, in this paper, eld-programmable gate array (FPGA) technology is used to verifythe digital system [12], [13].

The ADC subsystem digitizes the output current. modulators are widely used in power electronics eitheras ADCs [14][18] or pulsewidth modulators [19][21]. ADCs combine oversampling and shaping of the quantizationnoise to achieve high accuracy, which makes them a cost-effective and efcient solution [18], [22], [23]. Due to do-mestic IH being a cost-oriented application and the trend toimplement multiload hobs [24], this paper proposes a second-order ADC as a cost-effective solution. Despite that someintegrated ADCs are available [16], [18], the modulator

0278-0046 2013 IEEE


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2602 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 5, MAY 2014

Fig. 1. Domestic IH system. (a) General block diagram. (b) Power converter waveforms.

is implemented with discrete elements to optimize the converteraccording to the target application.

The output current digitization is carried out in three steps.First, the output current is sensed and conditioned to the modulator dynamic range (DR). The conditioning circuit con-sists of a current transformer with a turns ratio of CTR, anda burden resistor R T . Second, a modulator digitizes theconditioned output current x(t) into a single-bit data streamibs . Finally, the digital low-pass lter (LPF) block reconstructsoutput current ir by ltering ibs .

The aim of this paper is to propose a measurement system formeasuring the current parameters of the power stage requiredby the IH control system. This paper presents the analysis anddesign of the ADC, the experimental verication of theproposed system and, nally, a calibration process in order to

assess the quality of the measurements.Several works have proposed rst-order single-bit

ADCs to digitize the output current of IH systems [1], [14].Although this converter architecture has very low cost im-plementation and achieves good accuracy in power measure-ment, the measurements of current parameters, particularlythe peak current, do not achieve the desired accuracy. Hence,this paper proposes a second-order single-bit ADCs inorder to improve the accuracy of the measurement systemwhile maintaining low-cost solution. The improvement of themeasurement quality would allow a control system to performa better control algorithm and to ensure the safety of theconverter. In [25], a second-order single-loop single-bit

ADC is presented for measuring the magnitude of interest in

power converters connected to a dc power supply. Based onthis study, we propose to use a ADC to measure theoutput current in half-bridge power converters used in domesticIH appliances [1]. The analysis presented in [25] has beenextended to cover rectied ac power supply, as shown in Fig. 1.Several oversampling ratios (OSRs) have been considered, anda statistical analysis of the nal measurement system has beencarried out in order to evaluate the system accuracy.

This paper is organized as follows. Section II explains the modulator design. Section III describes the ADCdigital lter design. The main experimental results are shownin Section IV. The calibration process is detailed in Section V.Finally, the conclusions of this paper are drawn in Section VI.

Fig. 2. Second-order modulator block diagrams. (a) Continuous-timediagram. (b) Discretized and linearized block diagram.

II. S IGMA D ELTA M ODULATOR D ESIGN

A. SigmaDelta Modulator Analysis

ADCs [26] use the modulation noise-shapingproperty and oversampling techniques to allow high-resolutionconversion. Assuming white quantization noise, the oversam-pling technique reduces the in-band quantization noise spread-ing its power along the frequency range dened by samplingfrequency f s . Thus, the sampling frequency is usually selected

to be signicantly higher than the Nyquist rate. The samplingfrequency sets the OSR, which is dened as the quotient be-tween sampling frequency f s and the Nyquist rate of the signal.In addition, the noise-shaping property place most of the quan-tization noise in the high frequency range to minimize in-bandnoise. The noise shape depends on the modulator order.Higher modulator orders allow higher in-band noise reduction.Nevertheless, single-loop single-bit modulators with anorder higher than two have instability issues [26]. Thus, inthis paper, a continuous-time second-order single-loop single-bit ADC has been chosen.

Fig. 2(a) shows the continuous-time block diagram of asecond-order single-loop single-bit modulator. It consistsof two integrator stages, a single-bit quantizer, and a sample-and-hold circuit. This ADC digitizes input signal x(t) into


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JIMENEZ et al. : DESIGN AND EVALUATION OF ADC FOR EMBEDDED CONTROL SYSTEMS 2603

single-bit signal ibs (k) at sampling rate f s . Fig. 2(b) shows thelinearized and discretized second-order modulator block diagram. The transformation from the continuous-time domainto the discrete-time domain has been done using the forwardEuler method. Thus, the integrators transfer functions are

I 1 (z) = 1

(1 z 1 ) (1)

I 2 (z) = z 1

(1 z 1 ). (2)

The rst integrator I 1 does not consider the delay term in thenumerator in order to obtain delay unity in the signal-to-outputtransfer function (STF). In addition, sampling period T s hasbeen included in coefcients and to simplify the equations.The relationships between the continuous-time and discrete-time coefcients are x = ax T s and x = bx T s , respectively.

The nonlinear quantizer has been modeled as white noisesource n plus gain factor kq [26]. The STF and the noise-to-output transfer function (NTF) for the proposed ADC are

STF = y(z)x(z)

= kq 1 2 z 1

1 + z 1 (kq 1 2 + kq 2 2) + z 2 (1 kq 2 ) (3)

NTF = y(z)n(z)

= (1 z 1 )2

1 + z 1 (kq 1 2 + kq 2 2) + z 2 (1 kq 2 ). (4)

Thus, the low-frequency gain of the modulator is

G = STF (z = 1) 1 1

. (5)

The modulator coefcients ( 1 , 2 , 1 , and 2 ) de-ne the ADC performance, which can be specied with theconverter attributes shown in Fig. 3, i.e., SNR, the signal-to-noise-plus-distortion ratio (SNDR), the overload amplitudelevel (OL), and the DR [26]. Fig. 3 shows how SNR andSNDR curves fall for higher amplitudes. The OL point is themaximum amplitude of the input sinusoidal signal, for whichthe modulator still works correctly. In this paper, the OL point is

set at the amplitude where the SNDR falls 6 dB below the peak SNDR value. Finally, the DR value is the rms amplitude rangebetween the smallest detectable amplitude and the overloadlevel.

The converter attributes also depend on the OSR. Dueto the fact that, in this paper, the clock frequency of the digitalsystem is f clk = 40 MHz, three sampling frequencies have beenanalyzed: 10, 20, and 40 MHz. Considering an input signalbandwidth of B i = 250 kHz, the selected sampling frequenciesentail the following OSRs, respectively, i.e., 20, 40, and 80.

The converter coefcients and the OSR have been chosenthrough Matlab simulations [27]. The simulation test benchconsists of two simulation levels. The rst level obtains theSNR or SNDR value for a specic set of converter parametersat a given input signal amplitude Ain . In this level, an input

Fig. 3. Second-order ADC performance characteristics for f s =20 MHz, 1 = 0 .134 , 1 = 0 .15 , 2 = 0 .7 , and 2 = 0 .448 .

signal composed by a sine wave (175 kHz for SNR and 75 kHzfor SNDR) of amplitude Ain and white noise (2N = 130 dB)is used. The output bit stream is ltered by an eighth-order Butterworth LPF with a cutoff frequency of f c = B ito remove all out-of-band noise. Finally, the IEEE sine-wavetting method [28] is applied to the ltered signal to extractthe SNR or SNDR value at this amplitude. The second levelof simulation, making use of the rst level, performs amplitudesweeps of the input signal to obtain the SNR and SNDR curves.

Prior to the converter coefcient selection, two design con-straints are introduced.

1) Stability criteria : The modulator has to be stable,which means that 2 1 / 2 < 3/ 4, as in [27].

2) Full-scale (FS) input support : The modulator op-erates in a high-noise environment due to the presence of a switched-mode inverter. To maximize the input signalx(t) SNR parameter, it is advisable to make the mostof the ADC input range. Thus, the modulator is

designed to operate with an FS input, i.e., OL = FS.The FS value takes the value of the supply voltage V CCwhen implementing a dual supply or half of it whenimplementing a single supply. The overload level can betuned using coefcient 1 . For specic 2 , 1 , and 2 co-efcients, the SNR and SNDR curves can be horizontallyshifted by tuning 1 , and consequently, OL is also shifted.If coefcient 1 is increased, the curves are shifted tothe left.

B. Selection Procedure

The selection procedure can be divided into two steps. Inthe rst step, different converters with an ADC gain of 1, i.e., 1 = 1 , have been tested for the three OSRs. This analysisallows extracting the attributes of the converter for specic 1 , 2 , and 2 coefcients. However, FS input support is notassured. The second step modies the gain of the converter byselecting coefcient 1 for conguring the converter with FSinput support.

The converters analyzed in the rst step of the selectionprocess are the combination of coefcients 1 and 2 in therange of [0.05, 1] with a step of 0.05, and the coefcient 2in the range of [S lim , 5S lim ] with a step of 0.2 S lim , whereS lim is the stability limit with respect to 2 and 2 , i.e., 2 > S lim = 2 1 4/ 3. For each converter, the SNR and SNDRcurves have been obtained in order to extract the attributes


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Fig. 4. SNR curves of the best analyzed second-order converter foreach OSR.

of the converter. The chosen converter parameters are thosethat yield the maximum values of SNR and SNDR. Fig. 4shows the SNR curves of the converters selected for each OSRvalue. The coefcients of the converter with OSR = 20 are 1 = 1 = 0.25, 2 = 0 .6, and 2 = 0 .44; the coefcients of the converter with OSR = 40 are 1 = 1 = 0 .15, 2 = 0.7,and 2 = 0 .448; and the coefcients of the converter withOSR = 80 are 1 = 1 = 0 .15, 2 = 0.5, and 2 = 0 .28. Asexpected, the attributes of the converter with OSR = 40 signif-icantly improve the attributes of the converter with OSR = 20 .However, due to system noise, the attributes of the converterwith OSR = 80 slightly improve the attributes of the converterwith OSR = 40 . In view of these results, a second-order ADC with OSR = 40 has been chosen to be implemented.

The second step of the selection process tunes the 1 coef-cient to obtain FS input support, leading to 1 = 0 .134. Theintegrator coefcients result in the ADC performance shownin Fig. 3, where SNRmax = 56 .7 dB, SNDRmax = 54 .2 dB,

OL = FS , DR = 58 .1 dB, and gain G = 0 .89.

C. Circuit Implementation

The schematic circuit of the designed ADC is shownin Fig. 5. The supply voltage of the converter is V CC = 3 .3 V.The relationship between the passive components and the modulator coefcients are given by

R n C n = 1f s n

(6)

where n = 1 , 2 , 1 , or 2 . The selected values for thepassive components are R

= 2 .5 k 1%, R

= 2.21 k 1%,

C 1 = 150 pF 10%, R = 475 1%, R = 750 1%, andC 2 = 150 pF 10%. Thus, the resulting coefcients are 1 = 0 .133, 1 = 0 .151, 2 = 0 .702, and 2 = 0 .444.

The ADC stability has been veried in the componenttolerance ranges. The converter attributes for the nominal com-ponent values are SNRmax = 56 .3 dB, SNDRmax = 54 .9 dB,OL = FS, DR = 60 dB, and G = 0 .884.

III. D IGITAL F ILTER D ESIGN

In order to measure the required current parameters, i.e.,io, peak , io, mean , and io, rms , output current io has to be ex-tracted from the ADC output ibs . A digital LPF archi-tecture reconstructs the output current by removing most of the

Fig. 5. Second-order sigmadelta ADC schematic circuit.

Fig. 6. Implementation block diagram for the CIC lter.

quantization noise. In this paper, a cascaded integratorcomb(CIC) lter has been chosen as a hardware-effective solution[29], [30]. The difference equation for the rst-order CIClter is

m(k) = 1d

d 1

i =0

y(k i). (7)

CIC lters perform a moving average over the last d sam-

ples. To minimize the logic-resource consumption, this lterhas been implemented as shown in Fig. 6. Moreover, the dparameter has been selected to be a power of two to avoidthe hardware division implementation. According to [31], theCIC lter order has been selected to be one order more than the modulator order, i.e., a third-order lter has been chosen.

The LPF removes most of the quantization noise while allow-ing the desired bandwidth to pass through with low attenuation.The CIC lter frequency response is a sinc whose rst zerois placed at f z = f s /d . Thus, the d parameter sets both, i.e.,the rst zero position and cutoff frequency f c . In this paper,three lters have been evaluated: a second-order CIC lter withd = 8 , a third-order CIC lter with d = 8 , and a cascade of asecond-order CIC lter with d = 8 and a rst-order CIC lterwith d = 16 . Fig. 7 shows the frequency response magnitudefor the evaluated lters. The frequency responses show thatthe CIC28 + CIC 16 lter has the higher attenuation at highfrequencies, which entails better quantization noise ltering,but it also has higher attenuation at the highest frequencies of the signal bandwidth.

The performance of the proposed lters has been evaluatedthrough simulation. Fig. 8 shows the current measurementrelative errors r for the three lters and the proposed second-order ADC. The relative error has been dened as

r = 100 I meas I I (8)


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Fig. 7. Magnitude of the frequency responses of the evaluated lters.

Fig. 8. Current measurement relative errors for different lters. (a) Error inpositive peak. (b) Error in mean of the absolute value. (c) Error in rms value.

where I is the reference magnitude obtained through a circuitalsimulation during T B = 10 ms, and I meas is the same magni-tude measured with the proposed system.

Fig. 8(a) shows the error in the current positive peak forthe whole power-converter frequency range of operation. Thepeak error for the CIC38 lter reaches 20%, which is insufcientfor the IH application. Thus, the CIC 28 + CIC 16 lter has beenselected to perform this measurement. Fig. 8(b) and (c) showsthe error in mean and rms current values, respectively. In thesemeasurements, the CIC28 + CIC 16 lter shows higher errorthan the CIC 38 lter due to the lter attenuation on the signalbandwidth. As expected, these errors get worse as the current

Fig. 9. Selected lter architecture.

frequency increases. Thus, the CIC 38 lter has been chosen forthe mean of the absolute and rms calculation.

Fig. 9 shows the nal lter architecture and the measure-ments obtained from each lter. This lter topology has beenoptimized to achieve the required accuracy while keeping the

lter to a reasonable size. The measurement block measuresthe current parameters during the mains half-cycle from thereconstructed currents ir . The peak value is obtained as themaximum of the reconstructed signal ir, CIC 28 +CIC 16 . The meanof the absolute is computed as

io, mean = 1N

N 1

n =0

ir, CIC 38 (n) (9)

where N is the number of samples taken into account in themeasurement, i.e., the number of samples of a mains half-cycle.Finally, the current rms value is computed as

io, rms = 1N N 1

n =0

i2r, CIC 38 (n). (10)

IV. E XPERIMENTAL V ERIFICATION

The experimental verication of the designed second-order ADC has been carried out in two steps. The rst stepveries the modulator by means of frequency analysisand the extraction of the modulator parameters. The secondone veries the ADC behavior while working under real

conditions.Fig. 10 shows the test bench used for the experimentalverication [32]. It is made up of four subsystems: the powerconverter, the modulator, the FPGA board, and the userinterface. The power converter features a half-bridge series-resonant inverter designed for the IH application. The powerconverter operates with switching frequencies between 40 and80 kHz. In addition, this stage implements the output-currentconditioning circuit. The modulator board implements theproposed second-order modulator. The ADC samplingfrequency is 20 MHz. The digital system has been embedded ina Xilinx Spartan-6 FPGA included in an ATLYS developmentboard from Digilent. Finally, a Matlab-based graphical interfaceis using for controlling the modulation parameters of the powerconverter and retrieving the system results.


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Fig. 10. Experimental test bench.

TABLE IPARAMETERS OF PSD E STIMATION

A. ADC Analysis

In this analysis, the designed modulator is tested. First,the noise-shaping capability of the modulator is veried by

means of a frequency analysis. Second, the attributes of theADC are obtained by using the IEEE standard sine-wave ttingmethod. In both analysis, analog input signal x(t) is generatedby a Tektronix AFG3022 sine-wave generator.

The verication of the modulator noise-shaping prop-erty has been carried out by computing the power spectraldensity (PSD) estimation of the modulator output ibs . ThePSD has been calculated by using Welchs method P w (ejw )[33] with the parameters shown in Table I. Both frequencyand amplitude sweeps of the input sine-wave signal have beenperformed to verify the modulator behavior in the wholeoperating range.

Fig. 11 shows the simulated and experimental PSD estima-tions of the second-order modulator output ibs for an inputsine-wave signal of amplitude Asin = 0 .5 V and frequencyf sin = 75 kHz.

Following the frequency analysis, the attributes of the ADCare measured from the SNR and SNDR curves. To obtain thesecurves, amplitude sweeps of the input sine-wave signal x(t)have been performed for the whole ADC DR. In Fig. 12,simulation and experimental results of the ADC performanceare merged together. Because SNR and SNDR curves areaffected by the noise in the system, Fig. 12 represents the meanvalue of 50 measurements per amplitude. The SNR and SNDRcurves show good agreement between simulation and experi-mental results. The attributes of the implemented second-order ADC are SNRmax = 56 .5 dB, SNDRmax = 53.4 dB, and

Fig. 11. PSD estimation of the ADC output i bs . Simulation versus experi-mental results.

Fig. 12. ADC performance characteristics. Simulation versus experi-mental results.

OL = 0 .971. The DR attribute cannot be measured due to sine-wave generator limitations.

The DR of the ADC allow measuring output currentamplitudes up to 90 A, which covers the normal inverter op-erating conditions. However, the output current amplitude maybe higher than this value due to abnormal operating conditionssuch as short circuit or vessel removal. An output currentamplitude higher than 90 A deteriorates the modulatorbehavior or may even cause modulator instability. In spiteof the fact that the modulator does not work properly, thepeak current measurement is able to detect that the maximumcurrent value has been reached. This overcurrent detection isenough for the high-level control algorithm to execute thecorresponding security measures.

B. Complete System Verication

The complete system verication has been performed whileunder real operating conditions. Fig. 13 shows the power deliv-ered to the vessel versus switching frequency for the inductionload detailed in Table II. The values of the equivalent resis-tance Req and inductance Leq depend on the resonant inverteroperating point. Hence, these values have been specied atthe resonant frequency f o . The efciency of the half-bridgeresonant inverter depends on its operating point. Typically, theinverter efciency is in the range of 89%97% [34]. IH loadcharacteristics in conjunction with the power levels available indomestic induction appliances entail output current values of up to 90 A. To adapt these current levels to the ADCDR (03.3 V), a current transformer with CTR = 200 , and aburden resistor of RT = 3 .65 have been selected.


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Fig. 13. Output power versus switching frequency in the whole operatingrange.

TABLE IIINDUCTION L OAD PARAMETERS

In Fig. 14, the error in current measurements for the ltersincluded in the digital control system in the whole range of operation is shown. Fig. 14(a) shows the error in the positiveinductor current peak, Fig. 14(b) shows the error in the cur-rent mean of absolute, and Fig. 14(c) shows the error in therms measurement. The experimental values used for the errorcalculations at each frequency are the mean of 50 independentmeasurements. The experimental values have been comparedwith the measurements of a Tektronix TCP0030 current probeand a Tektronix DPO7354 oscilloscope congured to work with

high resolution ( > 11 bits), a sampling rate of 20 megasamplesper second (MSPS), and calculation time of 10 ms. As expected,the best results are obtained when using the (CIC 8 )2 + CIC 16lter for the peak measurement, and the (CIC 8 )3 lter for themean of the absolute and the rms measurements. Then, the lterarchitecture presented in Fig. 9 is selected to be implemented inthe nal measurement system.

The experimental output voltage and current at the limits of the switching frequency range for the load detailed in Table IIare shown in Fig. 15. Fig. 15(a) shows the output voltage andoutput current at the peak of the mains cycle when the inverterworks with a switching frequency of f sw = 40 kHz, i.e., closeto resonance. Fig. 15(b) shows the same waveforms when theinverter works with a switching frequency of f sw = 40 kHz.Close to resonance, the output current waveform has a sinusoid-like shape and high amplitude. However, as the switchingfrequency increases, the waveform shape gets a triangular formand the amplitude decreases.

Finally, Fig. 16 shows the experimental time-domain wave-forms of the output current when the inverter works with aswitching frequency of f sw = 40 kHz. The results show goodaccuracy in the reconstruction of the output power.

V. S YSTEM C ALIBRATION

The inductor current measurements are affected by severalerror sources in addition to the error caused by the algo-

Fig. 14. Error in current measurements for different lters. (a) Error inpositive peak value. (b) Error in the mean of the absolute value. (c) Error inrms value.

rithms. Among these error sources are the accuracy of thecurrent sensor, the tolerance of the passive components, and thenonidealities of the analog parts. For these reasons, the nalmeasurement system has to be calibrated [35]. This calibrationprocess assesses the quality of the proposed system measure-ments by using the measurements performed with a workingmeasurement standard, which is a measurement standard usedto calibrate instruments. In this paper, the working measure-ment standard is a Tektronix TCP0030 current probe and aTektronix DPO7354 oscilloscope congured to work with high-resolution, a sampling rate of 20 MSPS, and calculation time of 10 ms.

The measurement systems denote the accuracy of the systemby means of the uncertainty u. In metrology, the uncertainty of a measurement is the margin of error that limits the range of values that likely encloses the true value i. For that reason, themeasurement result is given as

i = L u

L = im i (11)

where im is the value calculated by the measurement system,and i is the bias of the measurement system. The uncertainty


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Fig. 15. Experimental output voltage vo (50 V/div) and output current io(15 A/div) waveforms. (a) Experimental results at switching frequency f sw =40 kHz. (b) Experimental results at switching frequency f sw = 80 kHz. Thetime is 5 s/ div.

Fig. 16. Experimental time-domain waveforms of the output current. Fromtop to bottom: output current, 1-bit data stream ADC output, recon-structed current with lter CIC 28 , reconstructed current with lter CIC

38 , and

reconstructed current with lter CIC 28 + CIC 16 .

can be specied by multiplying the standard deviation of themeasurement system sy by a factor k, i.e.,

u = ksy . (12)

A. Calibration at Each Calibration Point

The rst step in the calibration process is to obtain thebias and the uncertainty of the measurement system in each

Fig. 17. Bias in current measurements. (a) Values of the measurementsperformed with the working measurement standard. (b) Bias in the positivepeak. (c) Bias in the mean of the absolute and rms values.

operation point. In order to perform this task, in this paper,n c = 50 measurements have been captured at each calibrationpoint j . Then, the bias at each calibration point j , i.e., icj , iscalculated as

icj = icj ioj (13)

where icj is the mean value of the measurements at the cali-bration point j , and ioj is the working standard measurement.

Fig. 17(a) shows the value of the measurements obtainedwith the working measurement standard at the calibrationpoints considered in the calibration process. Fig. 17(b) and (c)shows the bias values at each calibration point for the threemeasurements.

The uncertainty of each calibration point is obtained throughthe variance calculation. In order to obtain the variance of the measurements at each calibration point, the propagation of uncertainty rule is applied to the error effects in the calibrationchain as follows:

s2j = s2oj + s

2cj + s

2mj (14)

where s2j is the variance of the measurement at the calibrationpoint j , s2oj is thevarianceof theworking standard measurement,


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Fig. 18. Uncertainty in current measurements for the selected lterarchitecture.

s2cj is the estimated value of the variance of the measures usedin the calibration process, and s2mj is the estimated value of the variance of the measurement sample working under realconditions. The variance at each calibration point leads to

s2j = s2oj +

s2icj

n c+

s2icj

n (15)

where s icj is the standard deviation of the measurements usedin the calibration process at the calibration point j , and n isthe number of samples used for each current measurement atreal working conditions, which is in the implemented systemn = 1 . Fig. 18 shows the uncertainties of the measurements ateach calibration point ucj setting k = 2 in order to obtain aninterval of condence of 95%, considering the uncertainty of the working standard 1% with an interval of condence of 99%.

B. Calibration in the Whole Measurement Range

In the second step in the calibration process, a unique value of uncertainty is given for the whole operating range that considersthe variance and the bias. For calculating the global uncertainty,rst, the uncertainty of each point of calibration is obtained withan interval of condence of 95% (k = 2) . Considering (10) and(13), and including the bias in the error chain, the uncertaintycan be calculated using

u j = 0.44u2oj + k2 s2icj 1n c + 1n + i2cj (16)where u i is the uncertainty of the calibration point j , and uoj

is the working standard uncertainty in the calibration point j . Finally, the uncertainty of the measurement system is themaximum of the obtained uncertainties; thus, u = max( u j ).

The global uncertainties of the measurements performedwith the proposed measurement system (second-order ADC) are presented in Table III, together with the uncertaintiesobtained with a measurement system that performs a rst-order ADC. These results show that the proposed measurementsystem offers better accuracy in the measurements while keep-ing low-cost implementation. The uncertainty is a conservativevalue that indicates the maximum absolute error in the wholeoperating range with an interval of condence of 95%. Inaddition to this, the experimental results show that the proposedsystem achieves accuracy better than 9% for the peak currentand better than 1% for the mean and rms values.

TABLE IIIG LOBAL U NCERTAINTY

VI. C ONCLUSION

In this paper, a low-cost solution for measuring the mainrequired current parameters of a resonant power converterapplied to IH has been presented. The proposed system consistsof a second-order single-bit ADC and a digital lterarchitecture. A general design procedure for designing the ADChas been explained, and an optimized lter architecture hasbeen proposed to improve the accuracy and hardware resources.

The proposed architecture has been experimentally testedwith an induction-heating resonant converter. A calibrationprocess has been performed in order to assess the quality of themeasurement system. This calibration process shows that themeasurement system achieves accuracy better than 9% in peak current measurement and 1% in mean of the absolute and rmsmeasurements. The achieved accuracy is good enough to bothperform proper output power control and to ensure the safety of the converter.

In addition, the proposed architecture can be easily extendedto any other power converter. This paper considers the outputcurrent DR from 90 to 90 A when operating under nor-mal conditions. However, the measurement system DR can

be adapted to the specic application by selecting the currenttransformer turns ratio CTR value and/or the burden resistorRT value.

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Oscar Jimenez (S10) received the M.Sc. degreein telecommunication engineering from the Univer-sity of Zaragoza, Zaragoza, Spain, in 2009. He iscurrently working toward the Ph.D. degree in theDepartment of Electronic Engineering and Commu-nications, University of Zaragoza.

His current research interests include domesticinduction heating, resonant inverters, and digital con-trol applied to power converters.

Mr. Jimenez is a member of the Aragon Institutefor Engineering Research.

Oscar Lucia (SM04M11) received the M.Sc. andPh.D. degrees in electrical engineering from the Uni-versity of Zaragoza, Zaragoza, Spain, in 2006 and2010, respectively.

He has been with the Department of ElectronicEngineering and Communications, University of Zaragoza, where he is currently an Assistant Profes-sor. His main research interests include multiple out-put converters, digital control, and resonant powerconversion for induction heating applications.

Dr. Lucia is a member of the Aragon Institute forEngineering Research.

Isidro Urriza received the M.Sc. and Ph.D. de-grees in electrical engineering from the Universityof Zaragoza, Zaragoza, Spain, in 1991 and 1998,respectively.

He is currently an Associate Professor with theDepartment of Electronic Engineering and Commu-nications, University of Zaragoza. He has been in-volved in various research and development projects.His main research interests include digital im-

plementation of modulation techniques for powerconverters.Dr. Urriza is a member of the Aragon Institute for Engineering Research.


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Luis A. Barragan received the M.Sc. and Ph.D.degrees in physics from the University of Zaragoza,Zaragoza, Spain, in 1988 and 1993, respectively.

He is currently an Associate Professor with theDepartment of Electronic Engineering and Commu-nications, University of Zaragoza. He has been in-volved in various research and development projectson induction heating systems for home appliances.

His research interests include digital circuit designand digital control of inverters for induction heatingapplications.

Dr. Barragan is a member of the Aragon Institute for Engineering Research.

Denis Navarro received the M.Sc. degree in mi-croelectronics from the University of Montpellier,Montpellier, France, in 1987 and the Ph.D. degreefrom the University of Zaragoza, Zaragoza, Spain,in 1992.

Since September 1988, he has been with theDepartment of Electronic Engineering and Commu-nications, University of Zaragoza, where he is cur-

rently an Associate Professor. In 1993, he designedthe rst SPARC microprocessor in Europe. He isinvolved in the implementation of new applications

of integrated circuits. His current research interests include computer-aided de-sign for very large scale integration, low-power application-specic integratedcircuit design, and modulation techniques for power converters.

Dr. Navarro is a member of the Aragon Institute for Engineering Research.

6. design and evaluation of a low-cost

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