1

4-Integrating Peripherals in Embedded Systems (cont.)

2

Using LEDs and switches•The DE2 board provides four pushbutton switches. Each of these switches is debounced using a Schmitt Trigger circuit.

• The four outputs called KEY0, …, KEY3 are connected directly to the Cyclone II FPGA.

•Each switch provides a high logic level (3.3 volts) when it is not pressed, and provides a low logic level (0 volts) when•depressed.

•Since the pushbutton switches are debounced, they are appropriate for use as clock or reset inputs in a circuit.

3

Using LEDs and switches

4

Using LEDs and switches

5

Using LEDs and switchesThere are also 18 toggle switches (sliders) on the DE2 board.

These switches are not debounced, and are intended for use as level-sensitive data inputs to a circuit.

When a switch is in the DOWN position (closest to the edge of the board) it provides a low logic level (0 volts) to the FPGA, and when the switch is in the UP position it provides a high logic level (3.3 volts).

6

Using LEDs and switches

7

Using LEDs and switches•There are 27 user-controllable LEDs on the DE2 board.

•Eighteen red LEDs are situated above the 18 toggle switches

•Eight green LEDs are found above the pushbutton switches (the 9th green LED is in the middle of the 7-segment displays).

•Each LED is driven directly by a pin on the•Cyclone II FPGA; driving its associated pin to a high logic level turns the LED on, and driving the•pin low turns it off.

8

Using LEDs and switches

9

Using LEDs and switches

10

Seven Segment Display

•The DE2 Board has eight 7-segment displays. These displays are arranged into two pairs and a group of four, with the intent of displaying numbers of various sizes.

•Applying a low logic level to a segment causes it to light up, and applying a high logic level turns it off.

11

LED_pio.vmodule led_red ( // inputs: address, chipselect, clk, reset_n, write_n, writedata,

// outputs: out_port );

output [ 17: 0] out_port; input [ 1: 0] address; input chipselect; input clk; input reset_n; input write_n; input [ 17: 0] writedata;

wire clk_en; reg [ 17: 0] data_out; wire [ 17: 0] out_port; assign clk_en = 1;

always @(posedge clk or negedge reset_n) begin if (reset_n == 0) data_out <= 0; else if (chipselect && ~write_n && (address == 0)) data_out <= writedata[17 : 0]; end

assign out_port = data_out;

endmodule

12

Switch_pio.v module switch_pio ( // inputs: address, clk, in_port, reset_n,

// outputs: readdata ) ;

output [ 17: 0] readdata; input [ 1: 0] address; input clk; input [ 17: 0] in_port; input reset_n;

wire clk_en; wire [ 17: 0] data_in; wire [ 17: 0] read_mux_out; reg [ 17: 0] readdata; assign clk_en = 1; //s1, which is an e_avalon_slave assign read_mux_out = {18 {(address == 0)}} & data_in; always @(posedge clk or negedge reset_n) begin if (reset_n == 0) readdata <= 0; else if (clk_en) readdata <= read_mux_out; end

assign data_in = in_port;

endmodule

13

Button_pio.v (1)module button_pio ( // inputs: address, chipselect, clk, in_port, reset_n, write_n, writedata, // outputs: irq, readdata );

output irq; output [ 3: 0] readdata; input [ 1: 0] address; input chipselect; input clk; input [ 3: 0] in_port; input reset_n; input write_n; input [ 3: 0] writedata;

wire clk_en; reg [ 3: 0] d1_data_in; reg [ 3: 0] d2_data_in; wire [ 3: 0] data_in; reg [ 3: 0] edge_capture; wire edge_capture_wr_strobe; wire [ 3: 0] edge_detect; wire irq; reg [ 3: 0] irq_mask; wire [ 3: 0] read_mux_out; reg [ 3: 0] readdata; assign clk_en = 1;

14

Button_pio.v (2) assign read_mux_out = ({4 {(address == 0)}} & data_in) | ({4 {(address == 2)}} & irq_mask) | ({4 {(address == 3)}} & edge_capture);

always @(posedge clk or negedge reset_n) begin if (reset_n == 0) readdata <= 0; else if (clk_en) readdata <= read_mux_out; end

assign data_in = in_port; always @(posedge clk or negedge reset_n) begin if (reset_n == 0) irq_mask <= 0; else if (chipselect && ~write_n && (address == 2)) irq_mask <= writedata[3 : 0]; end

assign irq = |(edge_capture & irq_mask); assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3); always @(posedge clk or negedge reset_n) begin if (reset_n == 0) edge_capture[0] <= 0; else if (clk_en) if (edge_capture_wr_strobe) edge_capture[0] <= 0; else if (edge_detect[0]) edge_capture[0] <= -1; end

15

Button_pio.v (3)always @(posedge clk or negedge reset_n) begin if (reset_n == 0) edge_capture[1] <= 0; else if (clk_en) if (edge_capture_wr_strobe) edge_capture[1] <= 0; else if (edge_detect[1]) edge_capture[1] <= -1; end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) edge_capture[2] <= 0; else if (clk_en) if (edge_capture_wr_strobe) edge_capture[2] <= 0; else if (edge_detect[2]) edge_capture[2] <= -1; end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) edge_capture[3] <= 0; else if (clk_en) if (edge_capture_wr_strobe) edge_capture[3] <= 0; else if (edge_detect[3]) edge_capture[3] <= -1; end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin d1_data_in <= 0; d2_data_in <= 0; end else if (clk_en) begin d1_data_in <= data_in; d2_data_in <= d1_data_in; end end

assign edge_detect = ~d1_data_in & d2_data_in;endmodule

16

Seven Segment Display: Pin assignment

Shown above the pin assignments for segment digit 0 only

17

Seven Segment Display: Pin assignment

18

Cont.

19

Seven segment module SEG7_LUT ( oSEG,iDIG ); input [3:0] iDIG; output [6:0] oSEG; reg [6:0] oSEG;

always @(iDIG) begin case(iDIG) 4'h1: oSEG = 7'b1111001; // ---t---- 4'h2: oSEG = 7'b0100100; // | | 4'h3: oSEG = 7'b0110000; // lt rt 4'h4: oSEG = 7'b0011001; // | | 4'h5: oSEG = 7'b0010010; // ---m---- 4'h6: oSEG = 7'b0000010; // | | 4'h7: oSEG = 7'b1111000; // lb rb 4'h8: oSEG = 7'b0000000; // | | 4'h9: oSEG = 7'b0011000; // ---b---- 4'ha: oSEG = 7'b0001000; 4'hb: oSEG = 7'b0000011; 4'hc: oSEG = 7'b1000110; 4'hd: oSEG = 7'b0100001; 4'he: oSEG = 7'b0000110; 4'hf: oSEG = 7'b0001110; 4'h0: oSEG = 7'b1000000; endcase end

endmodule

20

LCD controller

E

R/W

RS

DB7–DB0

LCD controller

communications bus

microcontroller8

void WriteChar(char c){

RS = 1; /* indicate data being sent */ DATA_BUS = c; /* send data to LCD */ EnableLCD(45); /* toggle the LCD Enable with delay of 45 units of time*/}

CODES

I/D = 1 cursor moves left DL = 1 8-bit

I/D = 0 cursor moves right DL = 0 4-bit

S = 1 with display shift N = 1 2 rows

S/C =1 display shift N = 0 1 row

S/C = 0 cursor movement F = 1 5x10 dots

R/L = 1 shift to right F = 0 5x7 dots

R/L = 0 shift to left

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description

0 0 0 0 0 0 0 0 0 1 Clears all display, return cursor home

0 0 0 0 0 0 0 0 1 * Returns cursor home

0 0 0 0 0 0 0 1 I/D SSets cursor move direction and/orspecifies not to shift display

0 0 0 0 0 0 1 D C BON/OFF of all display(D), cursorON/OFF (C), and blink position (B)

0 0 0 0 0 1 S/C R/L * * Move cursor and shifts display

0 0 0 0 1 DL N F * *Sets interface data length, number ofdisplay lines, and character font

1 0 WRITE DATA Writes Data

21

Altera DE2 LCD moduleThe LCD module has built-in fonts and can be used to display text by sending appropriatecommands to the display controller (HD44780).

22

LCD module: Pin assignments

23

Lcd_16207.vmodule lcd_16207_0 ( // inputs: address, begintransfer, read, write, writedata,

// outputs: LCD_E, LCD_RS, LCD_RW, LCD_data, irq, readdata ); output LCD_E; output LCD_RS; output LCD_RW; inout [ 7: 0] LCD_data; output irq; output [ 7: 0] readdata; input [ 1: 0] address; input begintransfer; input read; input write; input [ 7: 0] writedata;

wire LCD_E; wire LCD_RS; wire LCD_RW; wire [ 7: 0] LCD_data; wire irq; wire [ 7: 0] readdata; assign LCD_RW = address[0]; assign LCD_RS = address[1]; assign LCD_E = read | write; assign LCD_data = (address[0]) ? 8'bz : writedata; assign readdata = LCD_data; //control_slave, which is an e_avalon_slave

endmodule