4 Bit Serial to Parallel Data Stream Converter

4 Bit Serial to Parallel Data Stream Converter

Vinaya AnneKristy LypenMichael ScheelVictor Zavaleta

Vinaya AnneKristy LypenMichael ScheelVictor Zavaleta

Design Specifications

Convert a serial data stream every 4 clock cycles to a 4 bit parallel stream

Operate at the positive edge of the clock Drive a 10pF load at 25MHz Minimize skew Area less than 40mil2

Parameters

D Flip-Flop• WnCaclulated = 10.4 m WnActual = 23.2 m• WpCaclulated = 27.6 m WpActual = 27.6 m

• Based on CLoad of Output = 179f F

Buffer

Total Area: 1750 x 600 m Power: 400mW

Stage Wp (m) Wn (m)

One 300 100

Two 80 28.8

Three 25.2 9.2

Block Diagram

Schmidt

Trigger

Frequency

Counter

SERIAL

D FlipFlop

D FlipFlop

D FlipFlop

Latch /

Buffer

DATA

PARALLEL

DATA

Schmidt Trigger Schematic

Trip Points of Schmidt Trigger

D Flip-Flop Schematic

D Flip-Flop Propagation Delay Waveform

Schematic D Flip-Flop / Logic Circuit

Output Waveforms

Layout of Four D Flip-Flops

Clock

Buffer Schematic

Buffer Transient Response

Questions?Questions?