3.1

3 Process and Device Physics

1. Quantum-Theoretical Definition of Semiconductor

2. PN Diode

3. MOS(Metal-Oxide-Semiconductor) Capacitor Theory

4. Ideal MOSFET : I-V Relations

5. Actual MOSFET(Secondary Effects)

6. CMOS Process

7. CMOS Layout Design Rules

8. SPICE Model for MOSFET

Contents

3.2

1. Quantum Theoretical Definition of Semiconductor

Semiconductor No.1 Property;

Two charge carriers(electron & hole) existing in energy bands separated by Eg

Two important facts about semiconductor(or Semiconducting Crystal) ; Band Gap & Fermi Level

Band Gap(between Conduction & Valence band) Discrete energy levels in Isolated Quantum Well

E=0

Energy level

3.3

Perturbation of discrete energy levels in multiple QW’s in interacting distance(plus the effect of finiteness of energy wall)

Energy level becomes Energy band

Eg

(Energy Gap)

“nucleus”

EF(Fermi Level)

If the structure is non-periodic, the allowed energy levels constitute continuum.

3.4

Fermi Level(P(EF)=0.5 always)

According to Fermi-Dirac Statistics, P(E) = Probability of energy level, E being occupied by a particle, is

~1+exp[(E-EF)/kT]

1

T=0

E

P(E)

EF

E=0

Ec

Ev

full

empty

EgEF

T0

freeelectron

hole

nucleus

0.5P(E)

3.5

Fermi Level(cont’)

Impurity-doped Semiconductor ; electron & hole populations are unbalanced by doping n-type & p-type atoms, respectively.

(n-type Semiconductor)

Ec

Ev

EF

(p-type Semiconductor)

EF

Excesselectron

Phosphorus

Silicon

(n-type Semiconductor)

Deficit of electron=hole

BoronSilicon

(p-type Semiconductor)

3.6

2. P-N Diode

3.7

3.8

In Equilibrium, particle movement, in macroscopic sense, has stopped(i.e., no current flow in case of charged particle) ; therefore Fermi level is constant throughout all locations in equilibrium, i.e., connected and unbiased

(n-type Semiconductor)(p-type Semiconductor)

Ec

EF

EV

EFP

EFN

3.9

Forward bias :

P N

I

VF

Reverse bias :

VF

I

VB

V

VR

3.10

3. MOS Capacitor Theory

MOS Capacitor : combination of Metal, (Perfect Conductor), Oxide(Perfect Insulator in DC Sense, and good Dielectric in AC sense), and Semiconductor substrate.

(Oxide)

EFM

(metal)

(p-type silicon)

Ec

EFS,P

EV

M

S,P

(M) (O) (S)

: Minimal energy an electron needs to escape from inside metal(silicon) to air

Deple-tionRegion

P-Si

V

[V=0]

[separation]

M( S)

M S,P

3.11

flat-band conditionflat-band condition

V=VFB

VFB = MS - VFB = MS - Qfc

Cox

MS = M - S(Work Function Difference)

Qfc : Fixed charge per area

Cox : Oxide capacitance per unit area

Flat-band voltage(VFB)

3.12

Inversion conditionInversion condition

Xd

s

(M) (O) (P-Si)

Ec

Ei

EF

X=0

F

VT = VFB + 2F +QB

Cox

F = Ei - EF

q

QB = charge per unit surface area

= qNAXD

Threshold voltage (VT)

3.13

From Gauss’ Theorem, D = E= - (x)

xxxx AqN1

d)(1

)(E

)(V)(E xx

A

F

A

2A

qN

)(2ε2

qN

)(ε2

2ε

qN)0(V)s(

sxxx dd

2AA

ε2

qNN

ε

q )E(- )V( xxdxdxxx As ,

Fsdx 2qNε2qNQ AAB

Fsox

FFBTC

VV 2qNε21

2 A

3.14

)2qNε21

2 (A BSFsox

FFBT VC

VV

)0(

qNε2

)22(

0

0

As

BSTT

ox

FBSFTT

VVVC

VVV

: body effect constant

VBS = Bulk(Substrate) to Source (reverse) bias voltage

3.15

Surface Conditions : Accumulation - Flat-Band - InversionV<VFB V=VFB V>VT

1) V=VFB

2) V=0

3) V=VT

4) V>VT

1)

2)

3)

4)

xdXd,max

1, 2 : immobile charge(ionized impurity)3, 4 : mobile charge(electron)

3.16

Capacitance-Voltage Plot (C/V Plot)

+_

vi

V

C

R

vo

vo -jRCvi

voC

Low frequency, or MOSFET structure

VT V

C

High frequencypulsed V(deep depletion)

( <<generation rate)

n+

p

Thermal generation of e,h-pair n+ diffusion: prompt supplier of electron

3.17

4. Ideal MOSFET I/V Relations

n+

p-sub

n-ch MOSFET

n+

p+

n-sub

p-ch MOSFET

p+

3.18

Enhancement-type MOSFET vs. Depletion-type

VDD > 0 VDD < 0

VGS > 0 VGS < 0

ID < 0ID > 0

VGS

ID

(NMOS)

(NMOS)

(PMOS)

(PMOS)

ID

ID

ID

VGS

VGS

VGS

VT > 0

VT < 0

VT < 0

VT > 0

Enhancement

NMOSDepletion

PMOS

3.19

MOSFET I/V Relation

LW

N+ N+

i) cutoff region ; VGS <VT

ID=0

ii) nonsaturation(or triode) region ; VGSVT, O<VDSVGS-VT

DrainSource

Gate

Qn=Cox(VGS-VT) Qn=Cox(VGS -VT-VDS)

Qn(X)=qCOX(VGS-VT-V(X))

IDS=WnQn(x)

dV(x)

dx

Qn(x) : #of electrons per unitsurface area

n : electron mobilityV(x) : surface potential at x

3.20

Integrating both sides ofIDS=WnQn(x)

dV(x)

dx

I dx qW C V V V x dV xDSo

L

n ox

V

GS TDS

0[ ( )] ( )

22

2

2

)(2

)]([2

],2

)[(

]2

)[(

TGSTGSDS

DSDSTGS

DSDSTGSoxn

VVVVV

VVVV

VVVV

L

WCq

IDS

where ( ) ( ) ( )q CW

Ln ox

Material process

Layout geometry

Pinch-offpoint

Short

Long-channel

(VGS-VT) (VDS)

IDS

2

2( )V VGS T

3.21

ii) Linear Region, VDS (0.1V)

IDS=(VGS-VT)VDS : analog multiplier

iii) Saturation Region

- MOSEF is called Square-Law Device

- Remember =qnCoxW/L, where n

VGS

VDS

IDS

I V V VV

V V VDS GS T DSDS

DS GS T [( ) ]

2

2

I V VDS GS T 2

2( ) , For VDSVGS-VT : indep. of VDS

n

GS TV V0

1 ( ) (surface scattering)

Actually less than square

3.22

i) Pinch-off in long-channel device

ii) Velocity saturation in short-channel device

Two causes for current saturation

Source Drain

pinch-off point depletion region

vsatv v=

Ecrit

E

v=critv=vsatcrit

3.23

5. Actual MOSFET(Secondary Effect)

Threshold voltage variations

i) Body effect(Substrate bias) :

ex.1 Series-connected MOSFET’s

- NMOSFET in 2-input NAND-gate

- PMOSFET in 2-input NOR-gate

VT of A-NMOS & VT of A-PMOS depend on VY

A

B

VDDX

YA B

XY

VDD

V V VT T F BS F 0 2 2 ( )

3.24

ii) -VT due to Short-Channel effect

iii) +VT due to Narrow-Channel effect(?)

1

QB : (effective) charge per unit surface area

L(channel length)

VT

1

V VQ

CT FB FB

OX

2 V VQ

CT FB FB

OX

2

3.25

iv) Drain-Induced Barrier Lowering(DIBL) ; for small L

can lead to Punch-through

ex. DRAM cell leakagecurrent depends on the voltageon the data line

pn+ n+ n+ n+p

S

VT

VDS

3.26

Channel Length ModulationLMASK

L

LXj

Xj

: )1(

11

11

11

2

2

0,

111

DSDSDS

DSDS

TGSDSA

s

eff

jMASK

VII

VLL

V

LL

LL

LLI

VVVqN

L

LLL

XLL

LAMBDA(SPICE Level1 modelparameter)

=

VDS

3.27

Subthreshold Current

Actually MOSFET is conducting also below VGS < VT ;

Subthreshold or weak inversion condition

ID ~ exp , Vth = , 0 < < 1

Reducing VT according to VDD down - scaling yields high subthreshold current.

VV

GS

th

kTq

I V VGS T~ ( ) 2

ln ID

VGS

I ExpV

VGS

th

~ ( )

3.28

Effect of Source, Drain Resistance

RS = · R + RC

LS

W

RC : contact resistance

R : sheet resistance

RSRD

ID

VDS

Silicidation reduces polysilicon gate resistanceas well as RS, RD

+ -RS

VGS

RD

3.29

Hot Electron Effect ;

For submicron MOSFET, electron becomes “hot” due to strong E(electric field) 104 V/cm = 1V/m

E is very high near the drain junction

LDD(Lightly-Doped Drain) MOSFET is effective for reducing the E-field near drain junction.

Hot electron captured in the gate oxide through tunneling causes VT instability(threshold drift).

n+ n+ n+ n+

n-

LDD-MOSFET

3.30

CMOS Latchup

i) When Rnwell = Rpsubs = 0

latchup is impossible

ii) When Rnwell = Rpsubs =

n p 1 causes latchup

iii) When 0 < Rnwell, Rpsubs <

n p ( >1) causes trouble

3.31

6. CMOS Process

Snapshot of IC fabrication process

3.32

Step1 : Crystal growing(Czochralski’s method)

2 : sawing

3 : CMP(Chemical-Mechanical Polish)

4 : SiO2-layer growth/Deposit(CVD) or Sputtering of poly, SiO2, Si3N4, Al

5 : Resist Spin Coat

6 : mask exposure

7 : Resist develop

8 : Oxide etch(using plasma/ion/wet)

9 : Ion Implant for Impurity doping

10

11 : Strip Resist

12 : Strip Oxide

Repeated12-20 timesfor a CMOS

process

3.33

Cross-section of MOSFET showing each layerLOCOS(or Isoplanar) Process for PMOSFET

3.34

1. Field Implant

2. Grow Field Oxide

& Remove Nitride

3. Form Poly Gate : deposit, dope, mask & etch

4. Form Source/Drain for

n-channel MOSFET &

n-type substrate contact

5. Form Source/Drain for P-channel MOSFET & P-type substrate contact

MOSFET Formation Process

+ + + + + +p-SiSiO2

Si3N4

+ + + + ++ Channel Stop

3.35

Basic N-well CMOS Process

3.36

Cross-section of CMOS Inverter in N-well CMOS Process

3.37

Substrate & Well Contacts

3.38

Twin-well CMOS

3.39

CMOS Process Layers

Via 1

3.40

Mask layer drawn

N-well = not(P-well) n-diffusion(silicon)={CAA(mask)

Active = Pdiff + ndiff CSN(mask)}

n-diffusion implant = grow(ndiff) ( CPG(mask)

P-diffusion implant = grow(Pdiff)

3.41

3.42

Sheet Resistance

W L

t

RL

W tLW t

LW R

layout geometry process

3.43

Reducing R with Silicide

Silicide : a metallic compound of silicon

i) polycide : reduces Rg

ii) salicide : reduces Rg, Rs and Rd

poly-Si Metal(Ti,W,Ta,Co)

deposit,sinter &

etch silicide

3.44

Multi-Level Metalization issues

Planarization of surface using CMP(Chemical-Mechanical Polishing)

insulating glass

rough surfaceflat surfaceafter grinding

with slurry

3.45

Inter-Level Interconnect I) diffusion contact/polysilicon contact using barrier metal(platinum)

ii) contact plug or via plug : Tungsten

iii) sandwiched metal layer : TiW/AlCu/TiW

3.46

7. CMOS Layout Design Rules

-based design rule : all dimensions rep. as integer times , scalable.

ex. Mead-Conway rule, MOSIS rev. 4-6

m-based design rule : some dimensions are not scalable.

ex. Most company(foundry), MOSIS rev.7

mixed(+) design rule :

3 types of design rules FEOL(Front End of the Line) ;

BEOL(Back End of the Line) ; metal interconnect

Glass layer

3.47

3.48

3.49

3.50

3.51

8. SPICE Model for MOSFET

SPICE originally developed at Univ. Berkeley

now many versions are available, e.g.,HSPICE, PSPICE, SmartSPICE, AIMSPICE, …

Models for R,L,C, V&I source, diode, BJT, JFET, MOSFET, Transmission lines, MOSFETs, and Macros(Behavioral models), etc.

Levels Level1(Schichman-Hodges Model): Simple, fast, good timing

Level2(Grove-Frohman Model): Short, narrow channel effect, slow, convergence poor

Level3(Empirical Model): Faster than Level2 while as accurate, convergence OK

Level13(BSIM Model): Now most widely used

Level27:SOS Model

3.52

MOSFET is defined by MOSFET model + element parameters,

CAPOP model parameters; gate capacitance

ACM(Area Calculation Method) model parameters: diode model

Model selection: each MOSFET is described by element & .MODEL statement

ex) M3 3 2 1 0 PCH .MODEL PCH PMOS LEVEL=13 <parameters>

Analysis: DC, transient, AC, and noise DC, transient analysis: same except the inclusion of capacitances

AC & noise analysis: replace Ids by gm, gds & gmbs

where gm= , gds=Ids

Vgs

Ids

Vds

3.53

Equivalent Circuit MOSFET Transient Analysis

3.54

Equivalent Circuit, MOSFET AC Analysis

3.55

MOSFET AC Noise Analysis

3.56

LEVEL 13 BSIM Model

Berkeley Short Channel IGFET Model(BSIM)

VT = VFB + B + K1 B+VSB - K2(B+VSB) + VDS

Sub-threshold current: calculated when NO(ZNO) < 200

Ilim*Iexp

Ilim + Iexp

IDS = : (weak-inversion current)

IDS = IDS,S + IDS,w : (continuous 1st derivative bet. strong & weak inversion region)

3.57

Geometry-sensitivity Factors for Parameter Processing

A = A+ LA0( - ) + WA0( - )

ex) VFB = - 0.35(volt), LVFB0 = - 0.1(volt*micron),

WVFB0 = 0.08(volt*micron)

LREFeff = 2 micron, WREFeff = 10 micron

zvfb = VFB + LVFB0 + WVFB0

– Model parameters processed according to the device size start with ‘z’ follo

wed by the parameter name

Bias-Sensitivity Factors( start with ‘’ )

xu0= zu0 - zx2u0 vsb

xu1 = zu1 - zx2u1 vsb + zx3u1 (vds - VDDM)

1Leff

1LREFeff

1 1weff WREFeff

3.58

3.59

이 시대는 정보화시대라고 한다 . 이 시대에는 모든 사업의 성패가 적절한 정보의소유정도에 달려 있다 . 많은 사람들은 자기에게필요한 정보가 매우 얻기 힘들고 , 그것만 얻으면모든것이 다 해결된다고 생각한다 .이들은 자기가 이미 갖고 있는 정보를 다듬고생각하여 활용하는 것 보다는 ,오로지 쓸데도 없는 새로운 정보를 찾아숱한 시간을 날린다 .

이 시대는 정보화시대라고 한다 . 이 시대에는 모든 사업의 성패가 적절한 정보의소유정도에 달려 있다 . 많은 사람들은 자기에게필요한 정보가 매우 얻기 힘들고 , 그것만 얻으면모든것이 다 해결된다고 생각한다 .이들은 자기가 이미 갖고 있는 정보를 다듬고생각하여 활용하는 것 보다는 ,오로지 쓸데도 없는 새로운 정보를 찾아숱한 시간을 날린다 .

정보의 허상을좇는 것

정보의 허상을좇는 것

3.60

자기가 도저히 얻을 수 없는 정보나사람 , 혹은 매우 구하기 어려운정보나 사람이 없어서사업이 안 된다고 생각하는 사람을운명적 비관론자라고 부른다 .

자기가 도저히 얻을 수 없는 정보나사람 , 혹은 매우 구하기 어려운정보나 사람이 없어서사업이 안 된다고 생각하는 사람을운명적 비관론자라고 부른다 .

비관의 자유 (?)비관의 자유 (?)