ece 340 lecture 33 mos capacitor threshold voltage
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ECE 340 Lecture 33 MOS capacitor Threshold Voltage. Inversion: at V > V T (for NMOS), many electrons drawn to surface, which is now “inverted” vs. the p-doped substrate. Draw charge distribution: Draw energy bands at inversion:. Note: - PowerPoint PPT PresentationTRANSCRIPT
© 2012 Eric Pop, UIUC ECE 340: Semiconductor Electronics 1
ECE 340 Lecture 33MOS capacitor Threshold Voltage
•Inversion: at V > VT (for NMOS), many electrons drawn to surface, which is now “inverted” vs. the p-doped substrate. Draw charge distribution:
•Draw energy bands at inversion:
© 2012 Eric Pop, UIUC ECE 340: Semiconductor Electronics 2
Note: Mobile charge anywhere is given
by difference between EC or EV and Fermi level as, e.g. n = NCexp(EC – EF)
If EF is close to EC then lots of __________________
If EF is close to EV then lots of __________________
• At high gate V (> VT) which band is closer to EF?
• The condition for this onset is ϕS = 2ϕF (see plot)
qVi
A
FSiT
i
AFS
qNWW
nN
qkT
)2(2
ln22
© 2012 Eric Pop, UIUC ECE 340: Semiconductor Electronics 3
• At inversion (on p-type sub.) the mobile surface charges are ______________, such that numerically nsurf. = NA,sub.
• Now we can calculate the threshold voltage, VT: For NMOS (electron inversion on p-type substrate):
For PMOS (hole inversion on n-type substrate):
Net surface charge in inversion layer?
2 A si SG FB S i FB S
i
qNV V V V
C
2 (2 )2 A Si F
T FB Fi
qNV V
C
0)/ln( iAF nNqkT
2 22 D Si F
T FB Fi
qNV V
C
ln( / ) 0F D ikT N nq
( )inv i G TQ C V V
© 2012 Eric Pop, UIUC ECE 340: Semiconductor Electronics 4
• This is a good place to recap MOS capacitor behavior:
• Since this is a capacitor, whatdoes the C-V measurement look like?
V = VFBV < VFB VFB < V < VT VT < V
© 2012 Eric Pop, UIUC ECE 340: Semiconductor Electronics 5
© 2012 Eric Pop, UIUC ECE 340: Semiconductor Electronics 6
•MOS capacitance measurement:
ECE 340 Lecture 34MOS Capacitance-Voltage (C-V) curve
vac
iac
C-V Meter
Si
GATE
MOS Capacitor
G
s
G
GATE
dVdQ
dVdQC
dtdvCi ac
ac
© 2012 Eric Pop, UIUC ECE 340: Semiconductor Electronics 7
• Why is there a difference in inversion capacitance at: Low-frequency (<10 kHz) High-frequency (~1 MHz)
• Answer:
Cox
gate
p-type Si
-
WTAC
DC
Cox
gate
p-type Si
Cox
gate
p-type Si
Cdep W
Cox
gate
p-type Si
WT
N+
DC and AC
Accumulation: Depletion:
Inversion:
Cdep,min
++ + + + +
-- - - - - -- - - - -
Case 1 Case 2
Ci Ci
CiCi
© 2012 Eric Pop, UIUC ECE 340: Semiconductor Electronics 8
• Inversion case I: inversion-layer (minority carriers!) can be supplied quickly to respond to changes in VG
• How do we supply them?1) Optical generation (turn lights on)2) Providing a nearby source of
minority carriers (like in a MOSFET)
• Inversion case II: inversion-layer cannot be supplied quickly enough to respond to changes in VG
M O SDQ
DQ
Cox
WT
oxG
inv CdVdQC
Time required to build inversion-layercharge = 2NAto/ni , where to = minority-carrier lifetime at surface
M O SDQ
DQ
WT
Cox Cdep
min
1)2(21
1
111
CqNC
WC
CCC
SiA
F
ox
Si
T
ox
depox
Ci
Ci
Ci
Ci
Ci
Ci
© 2012 Eric Pop, UIUC ECE 340: Semiconductor Electronics 9
• Ex: plot and label the C-V curve of a PMOS capacitor with P+ gate, substrate doping ND=5x1017 cm-3 and SiO2 d=2 nm
© 2012 Eric Pop, UIUC ECE 340: Semiconductor Electronics 10
• MOS capacitor non-idealities… in reality, neither the SiO2 nor the Si/SiO2 interface are perfect: Mobile ions (Na+ used to be a major headache) Dangling bonds at Si/SiO2 interface Charge traps within SiO2
• We can group these non-idealities together as an equivalent sheet of charge Qi (>0) at the Si/SiO2 interface
• + charge at the interface pulls down the E-bands there and changes the field across the SiO2
• This shifts the flat-band voltage:
iFB MS
i
QVC
© 2012 Eric Pop, UIUC ECE 340: Semiconductor Electronics 11
• Odd shifts in C-V characteristics were once a mystery:
• Source of problem: Mobile ionic charge (e.g. Na+, K+) moving to/away from the interface, ΔVFB = Qi / Ci
• Solution: cleaner environment, water, chemical supply.
• With simple C-V measurements we can learn (and “debug”) a great deal about the properties and quality of MOS capacitors: Obtain oxide thickness (d) from C accumulation Obtain substrate doping (NA) from Cmin at VT (high-freq) Interface charge (Qi) and VFB from C-V across various dox thicknesses
© 2012 Eric Pop, UIUC ECE 340: Semiconductor Electronics 12
• MOS capacitor wrap-up:
• Experimental measurement of fast interface states (traps):
Ci
© 2012 Eric Pop, UIUC ECE 340: Semiconductor Electronics 13
• A little more on the real measured C-V curve:
• Effective oxide capacitance affected by: Poly-silicon gate depletion (no problem with metal gate) Finite thickness of inversion layer
• Both of which are somewhat functions of voltage.• Last but not least:
Why HfO2 instead of SiO2? Why metal gate instead of highly-doped poly-Si gate?
CBasic LF C-V
with gate-depletion
with gate-depletion and charge-layer thickness
VG
data
Cox
33,invpoly
effoxWW
dd
Ci