3 rd june 2013, talent summer school, cern basics of ic design miroslav havránek

3rd June 2013, TALENT Summer School, CERN

Basics of IC design

Miroslav Havránek

M. Havranek, University of Bonn 2

Integrated circuitElectronic device PCB Integrated circuit

InterconnectionIntegrated circuit - core Transistor


IC design in HEP

~ 100 000 000 read-out channels

~ 1 000 000 000 collisions every second

~ 80 M pixels~ 6.4 M strips

Radiation hard Low power High speed Low mass electronics Long term reliability

Hard to meet with commercial electronics !!!

Large Hadron Collider Experiment ATLAS

Requirements for FE electronics:


Why doing IC design?

IC Design = maximum freedom of adjusting parameters of the

electronic circuit to meet the specification

= freedom of technology choice

A pplication

S pecific

I tegrated

C ircuit

Large integration density Scaling Low power Low cost Most of modern electronics is fabricated by CMOS

High speed – low noise applications High power consumption Low density integration Typical applications: TTL logic, OpAmps,

discrete components Widely used in the past

Bipolar technologyBipolar technology CMOS technologyCMOS technology


CMOS technology

CMOS technology uses MOSFET transistors

of both types: NMOS, PMOS

Bipolar transistor only parasitic (poor parameters)

Low cost (in large scale production)

High integration density

Scaling

- smaller transistors

- higher complexity

- higher power density

1947 20112006 2013 ?

14 nm


Silicon foundry

IC fabrication requires clean environment

-> clean rooms

Ordinary room 500.000 – 1.000.000 in m3

Clean room in silicon foundry

~100 particles in m3


Electronic components in CMOS technology

Active components - MOSFET transistors

- parasitic bipolar transistors (poor parameters)

CMOS technology is optimized for fabrication of NMOS and PMOS transistors,

passive components have limited performance (precision, linearity)

Passive components

- resistors

- capacitors

- inductors (used in RF application)

- diodes

Hard to integrate large capacitors (> 10 pF) and large resistors (> 50 kΩ)


Anatomy of MOSFET Transistor

High purity Monocrystalline silicon substrate <100> (epi-layer)

Channel

Polysilicon gate

Gate oxide SiO2 (thickness ~ several nm)

P-well contact

Drain contact Source contact


Inversion layer and threshold voltage

Vgs = 0 N+ P-WELL junction – depleted region by diffusion

Vgs > 0 (but small) -> depletion of bulk under gate, accumulation of minority charge carriers

Vgs > (100s mV) concentration of electrons is equal to concentration of holes

Vgs = Vt ….. Vt is threshold voltage

Vgs > Vt – inversion layer (conductive channel)

if Vds > 0 current between drain and source


NMOS and PMOS transistors

D

SG

D

SG

NMOS

PMOSB

B

MOSFET is 4-terminal device


NMOS transistor - a closer look

Saturation region

DSTGSOXND VVVL

WCI 12

DSDS

TGSOXND VV

VVL

WCI

2

Linear region VGS > VT, VDS < VGS - VT

- transistor operates in linear region

- transistor behaves as a resistor

VGS > VT, VDS > VGS – VT

- transistor operates in saturation

- transistor behaves as a current source


NMOS transistor - closer look

Weak inversion region

Tkm

qV

OXD

GS

eL

WCI

VGS < VT

- sub-threshold region

- drain current depends exponentially on VGS

- low power applications

TGSOXnGS

Dm VV

L

WC

V

Ig

Transconductance

DDS

D

OUTDS I

V

I

Rg

1Output conductance

Transconductance can be adjusted by changing

aspect ratio of transistor dimensions

λ … channel length modulation parameter

short channel transistors have large λ


Resistors in CMOS technology

Metallic resistor

- ρsq ~ 100 mΩ/sq lw

W

lR sq

Diffusion resistor

- ρsq ~ 10 Ω/sq

- non-linear, shielded from substrate

Polysilicon resistor

- ρsq ~ 10 Ω/sq

- linear

polysilicon metal

N-well resistor

- ρsq ~ 1 kΩ/sq

- non-linear, not shielded from substrate


Capacitors in CMOS technology

MOM – Metal Oxide Metal

- parasitic capacitance between metals

- small capacitance density

~ 50 aF/µm2

< 90 nm > 90 nm

MIM – Metal Insulator Metal

- parasitic capacitance between two

metal layers separated by thin

(~100nm)insulator layer

- large capacitance density ~ 1fF / µm2

METAL 1

METAL 2

Thin oxide layer

METAL

MOSCAP

- capacitance between gate and substrate

- large capacitance density ~ 5-10 fF / µm2

- non-linear behavior


Fabrication of MOSFET transistors - photolitography

2. Photoresist deposition

1. Deposition of silicon oxide and nitride

3. Illumination of the photoresist through the mask

5. Filling isolation trenches with SiO2

6. Ion implantation (Phosphor ~100 keV) -> N-well formation

4. Removing illuminated photoresist, etching silicon nitride,

etching isolation tranches in silicon


Photolitography7. Ion implantation (Boron ~100 keV) -> P-well formation

8. N-well and P-well are ready for implementing

NMOS and PMOS transistors

9. Gate oxide deposition

10. Deposition of polysilicon

11. Photoresist deposition, illumination through mask

12. Gates are formed


Photolitography13. Low energy implantation of Boron dopants -> forming P+ regions of drain and source

14. Low energy implantation of Phosphor dopants -> forming N+ regions of drain and source

15. Removing photoresist and oxide from source and drain

16. Silicidation

16. BPSG deposition

17. Etching, vias, deposition of METAL1, BPSG isolation


Design SoftwareIC = Complex systems of many components and interconnections

=> high level of automation is needed for

design and simulations

EDA – Electronic design automation

Design software : Cadence Virtuoso

- schematic editor

- simulation tools ADE…

- place and route tools (Encounter)

- layout editor

Process Design Kit:

-Libraries with electronic components

-Models of electronic components

-Customization of design environment

-Design rules

-Process documentation


Analog vs Digital design

Aspects of analog design Aspects of digital design

Functionality is described by schematic Functionality is described by HDL (Hardware Description Language)

Continuous quantities: voltage, current, bandwidth, noise Discrete quantities: logical states (“1” or “0”)

Basic building block is NMOS, PMOS, R,L,C or diode Basic building block is a gate (flip-flop, and gate, or gate….)

Design complexity: ~10-1000 components Design complexity: up to millions of transistors

Place and route is done by hand (or semiautomated) Place and route is automated

Scaling is difficult Scaling is easy

Analog circuit Digital circuit


Analog design flow

SpecificationSpecification Schematic capture

Schematic capture

SimulationSimulation

Does it meet

specs?

Does it meet

specs?

Corners & MC simulation

Corners & MC simulation

Does it meet

specs?

Does it meet

specs?

Layout Capture

Layout Capture

Post-layout simulation


Tape-Out

YES

NO

YES

NO

Does it meet

specs?

Does it meet

specs?

YES

NO

DRC/LVSDRC/LVS

OK?OK?NO


Digital design flow

SpecificationSpecification HDL designHDL design

Behavioralsimulation

Behavioralsimulation

Does it meet

specs?

Does it meet

specs?

SynthesisSynthesis

Place and route

Place and route



Tape-Out

YES

NO

YES Does it meet

specs?

Does it meet

specs?

YES

NO

DRC/LVSDRC/LVS

OK?OK?NO

ConstraintsConstraints


Design rules

IC – complex system of millions of transistors, interconnections, vias => all of them have to work!!

IC designer have to follow design rules provided by manufacturer and general rules of CMOS design

General design rulesGeneral design rules Process specific design rulesProcess specific design rules

Design for manufacturabilityDesign for manufacturability

- Provided by manufacturer

- EDA allows DRC check to avoid design rule violation

- 100s, in modern processes 1000s of design rules

- Distances between metals, transistors, wells etc.

Yield of IC production can be significantly improved by proper layout

- Folding of large transistors

-Minimizing mismatch effects

-Separation of analog and digital power lines


Process specific design rules


General design rules

Thickness of gate oxide in modern CMOS technologies ~ several nm

MOSFET is ESD (Electrostatic discharge)

Typical operating voltage in deep submicron technologies < 2V

Typical ESD event ~ several kV from capacitance of ~ 100 pF

Transistors must be protected from high voltage from outside

=> ESD protection is part of IO pads

Antenna effect - long metal routes can accumulate

charge during processing

changing metal layers using antenna diodes


General design rules

Transistor folding

- transistors with large aspect ratio W/L are often

folded in many-finder layout

- layout is more compact

- drain and source area reduced -> CSB, CDB smaller

- gate resistance is smaller -> transistor is faster

Transistor mismatch Common centroid design

Use appropriate metal width for high current lines

- max current density ~ 1 mA / um width … usually we use much smaller current density

- don’t use single vias !!

Dummy transistors


Example design - invertor

Specification:

- design an invertor in 65 nm CMOS technology, VDD power supply = 1.2V

- switching frequency 500 MHz, load capacitance = 50 fF

- rise-time = fall-time < 100 ps

- power consumption < 45 µW

W/L=200n/60nl

W/L=200n/60nl


Test-bench and simulations

CLOAD = 0 fF

tRISE = 4.2 ps

tFALL = 6.5 ps

Power = 0.27 µW

… but what if CLOAD = 50 fF ??

INPUT

OUTPUT


CLOAD = 50 fF

tRISE = 230 ps

tFALL = 305 ps

Power = 31.6 µW

… transistors don’t provide enough driving current -> increase W/L

CLOAD = 50 fF

tRISE = 75 ps

tFALL = 75 ps

Pwr = 39 µW

Meets specs !!

Test-bench and simulations

W/L=3.5µ/60n

W/L=1.6µ/60n

INPUT

OUTPUT

INPUT

OUTPUT


Process variations -> Monte Carlo simulations

POWER tR

tF


Layout

PMOS

NMOS

OUTPUT NODEINPUT NODE

P-WELL CONTACT

N-WELL CONTACT

1.9 × 4.5 µm2

3rd June 2013, TALENT Summer School, CERN

Thank you for your attention

3 rd june 2013, talent summer school, cern basics of ic design miroslav havránek

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